GB2250110A - Digital signal processing - Google Patents

Abstract

A circuit 10 for processing a digital data signal SI, such as a digital audio signal, by means of a digital control signal SC, such as that from a digitised control potentiometer, includes a signal processing section 12 and an interpolating section 14. The sampling frequency of the data signal SI is higher than that of the control signal SC and the interpolating section 14 provides an interpolated control signal SC at the data signal sampling rate. Thus each data signal sample can be processed in accordance with a corresponding interpolated control signal sample. The signal processing section 12 and the interpolating section 14 may be fabricated on a single integrated circuit. <IMAGE>

Description

DIGITAL SIGNAL PROCESSING This invention relates to digital signal processing, and in particular to the processing of digital data signals by means of digital control signals.

In digital signal processing applications, a frequent requirement is for a digital data signal to be subjected to processing in accordance with the value of a digital control signal. For example, in digital audio apparatus, a digital audio signal may need to be modified on the basis of a digital level control signal derived from a levelsetting potentiometer. The analog voltage from the potentiometer is digitised, and a digital control signal is thus obtained which can be used to alter the effective level of the audio signal as a result of multiplication of the audio signal by the control signal in a signal processor integrated circuit.A problem with this arrangement is that the sampling frequency of digital control signals derived from digitised potentiometer outputs is generally relatively low, for example 1 kHz (or lower), whereas the sampling frequency of digital audio signals is considerably higher, typically 50 kHz. Thus, in the example quoted, every 50 samples (or more) of the audio signal will be multiplied by the same control signal, even when the potentiometer setting is being changed. The effect of this is that the resulting controlled audio signal is within a modulation-type stepped envelope, the steps occurring every 1 ms, when the potentiometer setting is changed. The amplitude change between steps will depend on the rate of change of the potentiometer setting.Thus the audio signal will have superimposed thereon a 1 kHz generally square wave signal, whenever the potentiometer setting is changed, the amplitude of the superimposed signal depending on the rate of change of the potentiometer setting.

This effect is termed "zipper noise" due to its resemblance to the sound made by a zip fastener, and is clearly undesirable in audio signal processing, particularly in multi-channel audio mixing involving large numbers of level-setting (and other) potentiometers each of which can make a contribution to this damaging effect.

In order to overcome this problem, it has been proposed to use the signal processor to perform interpolation of the control signal such that, when the potentiometer setting is being changed, the control signal can change for every audio signal sample. Thus the stepped modulation envelope for the audio signal is effectively replaced by a ramp envelope more accurately representing the change to the potentiometer setting. Whereas this proposal is effective in overcoming the problem of "zipper noise", it involves the considerable disadvantage that the interpolation process is coded in software and therefore consumes a significant fraction, typically up to a half, of the available signal processing power.

According to the present invention there is provided a circuit for processing a digital data signal by means of a digital control signal, the sampling frequency of the digital data signal being higher than that of the digital control signal, the circuit comprising: an interpolating circuit portion for interpolating the digital control signal to provide an interpolated digital control signal at the sampling frequency of the digital data signal, the interpolating circuit portion comprising means for dividing the difference between sequential ones of the digital control signals into a plurality of interpolated increment signals, and means for sequentially adding the interpolated increment signals to the earlier one of the sequential digital control signals thereby to produce the interpolated digital control signal; and a signal processing circuit portion for processing the digital data signal by means of the interpolated digital control signal.

A preferred embodiment of the invention, described in greater detail below, provides on a single integrated circuit chip, a signal processing circuit portion and a separate control signal interpolation circuit portion. There is thus no reduction in the signal processing power since the interpolation of the control signal is performed in hardware.

In the preferred embodiment, the digital data signal is an audio signal, and the digital control signal is derived from a digitised control potentiometer such as by an interposed control computer. Each audio signal sample can thus be processed in accordance with a corresponding interpolated control signal sample, and this smooths out the abrupt variations present in the uninterpolated control signal.

The digital control signal is preferably in the form of an absolute value followed by a series of increment values defining variations from the absolute value. Memories are provided in the interpolating circuit portion for holding the values of the absolute value, each increment value, and the derived interpolated value.

The number of the plurality of required interpolated increment signals is preferably equal to the ratio between the data signal sampling frequency and the control signal sampling frequency.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a basic block diagram of a single chip signal processing/interpolating system according to an embodiment of the invention; Figure 2 is a more detailed block diagram of one implementation of a signal processing section shown in Figure 1; and Figure 3 is a more detailed block diagram of one implementation of an interpolating section shown in Figure 1.

The invention will be described in the context of a digital audio signal processing system, although it should be appreciated that the invention is also applicable to other digital signal processing systems in which a digital data signal is to be controlled by a digital control signal having a lower sampling rate than the data signal.

Referring to Figure 1, a single chip processing/interpolating system 10 is shown as including a signal processing section 12 and an interpolating section 14. Both the sections 12 and 14 are fabricated on a single integrated circuit chip constituting the system 10. The signal processing section 12 receives a digital input signal SI and, after suitable processing, a digital output signal SO is provided at an output of the system 10. A digital control signal, which will be referred to as a coefficient signal SC, is supplied to the system 10, typically from a digitised potentiometer and associated control system such that the coefficient signal SC is dependent on the position and/or extent of movement of the potentiometer. In the embodiment to be described, the coefficient signal SC may, under initial conditions such as following system power-up, represent a stored value of the parameter to be controlled. Thereafter, the coefficient signal SC may represent the increment of potentiometer movement detected since the previous sample. It is assumed that the sampling rate of the coefficient signal SC is lower than that of the input signal SI and, in order to avoid the signal modulation problem outlined above (namely the so-called "zipper noise" in the context of audio signal processing), the coefficient signal SC is interpolated by the interpolating section 14 to provide an interpolated coefficient signal SCI which is used to process the digital input signal SI.When digital audio signals are being processed, and the coefficient signal SC is indicative of a desired level setting, the signal processing section 12 will operate to multiply the input signal SI by the interpolated coefficient signal SCI. Assuming that the (audio) input signal is sampled at 50 kHz, and the coefficient signal SC from the digitised potentiometer control is sampled at 1 kHz, the interpolating section 14 will generate fifty interpolated coefficient signal SCI samples for each received coefficient signal SC sample. Accordingly, the digital output signal SO will show an accurate and smooth representation of any change to the potentiometer setting, rather than the 1 kHz stepped signal that would be provided without interpolation.

Figure 2 shows one implementation of the signal processing section 12 in greater detail. As shown, the signal processing section 12 broadly includes three data memories RAM-A, RAM-B, RAM-C, and an arithmetic unit 20 including a 32 x 32-bit multiplier 22 as well as a 181-type arithmetic logic unit (ALU) 214. Overload detection and shifting are incorporated for each of the multiplier 22 and the ALU 24 and are represented schematically by shifters 26,28 respectively.

Instructions to the arithmetic unit 20 use either the multiplier 27, the ALU 24 or both. The arithmetic unit 20 has three data inputs and one data output. The data inputs are connected to three respective multiplexers MUX-X, MUX-Y, MUX-Z which allow the output of any of the data memories RAM-A, RAM-B, RAM-C to feed any of the arithmetic unit data inputs. The data output is connected to a multiplexer MUX-W which selects the source of the data to be written into the data memories RAM-A, RAM-B, RAM-C. An input/output (I/O) section 30 is provided for directing the input signal SI and the interpolated coefficient signal SCI to selected ones of the data memories, and for reading out data from the selected memories to form the digital output signal SO.

The three data memories RAM-A, RAM-B, RAM-C are each preferably constituted by an identical 128 x 32-bit dual ported random access memory (RAM). A read access and a write access are possible in each machine cycle for each RAM. The three memories are completely independent and non-specific such that any piece of data may reside in any of the memories. Data may be routed from any memory to the multiplier 22, to the ALU 24 or to the I/O section 30; data from the multiplier 22; the ALU 24 or from the I/O section 30 may be destined for any of the memories.

The addressing of the three memories is such that at most four addresses are required per machine cycle, for example as shown below.

Address O Address 1 Address 2 Address 3 RAM-A ALU read RAM-B ALU read RAM-C ALU read ALU write or RAM-A OUT read or RAM-B OUT read or RAM-C OUT read or Any RAM IN write or Any RAM IN write or Any RAM IN write Depending upon the type of arithmetic instruction being performed, either two or three memories are read to provide operands for the arithmetic unit 20. I/O is permitted if only two operands are required for the arithmetic, in which case the third RAM address becomes the l/O read or write address.To explain in greater detail, consider the following examples: Multiply A by C and add B.

Address 0 - memory A read to multiplier Address 1 - memory B read to ALU Address 2 - memory C read to multiplier Address 3 - write ALU to memories determined by WRSEL field Multiply A by C and output from B.

Address 0 - memory A read to multiplier Address 1 - memory B read to I/O Address 2 - memory C read to multiplier Address 3 - write ALU to memories determined by WRSEL field Multiply A by C and input.

Address 0 - memory A read to multiplier Address 1 - write I/O to memories determined by WRSEL field Address 2 - memory C read to multiplier Address 3 - write ALU to memories determined by WRSEL field Multiply A by coefficient, add C and input.

Address 0 - memory A read to multiplier Address 1 - write I/O to memories determined by WRSEL field Address 2 - memory C read to ALU Address 3 - write ALU to memories determined by WRSEL field.

Thus the three memories are independently addressed for reads, and each machine cycle can have different ALU and I/O write addresses.

Each instruction can write its result into one, two or three data memories; however only one ALU write address is available, thus writes to more than one memory go to the same address in each memory. Each I/O input can also be written to one, two or three memories, and again only one I/O write address is available. The routing of the ALU and I/O write addresses and write enables is determined by the MEMSEL and WRSEL fields.

Address zero of these memory reads is specially decoded to control the interpolator multiplexer and thus is never read.

The four address fields occupy 28 consecutive bits in the instruction word and can be independently loaded as a single entity.

With reference to the arithmetic unit 20, two of the data inputs (X & Y) provide direct inputs to the multiplier 22. The 64-bit output from the multiplier 22 is examined for overflow and subjected to a shift controlled by the microcode word to produce 32 output bits.

There are also two inputs to the ALU 24, a direct data input Z and another which is either X or the shifted output of the multiplier 22, dependent on a selector 32. There is also overload detection on the ALU 24 represented by the shifter 28. The multiplexer MUX-W after the ALU 24 selects the data to be written back into memory. It can be X, Z, shifted multiplier output, shifted ALU output, +1 or -1.

Some instructions are not symmetrical about the two memories constituting primary arithmetic RAMs. Multiply coefficient add out is one example, because A*coefficient + B is not the same as B*coefficient + A. All instructions which are non-symmetric in this way have a corresponding reversed instruction, for which the orientation of the two primary arithmetic RAMs is reversed.

The arithmetic unit 20 implements the following basic types of function.

(i) Multiply instructions.

During multiply instructions, the two 32-bit 2's complement values presented on the inputs X and Y of the multiplier 22 are multiplied to give a 64-bit product. From this number, 32 bits are selected using the shifter 26, the quantity of shift being controlled from the instruction word. The unused bits at the most significant end of the product (due to the shift required) are examined and are used to cause saturating overflow. This is a two input instruction, thus an input/output or DRAM access may occur during the same machine cycle.

These are symmetric instructions.

(ii) Multiply arithmetic instructions.

During multiply arithmetic instructions, the two 32-bit 2's complement values presented on the inputs X and Y are multiplied to give a 64-bit product. From this number, 32 bits are selected using the shifter 26, the quantity of shift being controlled from a restricted field of the instruction word such that shifts of from 0 to 15 places are available. The unused bits at the most significant end of the product (due to the shift required) are examined and are used to cause saturating overflow. The resulting 32-bit number forms one input to the ALU 24, and the input Z to the arithmetic unit 20 forms the other. The ALU 24 may be configured to add, subtract or perform a reverse subtract. The resulting 33-bit number (due to carry whether adding or subtracting) may be shifted by one position under program control, and saturating overflow applied. These are three input instructions, thus no input/output of DRAM access may occur during the same machine cycle. These are symmetric instructions.

(iii) Multiply arithmetic coefficient instructions.

These instructions behave in the same manner as "Multiply arithmetic instructions" except that the input Y is always a coefficient. These are thus two input instructions, in the sense that they require only two read addresses for the arithmetic part thus allowing a possible input/output or DRAM access during the same machine cycle. These instructions also have a restricted shift range of O to 15. These are non-symmetric instructions, and there are corresponding "reversed" instructions.

(iv) Arithmetic instructions.

During arithmetic instructions, the values from the inputs X and Z are directly connected to the ALU 214. The input X by-passes the multiplier 22 by way of the selector 32 to feed directly to the ALU input which was previously connected to the multiplier shifter output, while the input Z remains connected as for multiply ALU instructions.

The instructions available are add, subtract, max, min, abs (the same value is presented to both inputs). The resulting 33-bit number may be shifted by one position under program control, and saturating overflow applied or may remain unshifted with non-saturating overflow applied.

These are two input instructions, thus an input/output or DRAM access may occur during the same machine cycle. These are symmetric instructions.

(v) Logic instructions.

During logic instructions, the ALU 24 is connected to the inputs as for arithmetic instructions. The instructions available are AND, OR, EX-OR and NOT. These are two input instructions, thus an input/output or DRAM access may occur during the same machine cycle.

These are symmetric instructions.

(vi) Multiplexer instruction.

The output of this instruction is either the value from the input X or the value from the input Z depending upon the sign of the value of the input Y. This is a three input instruction, thus no input/output or DRAM access may occur during the same machine cycle. This is a nonsymmetric instruction. An instruction MUX will select the input X if Y is positive and the input Z if Y is negative. An instruction MUX-REV will select the input Z if Y is positive and the input X if Y is negative.

(vii) Conditional write instruction.

The conditional write instruction serves as a form of multiplexer instruction which requires only two input values and hence two read addresses. The sign of the value at the input Z determines whether the value on the input X is written to the output or whether no write is performed (and the previous value present at the memory address selected for wiring is undisturbed). This is a two input instruction, that an input/output or DRAM access may occur during the same machine cycle. This is a non-symmetric instruction. An instruction CONDWR will write the value of the input X if Z is positive and inhibit the write if Z is negative. An instruction CONDWR-REV will not perform a write if Z is positive and will write the value of the input X if Z is negative.

(viii) Interrupt Generation Under program control, a control computer interrupt may be produced, dependent upon the condition of a specified memory. A means is provided whereby the control computer may determine the identity of the instruction causing the interrupt.

Referring to Figure 3, the second part of the system chip is the coefficient interpolating section 14, which allows individual coefficient values to be changed using linear interpolation from their present value to a new value over a coefficient sample period. The start time of this interpolation is synchronised to one of a number of global "coefficient sample rates". The interpolation processor functions at the rate of one coefficient processed per two signal processing section ticks. The interpolating section 14 is designed to cover a range of coefficient sample rates required for manual control updates and automation system inputs. Coefficient interpolation times outside this range which are required for editor type cross fades in audio signal processing are generated explicitly by signal processor computation.A special mode is also provided allowing immediate update with no interpolation.

The data received by the interpolating section 14 is in the form of "absolute" and "incremental" values. An absolute value is representative of the actual desired coefficient, whereas an incremental value represents the amount by which the coefficient is to be changed.

The interpolating section 14 contains three memories which are linked by various arithmetic functions, the memories comprising a new increment (NI) memory 140, an increment (I) memory 42, and a present value (P) memory 144. The interpolating works in a pipelined and interleaved fashion. The memories execute alternately read and write cycles (although the write cycles are not always active). For a particular coefficient, the data is first read during tick N, is processed during ticks N+1 to N+14 and is possibly re-written during tick N+5, where N is an even number. Thus reads take place on even ticks and writes on odd ticks.

An input to the interpolating section 14 for the coefficient signal SC from the control bus is connected via an adder 146 to the NI memory 40. An output from the NI memory 40 is connected to another input of the adder 146. The I memory 142 is connected to receive data from the NI memory 40. The P memory 44 is connected to receive data from the I memory 42 via a barrel shifter 48 and an adder 50, an output from the P memory 1414 being connected to another input of the adder 50.

The interpolated coefficient signal SCI is read out from the P memory 1ivy.

The NI memory 140 has a capacity of 256 words of 34 bits. The NI memory 140 is read during even cycles for internal use. When the coefficient sample time indicated for this new increment occurs, the contents of this memory are transferred to the I memory 142. This transfer may involve some computation to compensate for multiple loads during a single coefficient sample period.

A coefficient is 32 bits long. The maximum slew is twice the full scale so an extra bit is needed in the NI memory 40 to accommodate this range. Also, another extra bit is necessary to accommodate a range of coefficient sample rates that is not limited to a simple power of two. Thus the NI memory 40 needs to be 34 bits wide. An 'absolute' flag is also associated with each location, and this will be explained below.

The NI memory 140 is written directly with the coefficient signal SC, generally from a control computer. Each access from the computer is only 32 bits wide, so to prevent the necessity of dual accesses for 314-bit data, address space decoding is incorporated. There are four (consecutive) address spaces to which 32 bits can be written and this maps to one memory which is 34 bits wide. There is also a fifth address space which is decoded as 'absolute' and which will set the absolute flag for that location. (Absolute updates are only 32 bits wide.) The I memory 142 has a capacity of 256 words of 34 bits.It either contains the increment by which the present coefficient value is to change at each sample period or, if in absolute mode, it contains the value to which the present coefficient value should be changed immediately.

The P memory 44 has a capacity of 256 words of 1414 bits, the 32 most significant bits (MSBs) of which contain the present value of the coefficient. It is read every even cycle and written with a new value every odd cycle. The P memory 1414 needs to be larger than 32 bits to accurately compute slow slews. Assuming that the lowest coefficient sample rate of the range is 12 Hz, the slowest slew time is 1/4096 of 148 kHz and so needs 12 bits of extra range. Hence the P memory 44 is 1414 bits wide.

The interpolation arithmetic processing of the circuit shown in Figure 3 is divided into three parts. That which is used at the time a new value is loaded from the control computer is called the 'load' circuitry; that which is only used at the start of a new coefficient sample time is called the 'transfer' circuitry; and that which is used once per coefficient at every sample is called the 'running' circuitry.

Dealing initially with the load circuitry, two types of action occur when the control computer loads new coefficient data into the interpolating section 14. These are referred to as absolute and incremental loads. An absolute load will have the effect of setting the coefficient to a known value in an un-interpolated (immediate) way at the next coefficient sample period. This type of load is used to reset the interpolator at the start of program execution, or to provide instantaneously changing coefficients. An incremental load provides a new increment which, if added to the present value, would make it go to the new required value if added to the present value once per sample for one coefficient sample period. During normal action of the controlling program a maximum of one load happens for each coefficient for each coefficient sample period.Should synchronisation be lost, new absolute values will replace any previously loaded value, and new incremental values will be added to previously loaded incremental values.

Loading of absolute values will be described first. An absolute value is a 32-bit quantity which will become the value of the coefficient at the next coefficient sample time. This value is placed into the NI memory 40 at load time. At the same time, an "Absolute', flag associated with this coefficient's word in the NI memory 40 is set, indicating that an absolute value is at present stored in the NI memory 40.

Loading of incremental values is carried out as follows. An incremental value is a 34-bit quantity which will become the stored increment in the I memory 42 at the next coefficient sample time. This quantity is calculated in the control computer. Before this value is placed into the NI memory 140 this memory is read to determine its present contents. If the Absolute flag associated with this coefficient's word in the NI memory 40 is set, then this load is ignored. If however (as is normally the case) the Absolute flag is clear, indicating that the present contents of the NI memory 140 should be interpreted as an increment, then the new value is added to the present contents by the adder 46, producing the sum of the old and new increments.

Turning now to the transfer circuitry, once per coefficient sample period, the I memory 42 is loaded from the NI memory 40. An Absolute flag attached to the I memory 42 is also updated from the Absolute flag of the NI memory 140. Immediately after the transfer of data from the NI memory 140 to the I memory 142, the NI memory 140 is zeroed; this has the effect of placing in the NI memory 40 data equivalent to an incremental value change of zero, namely a "do nothing" command, which, if not overwritten by the control computer before the next coefficient sample period, will cause the interpolator to stop changing the present value.

The purpose of the running circuitry is to produce a new present value from a combination of the old present value and the increment value.

When the ADsolute flag of the I memory 42 is set, absolute running applies. The increment value is passed from the I memory 42 straight through the barrel shifter 148 to the P memory 44 in which it becomes its new value. This action is repeated until the contents of the I memory 42 change at the next coefficient sample period. No interpolation occurs when going to an absolute value.

When the Absolute flag of the I memory 142 is clear, incremental running applies. The increment value is passed from the I memory 142 to the barrel shifter 148 in which it is shifted by an amount dependent upon the ratio of the audio sample rate and the coefficient sample rate. In other words, if the ratio between audio sample rate and coefficient sample rate is R:l, the barrel shifter 148 is operative effectively to divide the increment value from the I memory 42 by R.

The resulting divided or shifted increment value is then added to the present value from the P memory 44 by the adder 50 to produce a new value for the P memory 1414. The quantity of shift combined with the value in the I memory 142 are arranged such that the current present value will arrive at the correct value at the next coefficient sample time.

Thus, to summarise the operation of the interpolating section 14 shown in Figure 3, assuming that the apparatus is in an initial condition such as following power-up, or that a different coefficient value is required to be applied to the signal processing section 12, an absolute coefficient value (from the control computer) is applied at the input of the interpolating section 14 and is loaded into the NI memory 40. An Absolute flag associated with the absolute value is also set in the NI memory 40. At the end of the coefficient sample period, the I memory 42 is loaded with the coefficient from the NI memory 140, and the Absolute flag is also transferred from the NI memory 40. After transfer of the absolute value, the NI memory 40 is zeroed. The absolute value is then passed from the I memory 142 unaffected by the barrel shifter 48 to the P memory 1414. Thus the present value held in the P memory 44 is set to the absolute coefficient value.

Once the absolute coefficient value has been supplied to the interpolating section 14 for setting in the P memory 1414, further data from the control computer is in the form of incremental coefficient values. Each increment value is added to the present contents of the NI memory 40 and then stored therein when it is established that the Absolute flag is clear. Assuming that the NI memory 140 has been zeroed, the value in the NI memory 140 will be equal to the current increment value. The increment value is then transferred to the I memory 142, as is the clear state of the Absolute flag.Accordingly, the increment value passes from the I memory 42 to the barrel shifter 148 which shifts the increment value by the required amount which is dependent on the audio/coefficient sample rate ratio. The shifted increment value is then added to the present value in the P memory 1414 by the adder 50 to form a new interpolated present value and this process will continue until the present value in the P memory 1414 has reached the value of the last coefficient as would be modified by the unshifted increment value. Thus, instead of the last coefficient being updated to its new value in a single incrementing operation, which would cause an undesired rapid step change, the last coefficient is more smoothly updated in a series of smaller interpolated incrementing operations, until the new coefficient value is reached. The series of interpolated coefficient values is supplied by the P memory 44 to form the interpolated coefficient signal SCI, which is presented to the signal processing section 12 for operating on the digital input signal SI so as to produce the digital output signal SO.

Claims (12)

1. A circuit for processing a digital data signal by means of a digital control signal, the sampling frequency of the digital data signal being higher than that of the digital control signal, the circuit comprising: an interpolating circuit portion for interpolating the digital control signal to provide an interpolated digital control signal at the sampling frequency of the digital data signal, the interpolating circuit portion comprising means for dividing the difference between sequential ones of the digital control signals into a plurality of interpolated increment signals, and means for sequentially adding the interpolated increment signals to the earlier one of the sequential digital control signals thereby to produce the interpolated digital control signal; and a signal processing circuit portion for processing the digital data signal by means of the interpolated digital control signal.

2. A circuit according to claim 1, wherein the digital control signal is in the form of an absolute value and increment values defining variation from the absolute value, the interpolating circuit portion comprising an increment memory and a present value memory, the absolute value being loaded into the present value memory and each increment value being loaded in turn into the increment memory for division into the interpolated increment signals for addition to the present value in the present value memory.

3. A circuit according to claim 2, wherein the absolute value is initially loaded into the increment memory before being transferred into the present value memory.

4. A circuit according to claim 2 or claim 3, including a new increment memory for holding a new increment value prior to transfer into the increment memory.

5. A circuit according to claim 2, claim 3 or claim 4, wherein the difference dividing means comprises a barrel shifter between the increment memory and the present value memory for shifting the increment value in the increment value memory in accordance with the number of the plurality of required interpolated increment signals.

6. A circuit according to any one of the preceding claims, wherein the number of the plurality of required interpolated increment signals is equal to the ratio between the data signal sampling frequency and the control signal sampling frequency.

7. A circuit according to any one of the preceding claims, wherein the signal processing circuit portion comprises: a plurality of memories for storing the values of the digital data signal, the interpolated digital control signal, and the processed digital data signal; and an arithmetic unit for processing the stored digital data signal and interpolated digital control signal to provide the processed digital data signal.

8. A circuit according to claim 7, wherein the arithmetic unit comprises a multiplier and an arithmetic logic unit.

9. A circuit according to claim 7 or claim 8, wherein the signal processing circuit portion includes multiplexing means for multiplexed interconnection between the memories and the arithmetic unit.

10. A circuit according to any one of the preceding claims, wherein the digital data signal is an audio signal, and the digital control signal is derived from the digitised output of a control potentiometer.

11. A circuit according to any one of the preceding claims, wherein the interpolating circuit portion and the signal processing circuit portion are fabricated on a single integrated circuit.

12. A circuit for processing a digital data signal by means of a digital control signal, the circuit being substantially as hereinbefore described with reference to the accompanying drawings.