GB2249644A - First-in first-out memory - Google Patents

First-in first-out memory Download PDF

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Publication number
GB2249644A
GB2249644A GB9118736A GB9118736A GB2249644A GB 2249644 A GB2249644 A GB 2249644A GB 9118736 A GB9118736 A GB 9118736A GB 9118736 A GB9118736 A GB 9118736A GB 2249644 A GB2249644 A GB 2249644A
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United Kingdom
Prior art keywords
sequence
check values
read
out memory
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9118736A
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GB2249644B (en
GB9118736D0 (en
Inventor
Trevor Robert Fox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of GB9118736D0 publication Critical patent/GB9118736D0/en
Publication of GB2249644A publication Critical patent/GB2249644A/en
Application granted granted Critical
Publication of GB2249644B publication Critical patent/GB2249644B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

Abstract

A first-in first-out (FlFO) memory has an integrity field 12 associated with each location. A cyclic sequence of check values is written into the integrity fields, and is then read out, and compared 21 with the expected sequence. Any discrepancy indicated a fault, e.g. a fault causing a location to he missed or read twice. The length of the sequence of check values is preferably co-prime with the number of locations in the FIFO. <IMAGE>

Description

FIRST-IN FIRST-OUT MEMORY Background to the invention This invention relates to first-in first-out (FIFO) memories. In general, a FIFO memory comprises a plurality of data storage locations which are written to in a predetermined cyclic order and read in the same cyclic order, so that the sequence of data is unchanged between the input and output.
The object of the present invention is to provide means for checking the correct operation of such a FIFO memory.
Summary of the invention According to the invention there is provided a first-in first-out memory comprising a plurality of data storage location which are written to in a predetermined cyclic order and read in the same cyclic order, wherein a) each location has an integrity field associated with it, b) a predetermined cyclic sequence of check values is written into the integrity fields of successive write locations, c) the check values in the integrity fields of successive read locations are tested to determine whether they follow said predetermined sequence.
It can be seen that the invention can therefore detect, for example, faults causing a location to be missed or read out twice.
Preferably, the length of the sequence of check values is a number which is co-prime with the number of locations in the FIFO. (Two numbers are co-prime if they have no common factors other than 1). This guards against addressing faults.
Brief description of the drawing On FIFO memory in accordance with the invention will now be described by way of example with reference to the accompanying drawings, which is block diagram of the FIFO.
Description of an embodiment of the invention Referring to the drawing, the FIFO comprises a register file 10 having 8 locations. Each location includes a data field 11 for holding a data word, and an integrity field 12 for holding a 3-bit check value.
The FIFO also includes a control circuit 15 which produces write and read addresses WADD and RADD for the register file. The control circuit 15 also produces a write enable signal WE for the register file. Whenever WE goes true, a data word is written from data input path 16 into the location of the register file addressed by WADD. The control circuit also produces a data available signal DAV. Whenever DAV goes true, a data word is read out from the location of the register file addressed by RADD, and loaded into a data output register 17. The read addresses RADD follow the same cyclic sequence as the write address WADD, so that the data is written to and read from the register file in the same cyclic order.
The register file 10 and the control circuit 15 may be conventional, and so need not be described herein in any further detail.
The FIFO also includes a counter 18 producing a sequence of check values. The counter 18 has a seven-stage cyclic count sequence 0, 1, 2, 3, 4, 5, 6. 0, 1, etc. Whenever WE does true, the output of the counter is written into the integrity field 12 of the register file location currently addressed by WADD, and the counter is then incremented.
Thus, it can be seen that, whenever a data word is written into a location of the register file 15, the next sequential check value is written into the integrity field of that location.
Whenever a data word is read out from the register file into the data output register, the corresponding check value is read out and loaded into a register 19.
The output of the register 19 is fed to an incrementer circuit 20 which increments the check value by 1. This incrementing is performed on a modulo 7 basis, which means that the value 6 is incremented to 0. The output of the incrementer 20 is compared, in a comparison circuit 21, with the check value currently being read from the register file, i.e. with the next check value in the sequence. In other words, each check value is compared with its expected value.
It can be seen that, in the absence of any errors, the check values read out of the register file 15 will be in the same sequence as they were originally written into the register file. Hence, each check value will match its expected value, and the comparison circuit 21 will normally detect equality. If the comparison circuit 21 detects inequality, this indicates that the current check value does not match its expected value, which means that an error has occurred. For example it may mean that a location in the register file has been missed, or read twice.
It should be noted that in the FIFO described above, the length (7) of the check value sequence is co-prime with the depth (8) of the register file. Thus, over a period of time, each register file location will hold all possible check values. This allows other possible addressing faults to be detected.

Claims (5)

1. A first-in first-out memory comprising a plurality of data storage locations which are written to in a predetermined cyclic order and read in the same cyclic order, wherein a) each location has an integrity field associated with it, b) a predetermined cyclic sequence of check values is written into the integrity fields of successive write locations, c) the check values in the integrity fields of successive read locations are tested to determine whether they follow said predetermined sequence.
2. A first-in first-out memory according to claim 1 wherein the length of said sequence of check values is a number which is co-prime with the number of data storage locations.
3. A first-in first-out memory according to claim 1 or 2 wherein the sequence of check values is produced by a counter.
4. A first-in first-out memory according to claim 3 wherein the check values are tested by storing the previously read check values in a register, incrementing the contents of the register, and comparing the incremented value with the currently read check value.
5. A first-in first-out memory substantially as hereinbefore described with reference to the accompanying drawing.
GB9118736A 1990-11-06 1991-09-02 First-in first-out memory Expired - Fee Related GB2249644B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909024085A GB9024085D0 (en) 1990-11-06 1990-11-06 First-in first-out memory

Publications (3)

Publication Number Publication Date
GB9118736D0 GB9118736D0 (en) 1991-10-16
GB2249644A true GB2249644A (en) 1992-05-13
GB2249644B GB2249644B (en) 1994-03-30

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GB909024085A Pending GB9024085D0 (en) 1990-11-06 1990-11-06 First-in first-out memory
GB9118736A Expired - Fee Related GB2249644B (en) 1990-11-06 1991-09-02 First-in first-out memory

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB909024085A Pending GB9024085D0 (en) 1990-11-06 1990-11-06 First-in first-out memory

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GB (2) GB9024085D0 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404332A (en) * 1993-10-07 1995-04-04 Fujitsu Limited Apparatus for and a method of detecting a malfunction of a FIFO memory
WO2003029953A2 (en) * 2001-09-28 2003-04-10 Infineon Technologies Ag Method for storing or transferring data
FR2929423A1 (en) * 2008-03-28 2009-10-02 Thales Sa Computer's data storage module i.e. first-in first-out type buffer memory, access managing device for aircraft, has generation module to generate sequential code, where generated code is attributes of space in which data is written

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1365057A (en) * 1972-02-26 1974-08-29 Ibm Testing the adressing circuitry of a data store

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1365057A (en) * 1972-02-26 1974-08-29 Ibm Testing the adressing circuitry of a data store

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404332A (en) * 1993-10-07 1995-04-04 Fujitsu Limited Apparatus for and a method of detecting a malfunction of a FIFO memory
GB2282682A (en) * 1993-10-07 1995-04-12 Fujitsu Ltd Detecting a malfunction of a fifo memory
GB2282682B (en) * 1993-10-07 1998-03-18 Fujitsu Ltd An apparatus for and a method of detecting a malfunction of a FIFO memory
WO2003029953A2 (en) * 2001-09-28 2003-04-10 Infineon Technologies Ag Method for storing or transferring data
WO2003029953A3 (en) * 2001-09-28 2004-05-21 Infineon Technologies Ag Method for storing or transferring data
US7577878B2 (en) 2001-09-28 2009-08-18 Infineon Technologies Ag Method for storing or transferring data using time sequencing
FR2929423A1 (en) * 2008-03-28 2009-10-02 Thales Sa Computer's data storage module i.e. first-in first-out type buffer memory, access managing device for aircraft, has generation module to generate sequential code, where generated code is attributes of space in which data is written

Also Published As

Publication number Publication date
GB9024085D0 (en) 1990-12-19
GB2249644B (en) 1994-03-30
GB9118736D0 (en) 1991-10-16

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20060902