GB2245443A

GB2245443A - Signal digitiser

Info

Publication number: GB2245443A
Application number: GB9013949A
Authority: GB
Inventors: Robert Nicholas Alcock
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1990-06-22
Filing date: 1990-06-22
Publication date: 1992-01-02
Anticipated expiration: 2010-06-22
Also published as: GB2245443B; GB9013949D0

Abstract

A digitiser is provided for measuring the amplitude of. for example, a radio frequency signal over an extended dynamic range. A radio frequency attenuator (2), switchable between predetermined attenuations, is connected in series before a radio frequency detector (0) to receive an input radio frequency signal on terminal (1) to be digitised. A switching signal (SD) is supplied to the attenuator to effect an increase in attenuation if the detected video signal input to an analogue to digital converter (10) exceeds a predetermined threshold level (VU). The increased attenuation is maintained while digitisation of the attenuated signal is effected. The switching signal (SD) and the digitised signal (D) are connected to combining means (16) to provide on an output (17) a digitised version of the input R.F. signal of wider dynamic range than that of the analogue to digital converter alone. Further threshold levels, each associated with a corresponding attenuation value, may be provided to yet further extend the dynamic range of the signal digitiser. <IMAGE>

Description

DESCRIPTION SIGNAL DIGITISER The present invention relates to signal digitisers and, more particularly, to a radio frequency signal digitiser comprising, in series, a radio frequency detector and an analogue to digital converter, ADC, of a predetermined dynamic range. In such a digitiser the detector produces a d.c. video signal proportional to the amplitude of an R.F. input signal. The ADC converts this d.c. signal into a digital number of a preset number of digits.

In typical applications of the digitiser, the input signal is an R.F. signal obtained from a radar or radio receiver and may have a wide range of signal strengths, 80 db being a typical range. A radio frequency signal digitiser suitable for this application is known from European Patent 0,160,338 (PHB33078).

In this known R.F. signal digitiser the input R.F. signal is applied directly to a first video detector and also to a second video detector via an R.F. amplifier of 40 db gain. Each video detector comprises a detector stage connected to an amplifier chain, each amplifier in the chain having a gain of 10, the outputs of the detector stage and amplifiers being combined in a logarithmic ADC. A digital combiner sums the digital outputs of the two video detectors. If each video detector has a dynamic range of 40 db, a total dynamic range of 80 db is realised.

However, an R.F. amplifier of accurately preset gain is required together with two ADCs.

It is an object of the present invention to provide a simplified R.F. digitiser having a wide dynamic range.

According to the present invention there is provided a signal digitiser comprising an analogue to digital converter (ADC) having a predetermined dynamic range, means coupled to an input of the ADC for determining if an input signal amplitude exceeds the dynamic range of the ADC, and control means responsive to determining that the input signal exceeds said dynamic range for connecting an attenuator of predetermined value in a signal path to the ADC and for providing an indication that the attenuator has been so connected The present invention provides a signal digitiser comprising a signal detector and an analogue to digital converter of a predetermined dynamic range connected to an output of the signal detector, characterised in that an attenuator is connected to an input of the signal detector having an input for a signal to be digitised, in that the attenuator is switchable between predetermined attenuations, in that control means are provided for supplying a switching signal to the attenuator to effect an increase in attenuation if the signal input to the analogue to digital converter exceeds a predetermined threshold level and for maintaining the increased attenuation while digitisation of the attenuated signal is effected, and in that the switching signal and the digitised signal are connected to combining means to provide a digitised version of the input signal of a dynamic range wider than the predetermined dynamic range of the analogue to digital converter.

In the signal digitiser made in accordance with the present invention a single ADC is used to digitise both weak and strong signals thereby reducing the overall cost of the digitiser whilst maintaining a wide dynamic range. Also the switched attenuations provided can be more accurately preset.

In certain applications of the invention the signal digitiser will be further characterised in that a signal amplifier is connected in series between an output of the switchable attenuator and the input of the signal detector, and in that a logarithmic video amplifier is connected in series between an output of the signal detector and the input to the analogue to digital converter. The radio frequency amplifier serves to raise the level of very weak input signals into the dynamic range of the detector. The use of a logarithmic video amplifier following the detector extends the dynamic range of the signal before digitisation by effectively compressing stronger signals into a limited output voltage range before digitisation.

It also has the benefit that the combining means becomes a digital addition device, rather than a multiplying device had the detector output signal been maintained linear.

Signal digitisers in accordance with the present invention may be used in either of two modes. In the first mode, known as the multisampling mode, the signal digitiser is further characterised in that the control means effects digitisation at regular intervals and in that the attenuator switching signal is supplied between digitisations if the predetermined threshold level is exceeded. This mode may be used, for example, to log a continuously changing incoming radio signal.

In the second mode, known as the event driven mode, the signal digitiser may be alternatively further characterised in that the control means effect digitisation when the signal input to the analogue to digital converter exceeds a lower threshold level. This mode may be used, for example, to measure the signal level of an incoming radar pulse, the timing of which cannot be predicted.

It will be seen that the use of one predetermined threshold level allows the dynamic range in decibels of a given analogue to digital converter to be effectively doubled. However, the signal digitiser made in accordance with the present invention may be further characterised in that the control means comprises a further threshold level at a higher level than the predetermined threshold level and means for providing a further switching signal connected to switch the attenuator to a further increased attenuation when the signal input to the analogue to digital converter exceeds the further threshold level. Thus with one further threshold level, the dynamic range in decibels may be tripled.Further threshold levels, each with a corresponding switchable attenuation value in the attenuator, may be added to yet further increase the dynamic range of the R.F. signal digitiser but using only one analogue to digital converter of limited dynamic range.

The present invention also relates to a receiver including a signal digitiser made in accordance with the present invention.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a block schematic circuit diagram of a signal digitiser made in accordance with the invention, Figure 2 shows typical control pulses applied to the circuit of Figure 1 when used in the multisampling mode, and Figure 3 shows the waveforms at various points in the circuit of Figure 1 following the arrival of a radio frequency pulse when the circuit is used in the event driven mode.

Referring to Figure 1, a radio frequency signal whose signal level is to be digitised is applied to a terminal 1. The radio frequency is typically in the range 2 to 6 GHz or 6 to 18 GHz.

The input signal may be in pulse form which may be down to 50 nanoseconds pulse-width or may be a continuously varying R.F.

signal.

The input signal is applied to a switchable radio frequency attenuator 2 which comprises a pair of fast single-pole two-way switches 3 and 4. In this example, the switch ways are connected to a straight through path 5 of minimal attenuation and to an attenuated path 6 providing a known amount of attenuation, for example 30 db. Thus, under the control of a switch drive circuit 7, shown schematically, the radio frequency signal can be unattenuated or attenuated by a known factor. Single pole double throw switches capable of switching times of 2 nanoseconds and passing up to 18 GHz signals are known, for example Alpha Industries GaAs MMIC SPDT Switch type number ASM018-01 is commercially available.

In this example, the radio frequency signal, attenuated or not, is passed to a radio frequency amplifier 8. The digitiser is required to operate over a wide dynamic range, typically 80 db, in the case of returning radar pulses or received radio signals. At very low input levels the signal level would be too low for the following circuits to handle and hence amplification is required. However, at high input levels the amplifier 8 may saturate. As will be explained later, the operation of the switchable attenuator 2 has the advantage of greatly reducing the risk of saturation and hence of digitisation accuracy degradation.

The amplified radio frequency signal is passed to a detector logarithmic video amplifier, DLVA 9. The DLVA is a combination of a detector 9A, which converts the R.F. signal to a video signal, d.c. coupled to a logarithmic video amplifier 9B which provides a d.c. output signal level proportional to the logarithm of the detector output signal. Hence the DLVA output is proportional to the signal level expressed in decibels (dB).

DLVAs of suitable frequency range and speed of response are available commercially, for example the Quantel D.C. Coupled Detector Logarithmic Video Amplifier Model 2700.

The d.c. output signal from the DLVA 9 is fed to an analogue to digital converter (ADC) 10 which converts the d.c. signal to a digital signal. In the present application, the R.F. signal may be pulses of a duration down to 50 nanoseconds. Desirably, therefore, the ADC 10 is of the highest speed and may be a so-called flash converter having a stack of voltage comparators to all of which the input signal is applied simultaneously and which produces all the binary digits of the signal simultaneously. A suitable commercially available ADC is the Analog Devices Ultra-high-speed 8-bit Monolithic ADC type No.

AD9002 having a sampling rate in excess of 150 megasamples per second, i.e. a sampling time less than 7 nanoseconds. A pulse input C2 applied to terminal 11 enables the ADC 10 to make one digitisation.

Control means are provided comprising two voltage threshold comparators 12 and 13 and a logic unit 14. The d.c. signal input to the ADC 10 is also fed to both comparators 12 and 13. A lower threshold voltage VL is supplied to comparator 12 by means not shown, and an upper predetermined threshold level Vu is supplied in a similar way to the comparator 13. The comparators 12,13 produce binary signals LT and UT, respectively, which each have the values i-or O if their thresholds are or are not exceeded, respectively. The output Sod of the logic unit 14 is likewise a binary signal having the values 1 or O if the attenuator is to be switched to a higher attenuation or not, respectively.A succession of logic states of LT,UT and SD arise with increasing time as a signal arrives at the signal digitiser and then decays to zero.

The initial logic state is LTsUT=SD=O in the absence of any signal. The next state is LT=l and UT=SD=O. This state signals the fact that either the signal is small enough not to saturate the R.F. amplifier 8 and lies within the dynamic range of DLVA 9 and ADC 10, or the signal is the rising edge of a larger signal.

In either event no action is called for to change the attenuator 2 and hence the logic unit signals SD=O. In the event that the input signal continues to rise and exceeds Vu, then UT=1, and increased attenuation is needed. This next logic state is then LT=UT=SD=1. The logic unit 14 comprises means for then maintaining SD=1 until LT falls to 0, indicating the end of a signal. Figure 3 shows the waveforms obtained following the arrival of a strong R.F. pulse shown as a pulse envelope 30.

When SD=1, the attenuation introduced is typically 30 db and it is assumed in the example for Figure 3 that this is sufficient to reduce the DLVA output signal below VU so that UT reverts to O but SD remains art 1 under the control of logic unit 14, maintaining the attenuation.

At any time during the logic state LT=1, UT=O and SD=1 the ADC 10 canoe energised to digitise its input. Also, once digitisation has occurred, the digital output D can be combined with the SD digit in a digital combiner 16 to produce a final digital output 17. The effect of the attenuation is to reduce the output of the RF amplifier 8 by a factor of, say, 30db in this example. Since a logarithmic amplifier is used in DLVA, the function performed by the combiner 16 is to add a digital number corresponding to 30db to the ADC output. If a linear amplifier had been used in unit 9, the combiner function would have been to multiply the ADC output by a digital number corresponding to 30db. Thus, in this example, the dynamic range of the ADC is extended by 30 db.To achieve the high speed required in the present example, the combiner 16 is preferably realised by a programmable logic array. Such an array can be programmed to list the possible combinations of the digitiser output and the SD multiplying factor. A suitable array is the Signetics PLC 153 programmable logic array having a total signal delay of 45 nanoseconds.

Finally, the signal level, in this example, falls below VL and LT=O. This signals the logic unit to produce SD=O, removing the attenuation and leaving the signal digitiser in the initial state ready to receive a further RF signal.

The signal digitiser in accordance with the invention can be used in either of two modes. In the first mode the signal is multisampled, the input signal being digitised at regular intervals. Figure 2 shows multisampling control waveforms which include a control pulse C1 applied to input 15 of the logic unit 14 to make changes in SD at controlled times in response to the prevailing values of LT and UT. The control pulses C1 and C2 are interlaced so that the attenuation value is set at time C1 and time allowed for the DLVA output to settle before digitisation is enabled by C2.

The second mode is event-driven. The change of LT from 0 to 1 produced by the rising edge of an input signal generates, after a fixed delay, a single C1 pulse which enables the logic unit 14. A single C2 pulse is generated after a further fixed delay to allow time for the DLVA to settle following any change in attenuation produced by C1 in accordance with the prevailing value of UT. No further digitisation is made until after LT falls to 0, signalling the end of the event.

In the above example, a single predetermined threshold level VU was used. However, it should be noted that a further higher threshold level may be provided which, if exceeded, can signal a further increase in attenuation. In this way, a further increase in the dynamic range of the signal digitiser may be obtained.

In the event of a rising ramp input signal, the crossing of VU for a first time will produce a fall in DLVA output below Vu A further rise of input signal may result in Vu being crossed for a second time. This can be used to signal the further increase in attenuation, the number of crossings of Vu in the upward and downward direction being stored and used to control the attenuation value.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of signal digitisers and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure ofthe present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

1. A signal digitiser comprising an analogue to digital converter (ADC) having a predetermined dynamic range, means coupled to an input of the ADC for determining if an input signal amplitude exceeds the dynamic range of the ADC, and control means responsive to determining that the input signal exceeds said dynamic range for connecting an attenuator of predetermined value in a signal path to the ADC and for providing an indication that the attenuator has been so connected.

2. A signal digitiser comprising a signal detector and an analogue to digital converter of a predetermined dynamic range connected to an output of the signal detector, characterised in that an attenuator is connected to an input of the signal detector having an input for a signal to be digitised, in that the attenuator is switchable between predetermined attenuations, in that control means are provided for supplying a switching signal to the attenuator to effect an increase in attenuation if the signal input to the analogue to digital converter exceeds a predetermined threshold level and for maintaining the increased attenuation while digitisation of the attenuated signal is effected, and in that the switching signal and the digitised signal are connected to combining means to provide a digitised version of the input signal of a dynamic range wider than the predetermined dynamic range of the analogue to digital converter.

3. A signal digitiser as claimed in Claim 2, characterised in that a signal amplifier is connected in series between an output of the switchable attenuator and the input of the signal detector, and in that a logarithmic video amplifier is connected in series between an output of the signal detector and the input to the analogue to digital converter.

4. A signal digitiser as claimed in Claim 2 or 3, characterised in that the control means effects digitisation at regular intervals and in that the attenuator switching signal is supplied between digitisations if the predetermined threshold level is exceeded.

5. A signal digitiser as claimed in Claim 2 or 3, characterised in that the control means effect digitisation when the signal input to the analogue to digital converter exceeds a lower threshold level.

6. A signal digitiser as claimed in any one of Claims 2 to 5, characterised in that the control means comprises a further threshold level at a higher level than the predetermined threshold level and means for providing a further switching signal connected to switch the attenuator to a further increased attenuation when the signal input to the analogue to digital converter exceeds the further threshold level.

7. A signal digitiser substantially as hereinbefore described with reference to and as shown in Figures 1 and 3 of the accompanying drawings.

8. A signal digitiser substantially as hereinbefore described with reference to and as shown in Figures 1 and 2 of the accompanying drawings.

9. A radio receiver including a signal digitiser as claimed in any one of Claims 1 to 8.