GB2244879A

GB2244879A - Procedure for connecting a refrigerated signal pre-processing circuit board and a processing circuit board

Info

Publication number: GB2244879A
Application number: GB8912712A
Authority: GB
Inventors: Henri Pruvot; Albin Virdis
Original assignee: T SA
Current assignee: T SA
Priority date: 1988-07-01
Filing date: 1989-06-02
Publication date: 1991-12-11
Anticipated expiration: 2009-06-02
Also published as: GB8912712D0; DE3921599A1; FR2656186B1; FR2656186A1; IT1232124B; IT8967522A0; GB2244879B

Abstract

The pre-processing circuit board of the system, on which a circuit board of thermal detection photodiodes can be hybridised, is arranged in a cryogenic chamber 1 and incorporates a field effect transistor 5, with a low polarising current and a high output impedance. The source 9 of the transistor is charged by a resistor 10 arranged outside the chamber 1. The source 9 is connected to the base of a bipolar transistor 7, mounted in a common emitter configuration, with a low input impedance, forming the input circuit of the processing circuit board 8. By virtue of the invention, the energy consumed by the pre-processing circuit board is low. <IMAGE>

Description

DESCRIPTION

PROCEDURE FOR CONNECTING A REFRIGERATED SIGNAL PREPROCESSING CIRCUIT BOARD AND A PROCESSING CIRCUIT BOARD AND A PROCESSING SYSTEM FOR UTILISING THE PROCEDURE This invention has its origins in the sensing system used for example in a thermal camerafor scanning landscapes in real time, for example integrated into an imaging or surveillance system.

An infrared thermal camera comprises, firstly, in the focal plane of its optical system, a sensing printed circuit board, containing a mosaic of several hundreds, or even a thousand infrared photodiodes. Having regard to the high number of diodes, it is not possible to connect them to an external processing circuit by traditional means. The sensing printed circuit board is therefore superimposed and connected to a pre-processing circuit board, also arranged in the focal plane, or more or less so - the two boards are thus hybridised - the pre-processing printed circuit board containing circuits for load transfer, namely, and essentially, input circuits associated with the photodiodes to integrate their output currents, pre- amplifying, filtering and multiplexing devices and an output circuit, also forming an interface between the pre-processing board and a separate board for subsequent processing. The interconnections between the boards may be of the "beam- leaC type.

In order to optimise performance, i.e. to minimise stray noise, the sensing board must operate at a low temperature. The focal plane assembly, consisting of the sensing and pre-processing boa.rds, is therefore arranged inside a cryogenic chamber, or cryostat, connected to a refrigerating system.

The electronic pre-processing circuits nevertheless obviously constitute a constraint for the refrigeration system, with regard to throughput, especially for high data output rates, above several MHz. By way of illustration, the efficiency of a cryostat is only in the order of 1%.

It might be desired to mitigate the presence of the electronics by increasing the cryogenic power. But that would be done to the detriment of the weight, which is often intolerable.

The applicant has therefore studied the problem of seeking to lower the energy consumption of the circuits of the pre- processing board of the focal plane.

In a sensing and processing system as produced up to the present day, and since the electrical power required for the pre-processing circuits to operate, of the order of several tens of mW, may be considered negligible, it is the interface between the focal plane -3and the processing board which consumes most of the energy (approximately 90%), because of the conditions under which the data is presented at the output from the pre-processing board which, because of the multiplexing of the sensing paths, must be supplied to the processing circuits in accordance with sampling pulses at a prescribed time of establishment, or connection, at a given amplitude (2 to 3 volts), and above all at the highest possible rate. In the case of MOS circuits, the only ones that can be used in practice at low temperature, with, in the pre-processing board, at least one output field effect transistor as an interface, it is above all the stray or parasitic capacitance (of the order of 10 to 20 pF) due essentially to the connections, and charging the source of the transistor, which consumes the energy. Now it is not possible to reduce this capacitance.

In existing sensing and processing systems, the information is delivered by the pre-processing board at low impedance and received by the processing board at high impe.dance, at high input impedance in order to avoid attenuation, and at low output impedance in order to deliver the information with a time coefficient, proportional to the output impedance, as low as possible, and therefore as rapidly as possible. When information to be delivered to the processing board arrives at the output transistor of the pre-processing board, because of the high impedance of the processing board upstream, at the start of its charging, it is the parasitic or stray capacitance charging the output transistor of the pre-processing circuit which absorbs most of the information current.

To return to the problem to be resolved with respect to decreasing energy consumption, in the case of an output FET, this consumption is proportional to the current I p and the polarisation voltage Vds of this transistor. In other words, it is the power Vds x Ip which is to be dissipated. In order to decrease it, it might have been wished to lower I p or Vds But lowering I p would lead to an increase in the output impedance, which varies inversely as the square root of IPS and therefore to an increase in the time constant, which is not acceptable. And lowering Vds would lead, with a large voltage deviation, to poor linearity, and therefore to poor performance, which is not acceptable either. As for reducing this voltage deviation, this is possible only with weak signal/noise dynamics, which is incompatible with the present requirements which exceed 12 bits, i.e. a ratio of 4096 between the peak signal and the effective noise, leading to a noise of the order of 1 mV, the threshold below which it is not possible to go without affecting performance.

As for the build up time of the output pulses from the focal plane, before which the time constant must remain as low as possible, it is not possible to increase it either, since it is directly linked to the data'rate, itself dependent on the imposed characteristics of the system, such as the duration of scanning, the number of photodiodes on the sensing board, and the number of samples to be obtained per unit of time.

It is for these reasons that the applicant puts forward this invention to resolve the problem posed.

The present invention concerns a process for connecting to an input circuit of a pro.cessing printed circuit board, a stray capacity output circuit of a printed circuit board for pre-processing output signals from a sensing board, the.sensing and pre-processing boards being hybridised one on top of the other and arranged in a cryogenic chamber, wherein the input circuit of the processing board is arranged to have a low impedance.

The invention, in this case,-is already noteworthy in that the output signals of the focal plane are fed into the processing board at a low impedance whereas it has been usual, as seen above, to feed them in at a high impedance.

The fact of feeding the output signals from the focal plane in.to the processing board at low impedance enables one to free oneself favourably from the integrating stray capacitance of the focal plane output circuit. In other words, the data-current of the focal plane is no longer diverted as previously in the stray capacitance, and not only is the energy consumed by this stray capacitance, and which is dissipated, strongly diminished in this way, but also a good data transmission rate is ensured.

By virtue of this low input impedance, the problem posed at the outset can be resolved to an even greater extent.

In the preferred use of the process of the invention, the output circuit of the pre-processing board is arranged so as to have a high impedance.

In reality, it is because the polarising current of the output circuit of the pre-processing board is decreased that the output impedance is increased. But decreasing the polarising current means reducing still further the energy to be dissipated.

Thus. at the interface between the pre-processing board and the processing board, the data emerges at high impedance and enters at low impedance. This is exactly the opposite of the process used earlier.

In other words, yet again, the invention has enabled the current, and therefore the energy consumption, to be decreased, whilst still keeping a proper time constant, and therefore a good transmission rate.

Although the invention does indeed have its origins in detection, and more particularly in infrared detection, the applicant does not for all that intend to limit the scope of the application to this field.

Having regard to current technological developments, and particularly in data processing, the applicant's invention will apply to the connection of any refrigerated printed circuit board for preprocessing signals and a subsequent processing board.

The invention therefore more generally concerns a process for connecting to an input circuit, a processing printed circuit board, a stray capacitance output circuit on a printed circuit board for pre-processing signals arranged in a cryogenic chamber, characterised by the fact that the input circuit of the processing board is arranged so as to have a low impedance.

Again, the output circuit of the pre-processing board is preferably arranged so as to have a high impedance.

The invention also concerns a processing assembly for utilising the process of the invention, comprising a signal pre-processing printed circuit board with a stray capacitance output circuit arranged in a cryogenic chamber, and a processing printed circuit board with an input circuit connected to the output circuit of the pre-processing board, characterised by the fact that the input circuit of the processing board has a low impedance.

Preferably, the input circuit of the processing board incorporates at least one in-line polarised diode, having therefore a low impedance; it would preferably be a case of the base-transmitter interface of a bipolar npn transistor mounted in a common transmitter.

Again, the output circuit of the pre-processing board preferably incorporates at least one FET, of high output impedance, and whose source is connected to the base of the bipolar input transistor of the processing board, the load resistor of the FET being outside the cryogenic chamber. Placing the load resistor of the output transistor outside the focal plane enables the power to be dissipated to be decreased further, by the product of the strength of the polarising current I p and the value of the potential of the source of the output transistor (Vdd - Vds).

As the potential of the base of the bipolar input transistor varies only very slightly, the voltage -gdeviation on the source of the output FET, whose potential is "clamped" to that of the base of the input transistor, is therefore small, and its polarising voltage Vdd can therefore, through design, be reduced to a minimum, without for all that effecting the linearity and therefore the dynamic performance.

Thus, not only the polarising current of the output FET but also its polarising voltage can be decreased, and therefore the power to be dissipated can be decreased considerably.

In other words, the invention has substituted, in place of the voltage matching of the traditional installation, a current matching, the amplification of the data current at the output from the pre-processing stage being a function of the parameter ú of the input transistor of the processing stage, equal to the ratio between its collector current and its base current.

It will be noted that the design of the output FET will have to be suited, in its geometry, and more particularly in the geometry of its gate, to the strength of the current passing through it, in order to optimise performance.

It will also be noted that the pre-processing printed circuit board and the processing board can incorporate several output stages and several input stages respectively, and, as a consequence and for example, several output FETs and several low impedance input amplifiers, respectively.

The pre-processing board can be a pre-processing board with output currents having a mosaic of detection photodiodes, e.g. infrared, with a detection board hybridised on the pre-processing board.

The invention will be better understood through the following description of several forms of embodiment of the processing assembly of the invention and their functioning, with reference to the attached drawings, in which Figure 1 is a schematic block view of a thermal camera of an earlier design for landscape scanning in real time; - Figure 2 is a schematic view-of a first embodiment of the processing system of the invention; Figure 3 is a schematic view of a second embodiment of the processing assembly of the invention, and; - Figure 4 is a schematic view of a third embodiment of the processing assembly of the invention.

The invention will therefore be explained with reference to the example, not limiting in its scope, of a thermal imaging camera, undertaking landscape scanning in real time. Only the elements of the camera necessary for understanding the invention are described below. For the other elements, reference may usefully be made to documentation on earlier designs and, more particularly, the French Patent Applications No. 2 591 349, 2 591 350, 2 591 409 and 2 599 529 madeby the applicant.

Schematically, inside a cryogenic chamber 1, drawing its refrigerating capacity from a refrigeration device 2, e.g. of the liquid helium type, behind a window allowing, in this case, infrared radiation to pass, itself arranged behind the optical system of the camera, and in the focal plane of this optical system, two printed circuit boards 3, 4 hybridised one 3 on top of the other 4 are arranged. The printed circuit board 3 is a detection board containing a nosaic of infrared photodiodes, for example of HgCdTe, InSb, AsGa. The printed circuit board 4 contains, in this case on a substrate of silicon, circuits for pre-processing output currents from the photodiodes of the printed circuit board 3, and in particular an output circuit 5. This output circuit 5 is charged by a parasitic (stray) capacitance 6 and is connected to,the input circuit 7 of a processing printed circuit board 8, the output of which is connected to an acquisition chain.

The camera, as described up to this point, is of a known type.

With reference to Figure 2, the output circuit of the pre-processing printed circuit board 4 in this case incorporates a single FET 5 (MOS-FET or J-FET) arranged inside the chamber 1, whose source 9 is charged by the parasitic capacitor 6 and, in parallel with it, by a load resistance 10. The drain 11 of the transistor 5 is subjected to a polarising voltage Vdd, and a polarising current I p circulates in it. The gate of the transistor 5 receives the information current Is, emitted by the photodiodes, and a current I p + IS circulates in the source 9 of the transistor. The input circuit of the processing printed circuit board 8 is in this case an amplifier with a low input impedance, consisting of a bipolar npn transistor 7 mounted in a common emitter configuration. The base B of the transistor 7 is connected to the source of the output FET 5, its emitter E is earthed and its collector C is subjected to a polarising voltage Vc, preferably and in actual fact Vdd, through a load 12.

The transistor 5 is designed, as will be seen later, for a weak polarising current I p and a weak polarising voltage Vdd. The current I p + IS is emitted by the pre-processing printed circuit board 4 at low impedance and the power to be dissipated by the cryostat is especially reduced.

The load resistor 10 deriving a current Ip, the output current of the input transistor 7, its collector current, is equal to the product of IS and the parameter of the transistor.

The base-emitter diode of the input transistor 7 is forward biassed. It therefore has, compared with the current-voltage curve of a diode, a very low impedance, and its potential is to all intents and purposes fixed. The same applies to that of the source of the output FET 5 which is connected to it (the so-called "clamping" effect).

In a first variant, and referring to Figure 3, the input transistor 7 is connected, through its collector, to the emitter of a second bipolar npn transistor 13, whose collector is subjected to the polarising voltage Vdd of the drain of the transistor 5, through a load resistor 14, and whose base is also subjected to this voltage Vdd, through a dividing bridge 20. This is a bipolar connection of the cascode type affording a better passband, by reducing the Miller effect due to the presence of the stray capacitance between the base and the collector of the output transistor 13.

In a second variant, and referring to Figure 4, the input circuit of the processing circuit board incorporates a transfer impedance amplifier 15 connected, through its negative input 16, to the source of the output transistor 5, through a capacitor 17, avoiding the passage of direct current, and a resistor 18 in series, the positive input 19 of the amplifier being connected to earth, the output of the amplifier being looped at its negative input by a feed back resistor 21. The advantage of the transfer impedance amplifier is that it has a very low impedance at its negative input. This set up has the advantage of better control of the transfer function of the interface circuit of the two pre-processing and processing circuit boards. It will be noted that the output impedance of the interface circuit assembly has to be high not only before the input impedance of the amplifier 15 but also before the input resistor 18.

A transfer impedance amplifier of the Analog Devices make may be used.

The design of the output FET 5, whose geometry, and more particularly that of its gate, must depend on the current passing through it, will now be dealt with.

The dimensions of the gate, namely its length L and its width W, are linked to the "aspect ratiC A of the transistor by the formula A = W- 2 E----Z (1) which is determined, particularly from the power to be dissipated, in accordance with the following procedure.

-is- Since the design technology of the transistor is known, the polarising voltages are predetermined, namely, in the case of a bipolar input transistor on the processing circuit Vdd, the potential of the drain of the output transistor 5, the non- operating potential of the gate of the output transistor 5, the threshold voltage of the output transistor where vgs Vt ' Ve 1 Vdd - Vs "" Vds \\Vdd - VBE Vds V. being the potential of the source of the transistor 5, and therefore the potential VB of the base of the input transistor 7, and therefore the known baseemitter voltage VBE of the transistor 7 whose emitter is earthed, and Vds being the voltage between the drain and the source of the transistor 5.

The result of this is a non saturated mode of operation of the transistor 5, by reason of the inequality Ve > Vds as will be seen by means of the example dealt with later.

A predetermined maximum permissible power p is adopted a priori.

The corresponding current I p passing through the output transistor 5 is deduced from this in accordance with the formula I p p (2) Vds The aspect ratio A is deduced from it in accordance with the formula 1 + V A = p (3) K' (VeVds - Vdf- where 0,06/V and K' = 130 jjA/V2 From this tMe ratio W the gate of the output L transistor is derived by using equation (1).

The transconductance gm of the output FET 5 is also deduced in accordance with the formula 1 g m = q I p T-,S-FT where q is the electron charge K is the Boltzmann constant T is the temperature of the focal,plane.

The output impedance Ro of the FET 5, consisting of the impedance 1 and its load resistance RL in parallel, gm is deduced from it in accordance with the formula R L R gm RL + 1 _m RL 1 + RL9M The pass-band of the output FET is derived from it in accordance with the formula f = 1 where Req.C C is the parasitic capacity Req is the equivalent impedance of the output impedance Ro and the input impedance Re of the bipolar transistor 7, in parallel.

If this pass-band is compatible with the requirements which have been chosen, the estimated starting data are maintained, otherwise, i.e. if it is too weak, for example, the outgoing power P is increased and the process is recommenced.

Purely by way of 'illustration, the calculation of an output FET with a bipolar input circuit wi 11 be described, before comparing it with that of an output transistor followed by a traditional input circuit.

Bipolar input circuit Vdd v 9 Vt = 1 2 V vs = VBE 0,7 V - vgs = V 9 vs = 14,3 V - Ve = Vgs - Vt = 13,1 V - Vds = Vdd - VS 4,3 V As the voltage V. 13.1 V is greater than the voltage Vds = 4.3 V, the FET is not saturated.

1.875 mW From equation (2) is derived I = 436 A From equation (3) is derived A: 1 -g = 5 V = 15 V From equation (1) the geometry of the gate of the transistor 5 can be derived W 10 L TU The transistor 5 is thus characterised by a gate with a length more than 6 times greater than its width, with a voltage Vds = 4.3 V, with a polarising current of 0.4 mA, and operating in an unsaturated mode.

0 Traditional Vdd '= 1 = 1 vs v e input circuit 5 V 5 V 1 2 V 6 V 9 v 7,8 V Vds 9 v As the voltage Ve = 7.8 V is less than the voltage Vds = 9 V, the FET is saturated.

P = 9.375 mW From equation I P = 1042 P A From equation A::-- 1 T-1-6From equation (1), the geometry of the transistor gate can be derived (2) is derived (3) is derived W = 10 E _z j The FET in the traditional set up is thus characterised by a length of gate a little more that double its width, with a voltage Vds = 9 V, with a polarising current of 1 mA, and operating in a saturated mode.

A pre-processing circuit board with a single output -20stage having a single FET has been considered. Nevertheless the invention applies just as well to a pre-processing circuit board with several output stages and therefore with several FETs.

S

Claims

- 2 1 CLAIMS

1. A procedure for connecting an input circuit of a processing circuit board and an output circuit with a parasitic capacitance of a signal preprocessing circuit board arranged in a cryogenic chamber wherein the input circuit of the processing circuit board is arranged so as to present a low impedance.

2. A connecting procedure as claimed in claim in which the output circuit of the pre-processing circuit board is arranged so as to present a high impedance.

3. A connecting procedure as claimed in claim 1 or 2, in which the circuit board arranged in the cryogenic chamber pre-processes output currents from a mosaic of detection photodiodes on a detection circuit board hybridised on the pre-processing circuit board.

4. A processing system utilising the connecting procedure of claim 1, comprising a signal pre-processing circuit board, with an output circuit with a stray capacitor and arranged in a cryogenic chamber and a processing circuit board, with an input circuit connected to the output circuit of the pre-processing circuit board wherein the input circuit of the processing circuit board has a low impedance.

5. A processing system as claimed in claim 4, in which the input circuit of the processing circuit board incorporates at least one amplifier with a low input impedance.

6. A processing system as claimed in claim 5, in which the amplifier is a transfer impedance amplifier.

7. A processing system as claimed in claim 5, in which the amplifier is a bipolar transistor mounted in a common emitter.

8. A processing system as claimed in claim 7, in which the bipolar transistor is connected to a second bipolar transistor in order to form a circuit of the cascode type.

9. A processing system as claimed in any of claims 4 to 8, in which the output circuit of the processing circuit board has a high output impedance.

10. A processing system as claimed in claim 9, in which the output circuit of the pre-processing circuit board incorporates at least one field effect transistor with a high output impedance, connected, through its source, to an input circuit of the processing circuit board.

11. A processing system as claimed in claim 10, in which the source of the field effect transistor is charged by a resistor arranged outside the cryogenic chamber.

12. A processing system as claimed in any of claims 11 -239 to 11, in which the pre-processing circuit board incorporates several output stages, each incorporating a field effect transistor with a high output impedance.

13. A processing system as claimed in any of claims 4 to 12, in which a circuit board with a mosaic of detection photodiodes is hybridised on the preprocessing circuit board.

14. A process system utilising the connecting procedure of claim 1, substantially as hereinbefore described with reference to and as illustrated in Figs.

2 to 4 of the accompanying drawings.

Published 1991 at The Patent Office. Concept House, Cardiff Road. Newport. Gwent NP9 1RH. Further copies may be obtained from Sales Branch. Unit 6, Nine Mile Point, Cwmfelinfach, Cross Keys, Newport, NPl 7HZ. Printed by Multiplex techniques lid. St Mary Cray. Kent.