GB2242767A - Precharging DRAM bit lines to half supply potential - Google Patents

Abstract

To sense the contents of a memory cell in a DRAM with improved speed, wherein both sides of a data bus pair 2, 3 are precharged to one-half the supply voltage level, the midpoint between a logic high and logic low level. Only a small voltage differential from the aforenoted intermediate level caused by connection to the bit line pair 1 is necessary to cause the sense amplifier to successfully read. A differential amplifier having a high gain region over that small differential is used to sense the differential, providing an output representative of the charge imparted to the bit line and thus to the data bus from the read-memory cell. During a cycle, one side of the data bus is pulled high by sense amplifier 7 and the other side is pulled low. Since the bit lines are precharged to half supply potential, full logic levels are achieved more quickly during a read cycle. <IMAGE>

Description

HIGH-SPEED, SMALL-SWING DATAPATH FOR DRAM FIELD OF THE INVENTION; This invention relates to a semiconductor dynamic random access memory (DRAM), and in particular to a method and apparatus for sensing the contents of a memory cell in the memory.

BACKGROUND TO THE INVENTION; Dynamic random access memories (DRAMs) are formed of rows and columns, each column being comprised of a complementary bit line pair to which bit storage capacitors are connected via access transistors. The word line corresponding to the row address, connected to the gate of one access transistor in each bit line pair, is turned on to dump memory cell charge to the bit line. Sense amplifiers are connected to the bit line pairs, and the charges on the bit lines are read by respective sense amplifiers which restore full logic levels to the bit lines. The bit lines corresponding to the column address are then read to a data bus pair.

Typically, the data buses are precharged to supply voltage Vcc prior to their connection to the bit lines. One side of the data bus pair is then pulled to low logic level by the bit line sense amplifier once the connection has occurred. A data bus sense amplifier, typically a differential amplifier, is enabled to sense the data on the data bus. The data bus sense amplifier has a high gain for input voltages within a mid-level common mode voltage region data bus. Sensing is slow because it takes some time for the data bus voltage level to fall from Vcc to the high gain range of the data bus sense amplifier. This has been found to be a significant impediment to making faster DRAMs.

SUMMARY OF THE INVENTION: In accordance with the present invention, both sides of a data bus pair are precharged to onehalf the supply voltage level, the midpoint between a logic high and logic low level. During a column cycle, one side of the data bus is pulled high by the sense amplifier and the other side is pulled low.

Only a small voltage differential from the aforenoted intermediate level caused by connection to the bit line is necessary to cause the sense amplifier to successfully read. A differential amplifier having a high gain region over that small differential is used to sense the differential, providing an output representative of the charge imparted to the bit line and thus to the data bus from the memory cell.

In accordance with an embodiment of the invention, a method of sensing the logic level of a random access memory data bus is comprised of the steps of precharging both sides of a data bus pair across which a bit line pair can be connected, to an intermediate voltage level between a logic high and a logic low voltage level, executing a column read cycle by connecting the sense amplifier to the data bus, thereby creating a voltage differential on the data bus centered around the intermediate precharge voltage level which is a small fraction voltage of the difference between the logic high and logic low levels, and sensing the small fraction voltage of the difference, in the sense amplifier.

Preferably the sense amplifier has high gain over a region centered by the data bus precharge voltage level, i.e. the difference between the logic high and logic low levels. Also preferably the intermediate level is one-half the voltage between the logic high and logic low levels.

According to another embodiment, a dynamic random access memory is comprised of apparatus for precharging both data buses of a data bus pair to a level between a logic high and a logic low level, apparatus for executing a column read cycle on the memory thereby creating a differential voltage, the polarity corresponding to a bit to be read centered about said intermediate level which differential voltage is a small fraction voltage of the difference between the logic high and logic low levels, and a sense amplifier connected across the data bus pair having high gain over an input voltage region spanning the voltage difference for sensing the small fraction difference voltage.

BRIEF INTRODUCTION TO THE DRAWINGS: A better understanding of the invention will be obtained by reference to the detailed description below, in conjunction with the following drawing, in which: Figure 1 is a block schematic illustrating the present invention.

DETAILED DESCRIPTION OF THE INVENTION: Figure 1 illustrates a portion of a dynamic random access memory (DRAM), showing a representative complementary bit line 1 and both data buses of a data bus pair 2 and 3, with capacitive loads 4 representing the data bus interconnect capacitance plus the source-drain capacitance of access transistors of all the unselected columns.

The bit line is coupled to the data bus by pass transistors 5 and 6. A sense amplifier 7 having outputs 8 is connected to data bus pair 2 and 3.

It will be recognized that the elements described above are representative of only a portion of the DRAM.

In accordance with the present invention, the precharge circuit 10 provides precharge voltage to the sense amplifier and is connected to a voltage level between the logic high and a logic low level, preferably Vdd/2. The precharge circuit 10 is comprised of a pair of N-channel field effect transistors 11 and 12 having their source-drain circuits connected between the low logic level source, Vdd/2, and respective data buses 2 and 3, and another N-channel transistor 13 which has its sourcedrain circuit connected across the data buses 2 and 3. The gates of transistors 11, 12 and 13 are connected together to a precharge enable logic signal source. The sense amplifier 7 contains a data bus amplifier having a high gain input range over a voltage interval which includes the data bus precharge voltage level noted above.This is preferably provided by an amplifier which has a differential input stage.

An example of a sense amplifier that can be implemented for use in the present invention is shown within the block 7. It is comprised of two identical circuits, each comprised of a pair of P-channel FETs 15A, 16A (15B, 16B) having their sources connected to voltage source Vdd and their gates connected together and to the drain of FET 15A (15B). A pair of N-channel FETs 17A, 18A (17B, 18B) have their sources connected together and their drains to the respective drains of FETs 15A, 16A, (15B, 16B). P-channel transistor 19A (19B) has its source-drain circuit connected in parallel with the source-drain circuit of transistor 16A (16B).

The drains of transistors 16A, 18A and 19A (16B, 18B and 19B) are connected to the gate of P-channel FET 20A (20B) which transistor has its source-drain circuit in series with the source-drain circuit of N-channel transistor 21A (21B) between Vdd and ground.

An inverter 22A has its input connected to the junction of the drains of transistors 16B, 18B and 19B and its output connected to the gate of transistor 21A, and an inverter 22B has its input connected to the junction of the drains of transistors 16A, 18A and l9A and its output connected to the junction of transistor 21B. An N-channel transistor 23 has its source-drain circuit connected between the sources of transistors 17A, 18A, 17B, 18B and ground.

The gates of transistors 18A and 17B are connected to one data bus 3 and the gates of transistors 17A and 18B are connected to the other data bus 2. A sense enable input EN is connected to the gates of transistors 19A, 19B and 23.

The junctions of transistors 10A and 2lea, and 10B and 21B respectively form the differential output leads 8.

In operation, during a read cycle the data bus precharge circuit receives a precharge enable signal and transistors 11, 12 and 13 conduct, precharging and equalizing both data buses of the data bus pair 2 and 3 to the intermediate voltage level Vdd/2 provided at terminal Vdd/2. A read cycle is executed on the column, i.e. bit line 1, which is connected to the data bus pair by transistors 5 and 6. Charge from the bit line 1 is passed to the data bus pair, thereby creating a small voltage differential which is a small fraction of the difference between the logic high and logic low levels Vdd and ground. The voltage differential represents the bit stored in a memory cell accessed to the bit line, which varies the polarity of the voltage difference on the data bus typically several hundred millivolts absolute value.This small fraction voltage is sensed in the sense amplifier differential pair and the resulting representative full logic level is provided at the outputs 8, as follows.

The small voltage differential between the data buses appears at the gates of transistors 17A and 18A, and 17B and 18B. Each pair of transistors 17A, 18A (17B, 18B) forms a differential pair. With the enable logic signal low, transistors 19A and 19B clamp the inputs of transistors 20A and 2OB to Vdd, inhibiting transistors 20A and 2OB, and via inverters 22A and 22B, inhibiting transistors 21A and 21B. Transistor 23 is also inhibited.

With a high logic level (sense enable) signal at the gate of transistor 23, it is enabled, connecting the two differential pairs to ground.

Transistors 19A and 19B are inhibited, releasing transistors 20A, 20B, 21A and 21B. The differential pairs sense the differential voltage across the buses 2 and 3, applying Vdd and ground to the respective gates of transistors 20A and 20B. This causes either transistors 21A and 2OB or 20A and 21B to conduct, connecting the output leads to Vdd and ground, full logic level.

The result is that the previous slow data bus pull down interval from the Vc precharge level to the point where the differential input devices operate in saturation is avoided, because the data bus pair is already close in voltage to the voltage imparted by the bit lines. The memory is thus considerably speeded up.

In addition, since the sense amplifier need only sense a differential of a few hundred millivolts, and since the differential exists at the high gain region of the sense amplifier, it operates much faster than sense amplifiers of the prior art.

The power required to charge the capacitance associated with the bit lines during precharge is thus also minimized. Therefore the power supply requirements of the memory are lower than in the prior art (i.e. the CV2/T power is minimized).

Since there is less voltage differential needed than in prior art DRAMs, longer data buses can be driven, thus allowing larger memory sizes to be obtained. The data bus sense amplifier input stage, being a simple differential FET pair, is thus simple and efficient. A considerably faster, larger and less power consuming DRAM results.

A person understanding this invention may now conceive of alternative structures and embodiments or variations of the above. All of those which fall within the scope of the claims appended hereto are considered to be part of the present invention.

Claims (10)

1. A method of sensing the logic level of a dynamic random access memory (DRAM) data bus comprising: (a) precharging both data buses of a data bus pair across which a bit line pair can be connected, to a voltage level between a logic high and a logic low level, (b) executing a read cycle on a complementary bit line pair and connect it to the data bus pair thereby creating a small differential voltage across the data bus pair which is a small fraction voltage of the difference between said logic high and logic low levels, (c) sensing said small fraction voltage of the difference, in said sense amplifier.

2. A method as defined in claim 1 in which said sense amplifier has a high gain over said small fraction voltage of said difference.

3. A method as defined in claim 2 in which said intermediate level is one-half the voltage between said logic high and logic low levels.

4. A method as defined in claim 3 in which the sensing step is performed in a differential amplifier.

5. A method as defined in claim 4 in which the input stage of said amplifier is comprised of a differential stage.

6. A dynamic random access memory (DRAM) comprising: (a) means for precharging both data buses of a data bus pair to which a bit line pair can be connected, to a level intermediate a logic high and a logic low level, (b) means for executing a column read cycle on said bit line pair for applying a charge differential from said bit line pair to said data buses, (c) a sense amplifier connected across the data bus pair having high gain over an input voltage region spanning said voltage difference for sensing the said small fraction difference voltage.

7. A DRAM as defined in claim 6 in which said intermediate level is one-half the voltage difference between said logic high and logic low levels.

8. A DRAM as defined in claim 6 in which the data bus sense amplifier input stage is a high gain differential stage.

9. A method according to claim 1, substantially as herein described with reference to and as shown in the accompanying drawing.

10. A DRAM according to claim 6, substantially as herein described with reference to and as shown in the accompanying drawing.