GB2242583A - Dual reference tracking resolver to digital converter - Google Patents

Abstract

Cosine and sine resolver inputs are multiplied with digital sine and cosine internal signals in DAC 22 and 23 respectively and the outputs are fed to an error amplifier 24 which produces an error signal which is digitalized by converter 25 and demodulated, 26, by a digitalized reference signal from the resolver. This output is demodulated in demodulator 27 and fed to a binary accumulator 29 via digital filter 28. The accumulator output 30 is firstly used by cosine look-up table 32 to produce via modulator 34 the cosine input signal for DAC 23 and secondly by sine look-up table 31 to produce via modulator 33 the sine input signal for DAC 22. Demodulator 27 and modulators 33 and 34 are connected to an internal digital reference synthesizer 35. <IMAGE>

Description

Dual Reference Tracking Resolver to Digital Converter This invention relates to a Resolver to Digital Converter (RDC) which is an electronic device for converting the positional information provided by a Resolver (Synchro or other similar transducer) in analogue SINE/COSINE format into an equivalent digital format.

The positional information provided by the transducer is termed the Resolver-Angle. The output digital format provided by the RDC is termed the Digital-Angle.

In position measurement and control systems, an RDC interfaces between a Resolver type transducer, which generates analogue SINE/COSINE signals indicative of the rotation of some component coupled to the Resolver shaft, and some form of digital data processing equipment which performs further processing of the data provided by the RDC. In the context of this invention, a Resolver type transducer is taken to mean a Resolver or any other form of transducer which gives out analogue SINE/COSINE outputs or any other form of transducer which, with the intervention of an auxiliary component, can ultimately produce analogue SINE/COSINE outputs.

One type of RDC is known as a Tracking Resolver to Digital Converter (TRDC). A TRDC includes a pair of multiplying Digital to Analogue Converters (DAC) each for receiving the SINE and the COSINE analogue signals from the Resolver. The analogue outputs from the DACs are subtracted and the difference signal, also known as the Error Signal, is integrated and, through a closed loop feedback system, is used to update the Digital-Angle which is represented by the count of a binary up/down counter. The Digital-Angle is converted to digital SINE and COSINE signals which are fed back to the DACs in reverse order so that the digital SINE signal is fed to the DAC receiving the analogue COSINE signal from the Resolver and the digital COSINE signal is fed to the DAC receiving the analogue SINE signal from the Resolver.In effect the Digital-Angle is compared against the Resolver Angle and any difference is eliminated by the action of the feedback loop. The TDRC thus tracks the analogue Resolver angle providing an equivalent binary representation.

The accuracy of this type of converter is dependent upon a comparison of the incoming analogue signals and digital (binary) signals supplied to the DACs via the closed loop feedback system. If any single binary code is interpreted incorrectly by the DACs then the corresponding value of the output Digital-Angle will be in error.

According to the present invention, there is provided a TRDC for converting analogue signals from a Resolver transducer to Digital-Angle format comprising a first DAC for receiving the analogue SINE signal from the Resolver, a second DAC for receiving the analogue COSINE output signal from the Resolver and a feedback loop for nulling the difference of the outputs of the DACs and providing digital signals indicative of the analogue SINE signal for controlling operation of the second DAC and digital signals indicative of the analogue COSINE signal for controlling operation of the first DAC wherein the feedback loop includes means for supplying an Internal Reference signal so that digital words indicative of the analogue SINE and COSINE signals are modulated.

The feedback loop includes an accumulator.

Following is a description, by way of example only and with reference to the accompanying drawings, of one method of carrying the invention into effect.

In the drawings: Figure 1 is a circuit diagram of a known type of Tracking Resolver to Digital Converter, Figure 2 is a circuit diagram of an embodiment of a Dual Reference Tracking Resolver to Digital Converter in accordance with the present invention, and Figure 3 is a circuit diagram of another embodiment of a Dual Reference Tracking Resolver to Digital Converter in accordance with the present invention.

Referring now to Figure 1 of the drawings, there is shown a circuit diagram of a known type of Tracking Resolver to Digital Converter (TRDC) generally designated 10 comprising a pair of multiplying Digital to Analogue Converters (DAC) 11, 12 each for receiving from a Resolver (not shown) a corresponding one of two signals, one signal representing the COSINE and the other signal representing the SINE function of the displacement angle of the Resolver shaft. The output terminals of the DACs 11, 12 are each connected to a respective one of two input terminals of a difference amplifier 13 the output of which is connected to a closed loop feedback system comprising in series a phase sensitive detector 14, an integrator 15, a voltage controlled oscillator 16 and an up/down counter 17.The loop is completed by converting the output Digital-Angle 18 of the counter 17 into SINE and COSINE components which are supplied to the DACs 11, 12 respectively. The conversion of the Digital-Angle 18 into SINE and COSINE components is performed by on-board sine and cosine look-up tables 19 and 20 respectively.

The arrangement is such that any difference in magnitude of signal received at the input terminals of the amplifier 13 results in an error signal at the output of the amplifier 13 represented as:- Error = V SIN(wt) SIN(theta)COS(phi) - COS(theta)SIN(phi)] which by trigononmetry is equivalent to Error = V SIN(wt) SIN(theta - phi) where V : is a constant dependent on the amplitude of analogue signals received from the Resolver W : is the angular frequency of the Resolver Reference Signal theta : is the Resolver-Angle phi : is the Digital-Angle output The output of the amplifier 13 is demodulated by the phase detector 14 which removes the AC component of the error signal providing a base-band signal in the form SIN (theta - phi).

This signal is fed to the integrator 15 which then feeds the voltage controlled oscillator 16 which in turn feeds the up/down binary counter 17. The output of the counter 17 feeds back to the DACs 11 and 12 through separate signal paths, one path via the SINE look-up table 19 and the other path via the COSINE look-up table 20, thus forming the closed loop feedback system.

The action of the closed loop feedback system is such that the TRDC compares the incoming Resolver angle theta with the Digital-Angle phi 18 trying to minimise their difference.

This comparison is an indirect one, because it involves the products SIN(theta) * COS(phi) and COS(theta) * SIN(phi).

Since there is one unique DAC input code for every different value of the Resolver angle theta, DACs 11, 12 are required to interpret correctly each and every binary code supplied by the look-up tables 19 and 20. This requirement imposed on the DACs 11, 12 is seldom satisfied (except possibly in the case of rare and very expensive DACs), consequently the accuracy of the TRDC 10 is compromised.

It is desirable, therefore, to provide an improved TRDC which is more tolerant to the inaccuracy attributable to the DACs.

Referring now to Figure 2 of the drawings, there is shown a circuit diagram of an embodiment of a Dual Reference TDRC, generally designated 21, in accordance with the present invention comprising a pair of multiplying Digital to Analogue Converters (DACs) 22, 23 each for receiving from a Resolver (not shown) a corresponding one of two signals, one signal representing the COSINE and the other signal representing the SINE function of the displacement angle of the Resolver shaft.

The output terminals of the DACs 22, 23 are each connected to a respective one of two input terminals of a difference amplifier 24. The output of the amplifier 24 is connected to a closed loop feedback system comprising an A/D converter 25 in series with a first demodulator 26, a second demodulator 27, a digital filter 28 and an accumulator 29. The output 30 of the accumulator 29 is converted via two look-up tables 31 and 32 to separate SINE and COSINE components which are fed respectively to digital inputs of the DACs 22, 23 via respective modulators 33, 34. Operation of the second demodulator 27 and of each of the modulators 33, 34 is controlled by the Internal Reference produced by a digital synthesizer 35 and control of the first demodulator 26 is effected by signals received from an A/D converter 36 the input of which receives an (External) Reference signal of the Resolver.

The form of the Internal Reference waveform is typically sinusoidal with frequency higher than that of the External Reference Signal. The name DUAL REFERENCE TRDC is due to the presence of this second, Internal Reference, signal.

In operation, digital words representing the SINE and COSINE functions of the Digital-Angle phi are multiplied (modulated) by the Intenal Reference signal and fed to the DACs 22, 23 respectively. The output terminals of the DACs 22, 23 are each connected to a respective one of two input terminals of the difference amplifier 24, the output of which is connected to the A/D converter 25 where the signal is converted to digital format. This binary form of the error signal is demodulated by the demodulators 26, 27 under control of the External and Internal references supplied to the demodulators 26, 27 respectively and the necessary signal filtering and frequency compensation is provided for as the signal subsequently passes through the digital filter 28 whereby a set of zeros and poles are inserted to ensure the stability of the closed loop system.The resulting signal is used to correct the output Digital-Angle phi, which is represented by the accumulated count in the binary accumulator 29, in accordance with well established rules of feedback theory. Like the known type of TRDC shown in Figure 1, the Dual Reference TRDC shown in Figure 2, under loop equilibrium conditions and constant Resolver-Angle theta, outputs a constant Digital-Angle phi. Unlike the known type of TRDC, binary data fed to the DACs 22, 23 in the Dual Reference TRDC are continuously varying functions, changing in sympathy with the Internal Reference signal.

Thus, many different binary codes of the DACs 22, 23 are involved for any given value of the Resolver-Angle (theta) and this implied 'averaging' of the DAC codes results in improved accuracy of the Dual Reference TRDC 21 compared with the TRDC 10 known hitherto.

Referring now to Figure 3 on the drawings, there is shown a circuit diagram of another embodiment of a TRDC 37 in accordance with the present invention which is similar to the TRDC 21 shown in Figure 2 except that the components 26 to 35 inclusive have been combined in a single digital signal processor 38.

An additional advantage arises from the fact that DC offsets, arising in the part of the circuit 38 between the Modulators 34, 33 and the second Demodulator 27, do not correlate with the Internal Reference consequently being eliminated by the Demodulator 27. Thus any errors which may have resulted from DC offsets in the analogue part of the circuit are removed.

Similarly any DC offset deliberately inserted in the same part of the circuit 38, i.e. between the Modulators 34, 33 and the second Demodulator 27, have no effect on the Digital-Angle output of the Dual Reference TRDC 21. Consequently, the binary numbers fed to the DACs 22, 23 may be constrained to +ve numbers only by adding a suitable +ve offset.

Simplification of the design of the DACs 22, 23 therefore is effected because only two quadrant operation is required.

Furthermore, since in the present invention the conventional up/down counter has been replaced by an accumulator 29 capable of incrementing by more than one count at a time, the tracking speed of the TRDC is improved.

It will also be appreciated that, since a TDRC in accordance with the present invention relies less on drift-prone analogue parts, it is less subject to temperature and time drift compared with TRDCs known hitherto.

Claims (11)

1. A method of converting to digital form positional information provided by a resolver, the method including the steps of:taking respective analogue sine and cosine signals from the resolver and multiplying them with respective analogue converted digital internal signals representative of resolver cosine and sine functions to produce two outputs; producing a demodulated error signal using the two outputs according to a digital reference signal; using the demodulated signal to produce looked up signals representative of sine and cosine functions; and modulating the looked up signals according to the digital reference signal for use as said internal signals.

2. A converter for converting analogue resolver information to digital format, the converter comprising:first DAC means for producing a multiplied output from a received input signal representative of a cosine function and an analogue sine component received from the resolver, and second DAC means for producing a multiplied output from a received input signal representative of a sine function and an analogue cosine component received from the resolver; and substraction means including demodulation means for producing a demodulated error signal from said two outputs according to a digital reference signal, feedback means for receiving the demodulated error signal and producing therefrom signals representative of resolver sine and cosine functions, and modulating means for modulating the representative signals according to the digital reference signal for use as said internal signals.

3. A converter as claimed in claim 2 wherein said feedback means includes a digital filter.

4. A converter as claimed in claim 3 wherein said feedback means includes an accumulator for counting output signals from the filter.

5. A converter as claimed in any one of claims 2 to 4 wherein said feedback means includes look up tables containing sine and cosine functions for the resolver.

6. A converter as claimed in any one of claims 2 to 6 including a digital synthesizer for supplying said digital reference signal.

7. A converter as claimed in claim 6 wherein said reference signal is typically sinusoidal.

8. A converter as claimed in any one of claims 2 to 7 wherein said demodulation means includes comparison means for producing an error output from said two outputs, first ADC means for converting the error output to a digital format and producing a first demodulated signal according to a digitalized resolver reference signal, and second demodulation means for producing said demodulated error signal.

9. A converter as claimed in claim 8 wherein said second demodulation means, said reference means and said modulation means comprise a single digital signal processor.

10. A method of converting to digital form positional information provided by a resolver substantially as herein described with reference to figures 2 and 3.

11. A converter for converting analogue resolver information to digital format substantially as herein described with reference to figures 2 and 3.