GB2239147A

GB2239147A - Digital mobile communications clock extractor

Info

Publication number: GB2239147A
Application number: GB9015175A
Authority: GB
Inventors: Martin Greenwood
Original assignee: Individual
Current assignee: Individual
Priority date: 1989-12-13
Filing date: 1990-07-10
Publication date: 1991-06-19
Also published as: GB9015175D0

Abstract

Digital mobile communications apparatus, such as a cordless telephone, having clock recovery to enable sampling of the input signal, comprises a reference signal generator (40, 42) which provides a reference signal to a phase error adder (44) operating on the basis of modulo-arithmetic in a feedback loop which also provides frequency tracking, the feedback loop having single point gain adjustment for bandwidth control of two digital integrators (51, 54 and 56) which are clocked at differing speeds. When enabled, the up/down counter 42 accumulates the one-bit quantized value of the phase error by either counting up or down. <IMAGE>

Description

Digital Mobile Communications Clock Extractor This invention relates generally to radio equipment which is designed to receive binary digital signals, more especially but not exclusively CT2 digital cordless telephones, GSM cellular telephones and DECT digital cordless telephones.

The invention concerns apparatus which extracts timing information from the received signal so that the received signal may be sampled at the optimum instants between bit boundaries to generate a serial stream of digits. Such apparatus is commonly referred to as a "clock extractor" or "clock recovery circuit".

In general, the invention aims to provide improved clock recovery apparatus which reduces the amount of hardware necessary to achieve efficient sampling and is also able to minimise power consumption.

Typical clock recovery apparatus in accordance with the prior art is shown in Figure 1 of the accompanying drawings. A reference signal generator 10 having an input from a fixed frequency oscillator 12 provides an output to a phase error measurement circuit 14 which also receives the input signal 16. The phase error measurement signal is fed back via a filter 18 to the reference signal generator 10 in order to adjust the phase of the generated reference signal. The output of the reference signal generator is also fed to a sampler 19 which receives the input signal in order to provide the output data stream 20 in serial binary format.

This relatively simple known circuit is a first order clock extractor which has a phase correction feedback loop. It is also known in more complex apparatus to take into account second order errors arising from frequency variations in the input signal, for example by means of frequency error measurement and feedback.

According to the present invention, there is provided mobile communications apparatus with clock recovery, comprising a reference signal generator, a phase error measurement circuit receiving the input signal and the reference signal, and a feedback loop whereby the phase error measurement signal is fed back to the reference signal generator, together with a sampler receiving the input signal and the reference signal, wherein the reference signal generator comprises a free-running counter fed from a fixed frequency oscillator, together with an adder which receives the output of the counter and the feedback signal in order to effect phase adjustment by moduloarithmetic addition.

According to a further feature, the phase error measurement signal is fed back to the reference signal generator via a filter, and, at the stage of phase error measurement, a quantizer is provided for quantizing the phase error measurement signal to one bit value before it is fed to the filter.

The step of one bit quantization of the phase error measurement signal is generally applicable, whatever the practical circuits employed for phase adjustment and sampling. Thus, in all cases, the step of quantization simplifies both the measurement of the relative phase of the input signal and the filtering of the phase error measurement signal. For instance, and without loss of generality of the foregoing, the step of measuring the phase error can be reduced to simply latching the sign bit of the reference signal, whilst the filter can be simply an up/down counter instead of an adder/latch combination.

As well as simplifying the hardware, there are performance advantages to be gained. In digital mobile communications, burst errors tend to be a problem. The phase error tends to switch between jittering a small amount about the mean position, and having periods of wild fluctuation. By clipping the error at one bit, the effect of such large perturbations is substantially reduced without affecting the ability of the apparatus to track the small phase changes which accompany frequency drift of the bit rate.

According to a further feature, in order to provide frequency tracking, the feedback loop includes two integrators with predetermined gains, the second integrator receiving the output of the first integrator whilst the outputs of the two integrators are summed before being fed back to the reference signal generator, the second integrator being clocked at a different, preferably substantially slower, rate compared with the first integrator.

Each integrator may be the combination of an adder and a latch.

Conveniently, the first integrator may be clocked at the bit rate of the output signal or at each valid edge transition in said signal, whilst the second integrator may be clocked at a fixed rate which is a small fraction, for example 1/144th, of the bit rate.

According to still another feature, the feedback loop provides frequency tracking by means of integrator means, and bandwidth control in the feedback loop is effected by means of gain adjustment at a single point in the loop in such a manner that both the response time and the damping rate are altered.

Any one or more of the above-described differing features may be combined with the invention, but in a preferred embodiment to be later described all the differing features are incorporated in an improved clock extractor.

The invention is exemplified in the following description, making reference to the accompanying drawings, in which: Figure 1 shows the prior art; Figures 2 to 5 respectively show clock recovery apparatus in accordance with the differing features previously described, the invention being exemplified with reference to Figure 4; and Figure 6 shows a preferred embodiment.

In Figures 2 to 6, the same reference numerals as in Figure 1 are employed for corresponding parts.

Figure 2 illustrates a clock extractor with one-bit phase error quantization, in accordance with the invention claimed in Patent Application No. 8928174.5. The input signal is compared with an internally generated reference signal, to generate a signal which represents the phase error between the bit-boundaries on the input signal and the phase of the reference signal. In conventional clock extractors, the phase error is then digitally filtered, fed back and used to adjust the phase of the frequency reference. In the clock extractor of Figure 2, however, the phase error is quantized at the phase error measurement circuit 14A to a one-bit value before it is filtered at filter 18A.

The reference signal, which has had its phase adjusted to match that of the incoming signal, is used to sample the incoming signal and generate the serial binary data.

Figure 3 illustrates a second order clock extractor with different clock speeds for two integrators, generally referenced 22 and 24. As a whole, the system measures the phase error between the input data transitions and the reference signal, filters the error, and uses the filtered signal to adjust the phase of the reference signal. The reference signal specifies the times at which the input signal is sampled.

As is usual in a second order clock extractor, there are two stages of numeric integration. In Figure 3, the two integrators 22, 24 are each illustrated as the combination of an adder 22A, 24A and a latch 22B, 24B though if the phase error were quantized in accordance with Figure 1, the first integrator would be reduced to a counter. Each integrator increments the value of its output by the value presented to the adder each time it is clocked. Two gain constant controllers 26, 28, which determine gains kl and k2, control the dynamic characteristics of the system, though these controllers can be placed at points in the system other than as illustrated without affecting the generality of application of the invention.

When the system has stabilised, the output of the first integrator 22 stays fairly constant, and the second integrator 24 generates a continuous ramp. The ramping of the second integrator 24 corresponds to the frequency error of the received bit rate. It is to be noted that the ramp wraps round periodically as the integrator overflows, but this event corresponds to the phase going,through 3600 and back to 00. The rate of integration depends on both the gain applied at the inputs to the integrators 22, 24 and the rate at which the integrator 24 is clocked.

In some forms of known second order apparatus, the combination of relatively long fades and a slow rate of drift means the gain factor k2 has to be inconveniently small, and the word width of the integrator 24 correspondingly large to maintain accurate frequency tracking. If the second integrator 24 is clocked at a slower rate, however, the gain factor k2 can be made larger, reducing the number of logic gates in the second integrator.

The clock signal 30 to the second integrator 24 can be many times slower than the clock signal 32 to the first integrator 22. Clock signal 32 is typically either at the bit rate, or is clocked at every valid edge transition, whereas clock signal 30 can be at almost any fixed rate and can use whatever system clock might be suitable for the purpose. For instance, without the loss of generality of the foregoing, in a CT2 system, clock signal 30 can be provided by the 500 Hz clock which generates the burst rate, i.e. 1/144 of the bit rate. It is to.be noted that the gain factors kl and k2 are not critical and can be binary shifts of the form 2n, whatever the ratio of frequency between clock signal 30 and the clock signal 32.The feed back stability of the system ensures that the output of the first integrator 22 gives rise to the appropriate ramp rate in the second integrator 24 to ensure frequency tracking.

As well as the reduction in hardware, the technique reduces power consumption. In a CMOS ASIC implementation, for instance, most of the power is consumed by gate transitions.

The reduction in the switching rate of the second integrator reduces the power consumption.

Figure 4 shows a digital clock extractor in accordance with the present invention in which the reference phase is adjusted by using modulo-arithmetic addition. The basic feedback control apparatus is similar to that shown in the preceding figures but a different means of phase adjustment is employed.

It is usual for phase adjustment to be made by resetting the reference counter at a particular moment in.time. In the arrangement shown in Figure 4, however, the counter 34 is made free-running and the phase is adjusted by adding a variable modulo-arithmetic offset at adder 36.

This aspect of the invention makes use of the property of modulo-arithmetic that the numbers within the modulus range form a cyclic group under addition. For every number corresponding to the feedback signal, the phase of the adjusted reference signal output from the adder has been shifted relative to the phase of the free-running counter.

For instance, if 4-bit modulo arithmetic is used and the counter is a binary up-counter, a feedback value of 5 causes the following transformation: input output 0 5 1 6 2 7 3 8 4 9 5 10 6 11 7 12 8 13 9 14 10 15 11 0 12 1 13 2 14 3 15 4 Assuming the numbers represent a phase, the addition of the variable offset causes a variable phase shift.

There are several advantages to be gained from using this technique: (a) the adder can be combined with any adder present at the output of the loop filter (shown as filter 18 in Figure 4). A large number of extra gates are not required; (b) there is no requirement to generate an accurately timed reset pulse for the counter because it is left free running, so use of a timing circuit is unnecessary; (c) the process of measuring the phase error may neverthe less, if desired, simply be a matter of latching the adjusted reference count upon an edge transition of the input signal.

Figure 5 shows a second-order digital clock extractor with single-point gain adjustment, in accordance with the invention claimed in Patent Application No.

Reference numerals similar to those of Figure 3 are employed in Figure 5 for corresponding parts, as a matter of convenience.

Gain adjustment is useful in a clock extractor for mobile communications because it affects the rate at which the clock extractor locks. For instance, in a CT2 system, it is necessary for the clock recovery circuit to perform sampling correctly within ten bit periods of being presented with valid data, but once the call has been established it will have to remain locked during fades of the order 1,000 to 20,000 bits duration. Fast locking requires a high gain in the clock extractor, whilst immunity to fades requires a low gain.

In adjusting the bandwidth of a second-order control system, it is necessary to adjust the gain at two points if. the damping characteristics of the system are to remain fixed.

In the arrangement of Figure 5, however, the gain is adjusted at a single point 38 only, so that both the response time and damping rate of the system are altered.

When the system is locked and at its minimum gain and bandwidth, the normalised values of kl and k2 are very roughly equal. In that state the system behaves very much as a second-order system, with good frequency tracking and a slightly under-damped response. However, prior to locking, only kl has an increased value. This has two effects. Firstly, the relative influence of the second integrator 24, which performs the frequency tracking, is very much less. This means that the frequency tracking can adapt itself as the system locks, and while the bandwidth is being reduced, without much affecting the transient response.

Secondly, at high gains the arrangement behaves very much as a first order system, so that limit cycle oscillation is avoided, and the arrangement remains robustly stable whilst in a state where it is more prone to phase noise on the input.

Apart from the performance advantages, there are simplifications to the hardware. Not only is it possible for k2 to be fixed, which saves hardware, but the limiting slew rate of the second integrator 24 can be kept low. That means that only sufficient word width from the first integrator 22 has to be added to account for expected frequency drift, say 100 ppm. During the locking phase, the frequency compensation can be expected to saturate, but because the gain, k2, of that part of the circuit is low, this is not of consequence. Once the system is locked, kl is reduced and frequency compensation emerges from saturation and becomes effective again. Thus, by keeping the word width of the second integrator just wide enough to deal with the long term bit-rate error, the hardware requirement is further minimised.

Figure 6 shows the preferred embodiment, which incorporates all the features above described in combination with the present invention. Crystal oscillator 40 drives a counter 42 which generates a reference signal.

A combined adder 44 adjusts the phase of the reference signal by means of modulo-arithmetic addition (in this case, subtraction). The adjusted reference phase is passed to a decoder 46 which generates two pulses, both at bit rate. One pulse passes to latch 48 where it samples the input signal, generating the output serial data.

The other is a square wave and is sampled when there is a transition of the input signal.

The input signal also passes through a latch where it is slightly delayed and gated with the thus delayed signal to generate pulses corresponding to the times of edge transitions. When the square wave is sampled in latch 50, it will produce a one if the edge is late, or a zero if the edge is early. These ones and zeros are fed back to up/ down counter 51 for direction control.

Each input edge causes the up/down counter 51 to count in the appropriate direction. A freewheel input 52 may be used to block the edges, if the transitions are known to be unreliable. When enabled, the up/down counter 42 accumulates the one-bit quantized value of the phase error by either counting up or counting down. Single point gain adjustment is made within the up/down counter 51 by selecting the word width of the counter. The counter 51 corresponds to the first integrator 30 shown in Figures 3 and 5.

The second integrator consists of adder 54 and latch 56.

Latch 56 is triggered by a separate clock, slow clock 58, which provides a pulse every 144 bits. Keeping the clock rate down means that the word width in the adder 54 and latch 56 is reduced. The summed outputs of the two integrators form the phase adjustment control signal, but a three-input adder 44 is used so that the determination of the adjustment value and the adjustment itself are effected in unison.

The preferred embodiment of Figure 6 makes good use of hardware, thereby keeping the cost of the design to a minimum. It does Sc without compromising the performance of the clock extractor and, indeed, its performance is better than many more complex systems and it is eminently suitable for integration in a digital mobile radio product. By offering full performance capability at a similar gate count to that used by much simpler systems, the arrangement will allow the consumer tc enjoy maximum retention of the calls made, but on less expensive equipment.

Claims

1. Digital mobile communications apparatus with clock recovery comprising a reference signal generator, a phase error measurement circuit receiving the input signal and the reference signal, and a feedback loop whereby the phase error measurement signal is fed back to the reference signal generator, together with a sampler receiving the input signal and the reference signal, wherein the reference signal generator comprises a free-running counter fed from a fixed frequency oscillator, together with an adder which receives the output of the counter and the feedback signal in order to effect phase adjustment by modulo-arithmetic addition.

2. Apparatus according to claim 1, wherein the phase error measurement signal is fed back to the reference signal generator via a filter and, at the stage of phase error measurement, a quantizer is provided for quantizing the phase error measurement signal to one bit value before it is fed to the filter.

3. Apparatus according to claim 1 or claim 2, wherein, in order to provide frequency tracking, the feedback loop includes two integrators with predetermined gains, the second integrator receiving the output of the first integrator whilst the outputs of the two integrators are summed before being fed back to the reference signal generator, the second integrator being clocked at a different, preferably substantially slower, rate compared with the first integrator.

4. Apparatus according to claim 3, wherein each integrator comprises the combination of an adder and a latch.

5. Apparatus according to claim 3 or claim 4, wherein the first integrator is clocked at the bit rate of the input signal or at each valid edge transition in said signal, whilst the second integrator is clocked at a fixed rate which is a small fraction, for example 1/144th, of the bit rate.

6. Apparatus according to any of claims 1 to 5, wherein the reference signal generator comprises a free-running counter fed from a fixed frequency oscillator, together with an adder which receives the output of the counter and the feedback signal in order to effect phase adjustment by modulo-arithmetic addition.

7. Apparatus according to any of claims 1 to 6, wherein bandwidth control in the feedback loop is effected by means of gain adjustment at a single point in the loop in such a manner that both the response time and the damping rate are altered.

8. Digital mobile communications apparatus with clock recovery substantially as hereinbefore described with reference to Figure 4 or Figure 6 of the accompanying drawings.