GB2237484A

GB2237484A - Speech codec replaces noise affected codewords

Info

Publication number: GB2237484A
Application number: GB8922962A
Authority: GB
Inventors: Leslie Derek Humphrey; Andrew David Wallace
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1989-10-12
Filing date: 1989-10-12
Publication date: 1991-05-01
Anticipated expiration: 2009-10-12
Also published as: CA2026924A1; GB8922962D0; GB2237484B; FI904768A0; EP0422802A1

Description

SPEECH CODEC ARRANGEMENT This invention relates to speech codec

arrangements for muting a voice band signal when the error rate in an ADPCM channel exceeds a predetermined threshold.

When the error rate in a digital speech channel becomes excessively high the listener can be subjected to unacceptably high level bursts of noise.

It is an object of the present invention to provide protection for the listener when the error rate becomes high by automatic muting and/or attenuation of the channel signal dependent on the error rate.

According to the invention a speech codec arrangement includes in the decoder means for detecting predetermined illegal codewords in a received coded bit stream, means for generating a muting control signal in response to detection of illegal codewords, means for generating preferred codewords and means responsive to said muting control signals to replace detected illegal codewords with preferred codewords.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which:- Fig. 1 is a schematic diagram of an illegal codeword muting arrangement for an ADPCM decoder, Fig. 2 is a schematic diagram of an alternative arrangement to that of Fig. 1, Fig. 3 is a schematic diagram depicting a modified ADPCM encoder, Fig. 4 is a schematic diagram of muting arrangement for a modified ADPCM channel, Fig. 5 is a schematic diagram of an alternative arrangement to that of Fig. 4.

Fig. 6 shows a modified form of the muting arrangement of Fig. 1, and Fig. 7 shows a modified form of the muting arrangement of Fig. 4.

In the following description references to ADPCM codecs relate to Adaptive Differential PCM codecs with particular relevance to codecs referring to CCITT G721 standards.

In the arrangement shown in Fig. 1 the ADPCM input to G721 decoder 10 is also fed to an illegal code detector 11 the output of which is applied to a muting control circuit 12. The arrangement exploits the fact that a code of 0000 should never be received by a G721 ADPCM decoder operating over an error free transmission channel.

However, in the presence of errors in the transmission channel the four valid codes 0001, 0010, 0100 and 1000 can each be transformed into the illegal code 0000 by corruption of a single bit. Each time that an illegal code 0000 is received the iilegal code detector 11 produces an output signal, e.g. a logic level 'high. The muting control circuit 12 conveniently comprises a filter followed by a comparator. The filter output may be used directly as an indication of the i - 3 current bit error rate. This output is then compared against a predetermined threshold to provide a muting control signal when the threshold is exceeded. The comparator may usefully have a defined amount of hysteresis to give the muting control circuit a minimum hangover time. The muting control signal is applied to control a multiplexer 13. The PCM output of the G721 decoder is fed as one input to the multiplexer. -An idie code generator 14 provides the other input to the multiplexer. When a muting control signal is present the multiplexer replaces the output of the decoder with idle codes. This method of operation of the muting process allows the decoder to operate as far as possible in synchronism with the encoder, even when the muting control is enabled.

In the alternative arrangement shown in Fig. 2 the muting control acts on the input to the G721 encoder. The incoming code stream is intercepted by the multiplexer 13 before it reaches the decoder. When. illegal code groups are detected by the detector 11 the arrangement acts to substitute idle code groups, e.g. 1111 for the illegal code groups in the input to the decoder. This will cause the output of the decoder to decay down to zero over a short period of time, typically a few milliseconds, but prevents any possibility of the decoder remaining roughly in synchronisation with the encoder.

The filter and comparator circuits can be implemented in either analogue or digital circuitry. For example an RC low-pass filter with a suitable time constant can be used as an analogue filter, or a leaky integrator can be used as a digital filter. Similarly an operational amplifier with a small amount of positive feedback, or its digital equivalent, can be used as the comparator with hysteresis.

Fig._3 shows how the encoder in a G721 ADPCM codec can be modified by the addition of a block parity encoder. Parity checking is a well-known technique used for detecting errors in digital bit streams. In the present case the ADPCM code stream from the G721 encoder 20 is intercepted by the block parity encoder 21. For parity encoder purposes the start of a block is defined by the occurrence of a 1111 code in the G721 encoder output. This 1111 code is transmitted if the parity of the previous block is even. If the parity of the previous block is odd then the 1111 code is replaced by a 0000 code.

For the decoder 10, Fig. 4, the incoming bit stream is intercepted by a block parity checker circuit 15, which considers blocks to be delimited by 0000/1111 codes. If code 0000 is considered to have odd parity then the parity of a block should always be even, and a block which has odd parity is therefore a direct indication that an error has occurred within that block. Note that there is no need to replace the incoming 0000 code by the original 1111 code because the G721 decoder handles both codes in exactly the same manner. As in the arrangements of Figs. 1 & 2 so in the arrangement of Fig. 4 the output of the block parity checker is applied to a muting control circuit 12 which causes multiplexer 13 to insert idle codes in place of the error containing codes in the output of the decoder 10. The arrangement of Fig. 5 corresponds to that of Fig. 2, wherein the codes deemed to contain errors, as determined by the block parity checker 15, are replaced by idle codes before the code stream enters the decoder.

The filter comparator can be implemented as in the arrangements of Fig. 1 or 2, although for Fig. 4 or 5 it may be preferable to use a digital filter which is clocked only on incoming parity block boundaries. This 1 4 1 would prevent the muting action from being removed should the time between 0000'and 1111 codes become large, as can happen during a loud speech burst.

In any of the embodiments described above simple muting can be replaced by a more elaborate arrangement employing variable attenuation such that the output signal level of the decoder reduces progressively as the error rate increases. This technique is illustrated in Figs. 6 and 7 which show modifications of Figs. 1 and 4 respectively. In the arrangement of Figs. 5 and 6 the output of the decoder 10 is progressively attenuated by the attenuator 21 as the bit error rate determined via the rate estimation filter 22 increases. This would give the user feedback about e.g. the location of radio nulls to be avoided in personal radio communications terminal applications.

Claims

1. A speech codec arrangement including in the decoder means for detecting predetermined illegal codewords in a received coded bit stream, means for generating a muting control signal in response to detection of illegal codewords, means for generating preferred eddewords and means responsive to said muting control signals to replace detected illegal codewords with preferred codewords.

2. An arrangement according to Claim 1 wherein said means for replacing is arranged to replace illegal codewords with preferred codewords in the input to the decoder.

3. An arrangement according to claim 1 wherein the decoder comprises a code conversion means, said detecting means is arranged to detect illegal codewords in the bit stream input to the decoder and said means for replacing is arranged to replace illegal codewords with preferred codewords in the bit stream output of the decoder.

4. An arrangement according to claim 1, 2 or 3 wherein said preferred codewords are idle codes.

5. An arrangement according to any preceding claim wherein said detecting means comprises block parity checking means for received signals incorporating block parity signals.

6. An arrangement according to any preceding claim wherein said preferred codewords include a variable attenuation component whereby the output signal level of the decoder reduces progressively as the rate of illegal codewords increases.

7. A speech codec arrangement substantially as described with reference to Figs. 1, 2, 4 or 5 of the accompanying drawings.

8. A communications device incorporating a speech codec arrangement as claimed in any one of the preceding claims.

Published 1991 at 7be Patent Oflice. State House. 66/71 High Holborn. London WCIR 47P. Further copies may be obtained from Sales Branch. Unit 6, Nine Mile PbInt. Cwnlinfach. Cross Keys. Newport. NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray, Kent.

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