GB2236593A

GB2236593A - Electromagnetic field detector

Info

Publication number: GB2236593A
Application number: GB9017401A
Authority: GB
Inventors: Janet Heather Driver; Leonard Arthur Driver
Original assignee: Individual
Current assignee: Individual
Priority date: 1989-08-25
Filing date: 1990-08-08
Publication date: 1991-04-10
Anticipated expiration: 2010-08-08
Also published as: GB2236593B; GB9017401D0

Abstract

A detector for detecting e.g. radiation from household microwave devices comprises an antenna (2) a diode detector D1, an amplifying arrangement e.g. a multistage integrated circuit which is screened (4) against non-ionising radiation, and an indicator BZI which is operated (UID) when the detected field of strength causes a reference (13, R12, R13, R16) to be exceeded (12). The detector may include a wide-band suppression state (C2, R1) which suppresses interference signals such as electrostatic or electromagnetic pick-up. <IMAGE>

Description

Electrical Signal Detector The present invention relates to a signal detector circuit for detecting electrical signals preferably, but not exclusively, microwave frequency signals.

With the increasing use of microwave devices, particularly in the house, there has arisen the need for apparatus capable of detecting the leakage of radiation form apparatus using such devices.

The present invention provides an electrical signal detector comprising a low bias operational amplifier arranged to detect very small input voltages and activate indicating or monitoring circuitry.

The present invention also relates to apparatus for suppressing interference signals, such as electro-static/electromagnetic pickup.

It is known to suppress interference signals in electrical equipment by screening leads and connections, using metal foil or braiding or to utilize filter circuits of varying degrees of complexity.

Despite the prevalence of the problem there is still a need for a simple wide-band suppression technique.

The present invention provides apparatus for protecting input stages of amplifiers from the effects of electrical charges generated by static electricity or other interfering signals.

The apparatus is preferably used with high gain amplifiers and is most useful with radio frequency signals.

The present invention also seeks to provide an electrical signal detector in which variations in component parameters (such as op-amp input offset voltages) occurring during mass production are compensated for, preferably by means of a voltage biassing arrangement.

The detection preferably comprises a multistage device in which each stage is implemented using an op-amp from a multi-op-amp (e.g. quad) integrated circuited (IC). The IC is preferably screened to reduce possible induced effects from the non-ionising radiation field, for example using aluminium foil or a similar shielding material positioned locally in the direct path between the source of the signal and the IC.

In order that the present invention be more readily understood, embodiments thereof will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows a circuit diagram of a microwave radiation detector according to a first embodiment of the present invention; Figure 2 illustrates a circuit diagram of a detector according to a second embodiment of the present invention, employing interference suppression stage; Figure 3 shows an equivalent circuit diagram of the interference suppression stage of Figure 2; Figure 4 illustrates a modified form of the interference suppression stage of Figure 2; Figure 5 shows a circuit diagram of a microwave radiation detector according to a third embodiment of the present invention.

Microwave radiation detector according to the present invention is based on a programmable operational amplifier such as that sold under the trade name Lincmos and the designation TLC 271 or TLC 251 and indicated by the reference numeral 10 in the drawing.

The input pins 2 and 3 of the amplifier 10 are connected via input resistors 12 and 13 respectively to input terminals (not shown). The pin 3 is the non-inverting input which is grounded through the input resistor 13 and the amplifier is used in the open input resistor 13 and the amplifier is used in the open loop mode. A folded dipole antenna 15 is connected to the input terminals of the amplifier and is thus effectively connected to the negative common rail and so ground to reduce risks due to electrostatic charges and off frequency interfering signals.

The folded dipole antenna feeds via a DC blocking capacitor 16 to a microwave diode detector 17 connected across the input pins 2 and 3 of the amplifier 10. A negative voltage proportional to the magnitude of the incident microwave energy centered on the tuned frequency of the antenna 15, in this case 2.45 GHz + 150 HHz, is fed to the inverting input resulting in the output pin 6 swinging positive.

The output from the amplifier 10 is fed via a resistor 19 to activate an output stage which in this case is a piezoelectric oscillator sounder 20 drive by a transistor 21. The sensitivity of the circuit is determined by the setting of the variable resistors 22 and 23 which constitute a potential divider.

The above arrangement with the values given on the drawing will detect microwave radiation centered on 2.45 GHz at distances of more than 2 metres which is an indication of a leaking door seal of a microwave oven.

The sensitivity, i.e. range, can be adjusted by the introduction of a range of selectable resistors forming the potential divider at the output of the amplifier.

A folded dipole is the preferred antenna arrangement rather than a monopole or half wave dipole as it matches to 240 ohms instead of 50 ohms and gives adequate bandwidth with a satisfactory "Q".

It has been found that if the folded dipole antenna and decoupling capacitor are removed, the circuit can detect minute electrical waves such as are generated by electrical power cables which are not passing load current but do have the supply switch 'on'.

The output circuitry can be adapted to give a wide variety of indicators or recording equipment.

Further, the circuitry can be housed to be portable or it may be portable or it may be fixed a specified distance from an appliance to be monitored.

Either form is possible since all components including the power source are incorporated in a single package.

Figure 2 shows a second embodiment microwave leakage detector. This embodiment includes an optional stage which comprises a resistor R1 and electrolytic capacitor C2 connected in parallel, all the other components being associates with microwave detection and monitoring. Capacitor C2 is connected with its positive terminal to ground, and resistor R1, a leakage resistor is connected paralleled with it. Resistor R1 may sometimes be omitted entirely.

If one refers to the equivalent circuit in Figure 3 and initially considers the circuit without the presence of resistor R1, went he input goes positive with respect to the ground rail, so does point A (assuming that the input frequency is high enough for capacitor C1 to the taken as a short-circuit) and dipole Dl conducts. This causes the amplifier output to go negative.

When the input signal goes negative with respect to the ground rail, so does point A, and diode D1 is reversed biased, so negligible current flows through it. Capacitor C2 will partially change but to no significant level, and will discharge the positive half-cycle.

If static pick-up is experienced then the potential of the ground rail will be raised to a high level. If this is greater than that at point A, capacitor C2 will charge for as long as the static condition is present or until it is fully charged. on removal of the static input, the ground level will try to return to zero volts but the result will depend on the discharge rat of capacitor C2. In the absence of resistor R1 the only route available for this discharge is the revers biased diode D1 and its very small reverse current. The amplifier will tend to lock on if capacitor C2 remains charged as a result of repeated static inputs.

To ensure capacitor C2 can discharge fully resistor R1 is introduced. This provides a controlled discharge path for capacitor C2 between point A and ground ensuring rapid decay and return to normal conditions. This prevents the amplifier locking up. An alternative is to replace resistor R1 by a diode D2 as shown in Figure 4 which has the same effect.

This technique eliminates electrical static charges and their effect on the input stages of amplifiers coupled to a receiver, antenna or other devices used to detect transmitted signals ranging from low frequency levels in the range of 100Hz to high frequency levels in the range of 100Hz. It could also be applied to any similar circuit configuration and eliminates the need for costly and complex solutions to problems caused by statically or electromagnetically induced signals.

Referring to Figure 5, this shows a circuit diagram of a microwave radiation detector according to a third embodiment. The configuration of the folded dipole antenna, dc blocking, capacitor C1, diode D1, and interference suppression stage R1.C2 is the same as described with reference to the first and second embodiments, except that, in the detector, diode D1, and interference suppression stage R1.C2 are mounted inside a non-ionising radiation screen 4 made of aluminium foil or plate, or other suitable screening material.

In the embodiment of Figure 5 the (LinCMOS) programmable op-amp (TLC251cp) has been replaced by a quad-op-amp integrated circuit (IC) U1 (a TLC 27L4), which has similar electrical characteristics to the former device. Each op-amp in the IC implements one of four stages in the detector.

The original generated in the antenna is fed via the interference suppression stage into the inputs 6,8 of the high gain differential amplifier stage 10, which is the first stage, formed by the first op-amp UIA of the IC. The voltage on the output 12 of stage 10 is directly proportional to the different between the voltages on the inputs 6,8 and the closed-loop gain of the subtractor (R4/R2). Variations in the input offset voltage of the op-amp UIA resulting from manufacturing spread are compensated for by means of a voltage bias arrangement connected to the non-inverting input of opamp UIA. The bias circuitry comprises a resistor network R5,R6,R15,R16.Resistors R14 and R15 form a voltage divider between the positive voltage supply rail Vcc and the ground rail, and resistors R5 and R6 form a voltage divider between the junction of resistors R14 and R15 and the zero rail 14 to be described later.

The voltage on the non-inverting input of opamp UIA, which is connected to the junction of resistors R5 and R6, is thus maintained at between 0.000 to 0.001 V for the range of input offset voltages encountered in practice. Since some manufacturers tolerance limits result in input offset voltages which may exceed 0.2V, compensation for this is provided by connecting pin 11 (the low voltage supply line for all four op-amps on the IC) to the zero rail.

The high value of the gain of stage 10 ensures that the detectors frequency response is inherently insensitive to mains frequencies and the like.

The output 12 of the first stage 10 is fed to the non-inverting input 5 of a second op-amp UIB in the second stage 16 via resistor R7. The second stage 16 provides a low level of gain (approx. 6) and forms a conventional non-inverting amplifier.

The output 18 of stage 16 is fed to the third stage 20 which forms a peak detecting stage. The output 18 is fed via resistor R10 to the non-inverting input 10 of a third op-amp UIC in the IC, which is configured as a peak detector. During operation, when the voltage on input 10 goes more positive than the voltage across capacitor C3, then the output of op-amp UIC is driven very positive, the diode D2 is forward biassed and the amplifier output 8 provides sufficient current to charge up capacitor C3 (towards the positive supply voltage Vcc).If the voltage on the input 10 is less (positive) than the voltage on capacitor C3, or drops below it during operation, then the voltage on the output 8 is low and diode D2 is highly reverse-biassed, so the voltage on capacitor C3 remains at its peak charged level until this is next exeeded, and with a stability dependent on the decay time constant of resistor Rll and Capacitor C3, which are connected in parallel.

The fourth stage 22 consists of the fourth op-amp U1D of the IC performing a Schmitt trigger function inthe conventional manner. The output 24 of stage 20 is fed to the input 12 of op-amp U1D. A voltage divider formed by resistors R12,R13 and R16 connected between Vcc and the zero rail 14 set a reference voltage for the Schmitt trigger which is applied to pin 13 of op-amp U1D. If, assuming the voltage at the output 24 is initially negative thenthe output 14 of the Schmitt trigger wil rise to a maximum voltage Umax equal to the positive saturation voltage of op-amp U1D. The circuit configuration in stge 22 ensures that the hysteresis of the Schmitt trigger involves a very fast ON-OFF transition.

The output 26 of the stage 24 directly drives a piezo buzzer BZ1, which has its other terminal connected to the zero rail 14. The piezo buzzer sounds when the output 14 of op-amp U1D goes into positive saturation (i.e. when the peak voltage derived fran the detected signal exceeds the referencevoltage on the inverting input 13 of op-amp UlD,so that the Schmitt trigger is ON).

The voltage supply rails Vcc,GND are provided by a 9V dc battery BT1, which enables the detector to be manufactured as a portable unit.

The zero rail (or virtual ground) is provided by diodes D3 and D4and forms a low voltage supply rail for the four stages of the detector. The diodes D3 and D4 are connected in series between the zero rail 14 and the ground (GND) 28 which iS connected to the negative terminal of the battery BT1. As a result of their forward voltage drops, diodes D3 and D4 create a voltage difference oft approximately 0.75 V between the zero rail 1e and the and rail 28. This voltage biassing arrangement enable s the voltage on pin 3 of UIA to be heldapprox. 0.000 V irrespective of input offset voltage variations of UI with different manufacturing sources, eliminating the need for a variable offset voltage trimmer.

A further advantage is that the detector is protected from effects of electrostatic/electro-magnet;c interference, as described above.

Further, a feature of the detectors design is that it has narrow band frequency of selectivity at 2456GHz.

Also, all of the components of the detector, with the exception of the folded dipole antenna 2, capacitor C1, buzzer BZ1 and battery BTl are screened in a compact arrangement by means of a screen 4 which prevents the effects of non-ionising radiation from corrupting the detected signal from the antenna within the interference suppress ion stage and the four subsequent stages performed by the IC.

Additionally, to improve the sensitivity of the detector, a capacitor C5 may be connected between the junction of resistors R5 and R6, and the ground rail.

Claims

CLAIMS:

1. An electrical signal detector, comprising: an antenna for receiving electromagnetic radiation and generating an electrical signal in response thereto; a frequency-selective detector circuit, including a high gain differential amplifier coupled to the antenna, for generating an electrical drive signal in response to the electrical signal; an indicator, coupled to the detector circuit; and activated by means of the electrical drive signal; wherein the electrical drive signal is generated when the amplitude of the electrical signal reaches a pre-determined value.

2. An electrical signal detector according to claim 1, wherein the high gain amplifier is coupled to the antenna by a static suppression circuit which includes a capacitor connected across the inputs of the amplifier.

3. An electrical signal detector according to claim 2, wherein: the static suppression circuit includes a resistor or a diode connected in parallel with the capacitor.

4. An electrical signal detector according to any of claims 1 to 3, wherein: the high gain amplifier comprises an op-amp in open-loop configuration, whose output is coupled to the indicator.

5. An electrical signal detector according to any of claims 1 to 3, wherein: the detector circuit includes a multi-stage circuit and the high gain differential amplifier comprises a first stage of the multi-stage circuit.

6. An electrical signal detector according to claim 5, wherein: the output of the first op-amp is coupled to the input of a second stage of the multi-stage circuit and the second stage is configured as a non-inverting amplifier having a gain of about 6.

7. An electrical signal detector according to claim 6, wherein: the output of the second stage is coupled to the input of a third stage of the multi-stage circuit, and the third stage is configured as a peak detector circuit.

8. An electrical signal detector according to claim 7, wherein: the output of the third stage is coupled to the input of a fourth stage of the multi-stage circuit, and the fourth stage is configured as a Schmitt trigger circuit which generates the electrical drive signal.

9. An electrical signal detector according to any of claims 5 to 8, wherein: the multi-stage circuit includes a multi-opamp integrated circuit (IC), and each of the first, second, third and fourth stages is implemented by means of a respective op-amp of the IC.

10. An electrical signal detector according to any of claims 5 to 9, wherein: the detector circuit includes, coupled to ground (GND) voltage supply line thereof and to an input of the differential amplifier, a biassing network for providing a zero voltage supply line; whereby the voltage level on the zero voltage line is substantially unaffected by variations in the input offset voltage of the differential amplifier.

11. An electrical signal detector according to claim 10, wherein: the biassing network includes: (a) one or more diodes and a resistor connected in series between the zero voltage line and the ground line; and (b) a plurality of resistors connected in parallel with (a), one of said resistors forming part of a voltage dividerbetween the positive voltage supply line of the detector and the ground line.

12. An electrical signal detector according to any of claims 5 to 11, wherein: the detection circuit and the static suppression circuit are mounted in an enclosure formed by a metallic screening material.

13. An electrical signal detector according to any of the preceding claims, wherein: the antenna comprises a folded dipole antenna.

14. An electrical signal detector according to any of the preceding claims, wherein: the indicator comprises a piezo buzzer.

15. An electrical signal detector according to any of the preceding claims, wherein: the frequency of maximum sensitivity of the detector lies in the range 2300 MHz to 2600 MHz.

16. An electrical signal detector substantially as hereinbefore described with reference to figure 1, figures 2 to 4 and figure 5 of the accompanying drawings.