GB2233496A - Preventing latchup in cmos circuits - Google Patents
Preventing latchup in cmos circuits Download PDFInfo
- Publication number
- GB2233496A GB2233496A GB9013026A GB9013026A GB2233496A GB 2233496 A GB2233496 A GB 2233496A GB 9013026 A GB9013026 A GB 9013026A GB 9013026 A GB9013026 A GB 9013026A GB 2233496 A GB2233496 A GB 2233496A
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- Prior art keywords
- mosfet
- well
- substrate
- latchup
- channel
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- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000003071 parasitic effect Effects 0.000 claims description 29
- 230000001965 increasing effect Effects 0.000 claims description 6
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Latchup protection is provided for an integrated circuit containing adjacent MOSFETS 7, 9 of opposite channel types integrated into a single substrate 10 in which one MOSFET is contained in a doped well 8 having polarity type opposite that of the substrate. The well has an extension 50 over a region adjacent the other MOSFET of such length so as to increase its resistance to a degree sufficient to increase latchup trigger current. Alternatively the distance between the source and drain of a MOSFET may be reduced and the p-well length maintained the same. <IMAGE>
Description
TECHNIQUE FOR IMPROVING LATCHUP IN CMOS CIRCUITS
-1
This invention relates to a latchup protection means for a CMOS integrated circuit.
Integrated CMOS circuits can contain parasitic bipolar devices associated with their internal structures. These parasitic devices can be interconnected in such a way as to form four-layer latch devices. In such cases, the parasitic latch devices can become connected directly across two voltage power supply rails used with the CMOS circuits.
A parasitic latch device is normally in its off state and will remain off as long as the minimum threshold current required to turn the device on is not exceeded. In the off state the latch device presents a very high impedance between the voltage rails. The normal way that a parasitic latch device is turned on is by current being forced into the input or output of the CMOS circuit that incorporates it.
This current is known as a trigger current and is defined as the minimum threshold current required to turn on a parasitic latch device and may be in the form of a pulse, series of pulses, or as d.c. A positive feedback arrangement that exists within the parasitic latch device ensures that the latch device remains on even if the trigger current is interrupted.
A parasitic latch device that is on is said to be in latchup. Latchup is defined as the creation of a stable low impedance current path between two power supply rails to which a CMOS circuit is connected. Since the latch device is switched into a low impedance state, large currents can flow through the CMOS circuit connected between the power supply rails. The high currents have the potential of destroying and/or rendering the CMOS circuit inoperable. Thus protecting CMOS integrated circuits from latchup is a major concern.
Over the years, designers have attempted to improve the ability of a CMOS circuit to withstand the triggering stimuli and to raise the threshold at which latchup occurs.
Designers of prior art circuits utilized "guard rings" surrounding and separating transistors prone to forming parasitic latch devices at the input or output (I/O) circuitry of CMOS circuits.
This is known in the prior art as guardbanding. In guardbanding, N-channel transistors are surrounded by
P+ doped diffused rings and P-channel transistors are surrounded by N+ doped diffused rings. N+ doped diffused rings are connected to a positive voltage source and P+ doped diffused rings are connected to a negative voltage source. The diffused rings are heavily doped areas which serve to prevent spurious field effect channel-type or bipolar leakage current conduction between elements of different devices which otherwise could produce unwanted leakage currents which can trigger latchup.
Designers of prior art circuits further utilized "guard barriers" separating transistors prone to forming parasitic latch devices at the I/O circuitry of CMOS circuits. Internal CMOS circuitry having a parasitic latch device and therefore susceptable to latchup were isolated from propogation of leakage current from the I/O circuitry to the internal circuitry by the placement of the guard barriers to separate the internal circuitry from the
I/O circuitry. The barriers, also known as parasitic collectors, can be a P-type dopant material diffused into an N-substrate or an.N+ type dopant material diffused into a P-type well. P-type barriers are connected to a negative voltage source and N+ type barriers are connected to a positive voltage source.
Guard rings and barriers provide a path to a negative (V55) or positive (VDD) voltage source for injected minority (hole) and majority (electron) carrier current respectively, a P-type barrier connected to Vss would collect current caused by a current source of holes or a dc voltage above VDD, and similarly, an N+ barrier connected to VDD would collect current caused by a current source of electrons or a dc voltage below Vss.
The use of guard rings and barriers requires extra semiconductor chip area to be devoted to latchup protection. The extra chip area is required for the guard rings and barriers themselves and for the separate power supply rails that must be brought to them. The use of guard rings and barriers increases the complexity of the circuit and limits layout flexibility.
The present invention avoids the requirement for separate power supply rails to be brought to the guard barriers, thus saving chip area and simplifying the circuit. Furthermore, the invention makes use of existing masking and process steps, and thus can easily be incorporated into a semiconductor circuit design.
The present invention is implemented by the simple structure of extending the well in which one MOSFET is contained toward the nearest active element of the adjacent opposite channel type MOSFET.
This appears to increase the resistance of the base of one of the parasitic bipolar transistors, decreasing its gain, and then increasing the latchup trigger current. Since only a change in mask dimensions is required, no additional or changed process steps are required.
A preferred embodiment of the invention is a latchup protection apparatus for adjacent MOSFETS of opposite channel types integrated into a single substrate in which one MOSFET is contained in a doped well having polarity type opposite that of the substrate, the well having an extension over a region adjacent the other MOSFET of such length so as to increase its resistance to a degree sufficient to increase latchup trigger current.
Another embodiment is latchup protection apparatus for a pair of adjacent MOSFETS comprising an
N-channel MOSFET contained in a P-well which is contained in an N-doped substrate, a P-channel MOSFET contained in the substrate adjacent the N-channel
MOSFET, the P-well extending asymetrically toward the
N-channel MOSFET.
Still another embodiment is latchup protection apparatus for CMOS integrated circuit containing a parasitic latch device in a doped substrate of one polarity type, the integrated circuit comprised of a first circuit of one channel polarity type, and further comprised of a second circuit of a second channel polarity type in a doped well of the one polarity type within the substrate, the first circuit including a guard ring for collecting leakage current of the one polarity type which may otherwise pass between a P-N junction formed of the well and the substrate separating the first and second circuits, the protection apparatus comprising an extension of the doped well of the second circuit laterally in the direction of the first circuit outside of the guard ring and wherein the lateral resistance of the well near a surface of the substrate is increased by the lateral extension, thereby impeding the leakage current, thereby enhancing the effectiveness of the guard ring for collecting the leakage current.
A better understanding of the present invention will be obtained be reading the description below in conjunction with the following drawings in which:
Figure 1 is schematic diagram of a parasitic latch device formed by a pair of bipolar transistors.
Figure 2 is a cross-section of a CMOS integrated circuit inverter used to illustrate the formation of a parasitic latch device,
Figure 3 is a cross-section of a CMOS integrated circuit inverter illustrating latchup protection means for two transistors according to the present invention,
Turning to Figure 1, transistors Q1 and Q2 which are parasitic bipolar transistors in a CMOS circuit forming a parasitic latch device, are shown with the collector of PNP transistor Q1 connected to the base of NPN transistor Q2, their junction forming a first gate 1 of the device. The collector of transistor 02 is connected to the base of transistor
Q1, their junction forming a second gate 2 of the device.The emitter of transistor Q1 forms an anode 3 of the device and the emitter of transistor Q2 forms a cathode 4 of the device.
When there is a sufficient majority (electron) carrier current present of gate 1 to be injected into the base of transistor Q2 to turn it on, transistor Q2 begins to draw collector current via the base-emitter junction of transistor Q1. As a result Q1 also turns on, injecting additional current into the base of transistor Q2. This in turn causes transistor Q2 to turn on harder, supplying more base current to transistor Q1. Similarly, if there is a sufficient minority (hole) carrier current present at gate 2 to be injected into the base of transistor Q1 to turn it on, transistor Ol begins to draw collector current via the base-emitter junction of transistor
Q2. As a result transistor Q2 also turns on, injecting additional current into the base of transistor Q1.This in turn causes transistor Q1 to turn on harder, supplying more base current to transistor Q2. In both cases, the positive feedback arrangement sustains conduction, even if the gate current is interrupted. The parasitic latch device is thus turned on and is said to be in latchup.
The formation of the above described parasitic latch device will now be described with reference to Figure 2.
Figure 2 is a cross-section of a CMOS integrated circuit inverter. The circuit is comprised of an N-channel MOSFET 7 within a P-type well 8 and a
P-channel MOSFET 9 within an N-type substrate 10. A source 13 of transistor 7 is connected to a voltage ground (negative voltage Vss) and a source 14 of transistor 9 is connected to a positive voltage source
VDD (typically at +5 volts). A gate 15 of transistor 7 is connected to a gate 16 of transistor 9 and forms an input 17 to the inverter. A drain 18 of transistor 7 is connected to a drain 19 of transistor 8 and forms an output 20 to the inverter.
The fabrication of transistors 7 and 9 in close proximity can result in the formation of a parasitic latch device. In such a case, a parasitic
NPN bipolar transistor 25 is vertically oriented with the P-well 8 as the base, and the N-substrate 10 as the collector. Emitters are formed from N+ source 13 and N+ drain 18 diffused regions. A parasitic PNP bipolar transistor 26 is horizontally oriented with the N-substrate 10 as the base, and the P-well 8 as the collector. Emitters are formed from diffused regions P+ source 14 and P+ drain 19. The two transistors are connected together due to the collector of the NPN bipolar transistor 25 being in the commonly diffused N-region 10 as the base of the
PNP bipolar transistor 26-and due to the base of the
NPN bipolar transistor being within the P-doped region 8 with the collector of the PNP bipolar transistor 26.
Latchup can occur between the two MOSFET transistors 7 and 9 if there is sufficient majority (electron) carrier current injected into the base of the NPN bipolar transistor 25. This could take the form of a leakage current propogating through P-N junction 30 separating MOSFET transistors 7 and 9.
Alternatively, latchup can occur between the two transistors if there is a sufficient minority (hole) carrier current injected into the base of the PNP bipolar transistor 2. This could take the form of a leakage current propogating through the P-N junction 30 separating the two transistors. In both cases, latchup can occur by the progation of leakage current between the N-substrate 10 and the P-type well 8 through P-N junction 30.
It has been found that latchup can be protected against by significantly increasing the resistance of the base of parasitic transistor 25 and the collector of parasitic transistor 26. This is obtained by the simple change of one diffusion mask used during fabrication of the CMOS N-channel transistor 7, that of lengthening the P-well 8 at least at a region adjacent CMOS P-channel transistor 9. With the increase in resistance, the trigger current required to cause latchup is significantly increased.
For example, in one successful prototype, in a device in which the source and drain (active areas) of adjacent MOSFETS were 70 microns apart the
P-well was extended in the N-channel transistor toward the N-channel transistor about 20 microns so that the
P-channel active area to the opposite P-well was 40 microns, rather than 66 microns as was the distance in a control device. The trigger current below Vss (electrons) was raised from about 30-40 ma in the control device to about 85-95 ma. The trigger current above VDD (holes) was raised from about 100-130 ma in the control device to about 180- > 200 ma. Clearly this is a dramatic increase in trigger current, given the simplicity of the structure, and the fact that no change in process steps is required.
These results are surprising, since it would be expected that for trigger voltages above
VDD the trigger current would be less with the well extension, because the base width parasitic transistor 26 is made smaller by extending.P-well 30.
It should be noted that the invention is not limited to the extension of the P-well in an
N-substrate of an N-channel MOSFET toward a P-channel device in the same N-substrate. The invention will also work by providing an extension of an N-well in a
P-substrate for a P-channel MOSFET toward an N-channel
MOSFET in the P-substrate.
Figure 3 illustrates a cross-section of another embodiment. The structure is similar to
Figure 2, with similar reference numerals, except that the P-well of transistor 7 is extended at 50 toward transistor 9 sufficient to increase the resistance of the parasitic transistor 25 enough to increase the latchup trigger current to a desired degree. This can be, for example, to a boundary half the distance between the adjacent source and drain of the adjacent transistors. The spacing between the adjacent source and drain should remain the same.
Alternatively, for a given latch-up protection, the distance between the adjacent source and drain can be reduced, so long as the length of the
P-well of the N-channel transistor (or N-well of a
P-channel transistor in an N-well) between the adjacent N and P-channel MOSFET transistors is maintained the same.
It should be noted that the invention is not restricted to CMOS gates and can be used in other devices such as inverters, ring oscillators, etc. In addition, the structure can be used in conjunction with guard rings and guard barriers, and due to the increased base resistance of one of the parasitic transistors, will enhance operation of the guard rings and barriers. The invention can also be used in an epitaxial layer over a substrate, in which case the epitaxial layer is the substrate containing the
MOSFET's and extended well.
A person understanding this invention may now conceive of alternative structures or variations of the described embodiments,using the principles described herein, which are considered to be within the scope of the invention as defined in the claims appended hereto, given a purposive construction.
Claims (6)
1. Latchup protection means for an integrated circuit containing adjacent MOSFETS of opposite channel types integrated into a single substrate in which one MOSFET is contained in a doped well having polarity type opposite that of the substrate, the well having an extension over a region adjacent the other MOSFET of such length so as to increase its resistance to a degree sufficient to increase latchup trigger current.
2. Latchup protection means as defined in claim 1 in which the well is a P-well.
3. Latchup protection means as defined in claim 2 in which a boundary of the P-well adjacent said other MOSFET is approximately 1/3 the distance from an active region of the first MOSFET to an active region of said other MOSFET.
4. Latchup protection means for an integrated circuit containing a pair of adjacent
MOSFETS comprising an N-channel MOSFET contained in a
P-well which is contained in an N-doped substrate, a
P-channel MOSFET contained in the substrate adjacent the N-channel MOSFET, the P-well extending assymetrically toward the N-channel MOSFET.
5. Latchup protection means for a CMOS integrated circuit containing a parasitic latch device in a doped substrate of one polarity type, the integrated circuit comprised of a first MOSFET of one channel polarity type, and a second MOSFET of a second channel polarity type in a doped well of said one polarity type within the substrate, said first MOSFET including a guard ring for collecting leakage current type which may otherwise pass across a P-N junction formed of said well and the substrate separating the first and second circuits, the protection means comprising an extension of the doped well of the second MOSFET laterally in the direction of the first
MOSFET outside of the guard ring and wherein the lateral resistance of the well near a surface of the substrate is increased by said lateral extension, thereby impeding said leakage current, thereby enhancing the effectiveness of the guard ring for collecting said leakage current.
6. Latchup protection means as claimed in claim 1 substantially as described herein with reference to Figs. 1 and 2 or Fig. 3 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA604280 | 1989-06-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9013026D0 GB9013026D0 (en) | 1990-08-01 |
| GB2233496A true GB2233496A (en) | 1991-01-09 |
Family
ID=4140274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9013026A Withdrawn GB2233496A (en) | 1989-06-28 | 1990-06-12 | Preventing latchup in cmos circuits |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH03108757A (en) |
| GB (1) | GB2233496A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0198569A1 (en) * | 1985-02-14 | 1986-10-22 | Siliconix Limited | Monolithic integrated circuits having protection against latch-up |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63244876A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Complementary mis type semiconductor device and manufacture thereof |
-
1990
- 1990-06-12 GB GB9013026A patent/GB2233496A/en not_active Withdrawn
- 1990-06-28 JP JP2168580A patent/JPH03108757A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0198569A1 (en) * | 1985-02-14 | 1986-10-22 | Siliconix Limited | Monolithic integrated circuits having protection against latch-up |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03108757A (en) | 1991-05-08 |
| GB9013026D0 (en) | 1990-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |