GB2232313A

GB2232313A - Logic interface circuit

Info

Publication number: GB2232313A
Application number: GB8912028A
Authority: GB
Inventors: Michael John Gay
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1989-05-25
Filing date: 1989-05-25
Publication date: 1990-12-05
Anticipated expiration: 2009-05-25
Also published as: HK1000301A1; GB8912028D0; GB2232313B

Abstract

A logic interface circuit comprises a differential amplifier 104 with two outputs 126, 128 connected to the two inputs of a logic (NAND) gate 106. The differential amplifier is arranged so that the outputs of the amplifier are at substantially different levels if an input logic signal at terminal 122 is either high or low, but are at substantially the same level when the input signal is at an intermediate level; as a result logic gate 106 produces a high output for both low and high inputs, and a low output for intermediate level inputs. A diode 138 may be connected, with either polarity, allowing the circuit to be used as an inverting or non-inverting interface. <IMAGE>

Description

topic Interface Circuit This invention relates to logic interface circuits for use in circuitry which require logic signals to be coupled from one circuit to another.

It is often necessary to couple logic signals from one circuit to another: for example, in telephone circuits the dialler requires an interface circuit to couple logic signals to the telephone line interface circuit.

However, interfacing problems arise for a particular class of circuits where the logic levels of the two circuits to be coupled are opposite. That is, for one circuit a logic 1 is represented by a voltage pulled to a positive supply line while for another circuit, to which the logic signals are coupled, a logic 1 is represented by a voltage pulled down to a negative supply line.

In addition, interfacing is made complicated for another class of circuits where a first logic level is represented by a voltage near one of the supply lines and a second logic level is represented by the circuit providing a high impedance output (i.e. an open-circuit).

Thus, it is an object of the present invention to provide an improved logic interface circuit which facilitates the intercoupling of logic signals for the above classes of circuits.

In accordance with the present invention there is provided a logic interface circuit comprising: an interface input for receiving a logic signal; an interface output for providing a logic signal; differential amplifier means coupled to said input and having two outputs; and a logic gate having two inputs coupled respectively to the two outputs of said differential amplifier and an output coupled to said interface output, said differential amplifier being arranged to provide first and second output signals at the two inputs of the logic gate, said first and second output signals having substantially different signal levels in response to said logic signal at said interface input being at either a high or a low level or substantially equal signal levels in response to said logic signal at said interface input being at an intermediate level, whereby said logic gate provides a first polarity logic signal or a second polarity logic signal at said interface output.

Thus, it will be appreciated that due to the arrangement of the differential amplifier and the gate the interface circuit is able to provide a first output logic level in response to an input voltage near a supply line and a second output logic level in response to an input voltage at an intermediate level, for example, when the input is connected to a high impedance node. That is, the interface circuit will provide a first output logic level irrespective of the direction of the input current.

In a preferred embodiment a diode is connected in series with the input of the interface circuit: the polarity of connection of the diode will determine the relationship between the logic output and logic input.

Thus, since the polarity of connection of the diode can be easily changed, the interface circuit can provide output signals which match or invert their input.

The invention will be described in terms of bipolar technology to illustrate the principle.

Two logic interface circuits will now be described, by way of example only, with reference to the accompanying drawings in which: Figure -1 shows a circuit diagram of an interface circuit in accordance with a first embodiment of the present invention; Figure 2 shows a circuit diagram of an interface circuit in accordance with a second embodiment of the present invention.

Referring firstly to Figure 1, a logic interface circuit 2 in bipolar technology comprises a differential amplifier 4 coupled to a gate 6. In the preferred embodiment a NAND gate configuration is used.

The differential amplifier 4 comprises first and second pnp transistors, 8 and 10, coupled in parallel having their emitter electrodes coupled together to one terminal of a current source 12 which provides the bias for the differential amplifier 4. A second terminal of the current source 12 is coupled to a positive supply line 16.

The base of the second.transistor 10 is connected to a reference voltage 14 having a voltage level between the positive 16 and negative 18 supply lines. The base of the first transistor 8 is coupled to the reference voltage 14 via a resistor 20, and also to the input terminal 22 of the logic interface circuit 2 via a resistor 24. The collector electrodes of the first and second transistors, 8 and 10, form respectively the first 26 and second 28 outputs of the differential amplifier 4.

The NAND gate 6 comprises two npn transistors 30 and 32 and a current source 34. The current electrodes of the gate transistors 30 and 32 are coupled together in series: the collector electrode of the gate transistor 30 is connected to one terminal of the current source 34 and to the output terminal 36 of the interface circuit and the emitter electrode of the gate transistor 32 is connected to the negative supply line 18. A second terminal of the current source 34 is coupled to the positive supply line 16. The first and second outputs, 26 and 28, of the differential amplifier 4 are respectively coupled to the base electrodes of the gate transistors 30 and 32.

In operation the input terminal 22 is coupled to a driver circuit (not shown). This could be, for example, a dialler circuit in a telephone. The operation of the logic interface circuit will now be described.

When no current signal is provided at the input terminal 22 (that is, when the current signal is at an intermediate level), the differential amplifier 4 is balanced and the current from the current source 12 is divided substantially equally between the first and second transistors 8 and 10. Therefore, substantially the same current is supplied to the bases of the first and second gate transistors 30 and 32 which are driven into saturation. In a saturated state current from the current Referring now also to Figure 2, a second logic interface circuit 103 incorporating the invention is similar to the first logic interface circuit 2 described with reference to Figure 1.However, the second logic interface circuit 103 comprises a logic interface circuit 102, identical to the logic interface circuit 2 of Figure 1, which is integrated onto one Integrated Circuit (IC) and which has one diode 138 externally coupled thereto.

The logic interface circuit 103 according to the second embodiment of the present invention is required to be used when the logic signals to be coupled from one driver circuit (not shown) to another have a logic 1 represented by a voltage pulled to a positive supply line 116 and a logic 0 represented by a voltage pulled down to a negative supply line 118 or vice versa. Such circuits are referred to as having high and low logic levels.

Diode 138 is connected, having either a first polarity of connection or a second polarity of connection, to the input terminal 122 of the logic interface circuit 102. In a preferred embodiment described herein, the diode 138 is shown having the first polarity of connection such that its cathode is coupled to the input terminal 122 of the logic interface circuit 102 and its anode is coupled to a signal input terminal 123.

When the driver circuit (not shown) provides a voltage near the positive supply line 116 to signal input 123 the diode 138 is forward biased and the current will be supplied to the input terminal 122 of the logic interface circuit 102 and will flow through the resistor 124. The subsequent operation of the logic interface circuit 102 of Figure 2 is identical to that of the logic interface circuit 2 of Figure 1: therefore, the output signal from the output terminal 136 will be high.

When the driver circuit provides a voltage near the negative supply line 118 to signal input terminal 123, the diode 138 is reversed biased and no current will flow source 34 will be sunk by the first and second gate transistors so that as a result the output signal from the output terminal 36 will be low.

When the driver circuit (not shown) provides a voltage near the positive supply line 16, the current signal at the input terminal 22 will flow through the resistor 24 pulling the base of the first transistor 8 positive. This creates a voltage differential between the bases of the first and second transistors 8 and 10 so that the current supplied to the second gate transistor 32 is smaller than the current supplied to the first gate transistor 30. When the voltage differential is large enough, the current supplied to the second gate transistor 32 will be so small that the second gate transistor will no longer be able to absorb the current from the current source 34. As a result the output signal from the output terminal 36 will be high.

When the driver circuit (not shown) provides a voltage near the negative supply line 18, the current signal at the input terminal 22 will flow in the opposite direction through the resistor 24 pulling the base of the first transistor 8 negative. In this case the voltage differential between the first and second transistor bases results in a smaller current being supplied to the first gate transistor 30. However, if the voltage differential is large enough the first gate transistor 30 will no longer be able to absorb the current from the current source 34 and the output signal from the output terminal will again be high.

Since the output signal will be high irrespective of the direction of the input current signal i.e. whether the voltage is high or low, the logic interface circuit 2 can be used to interface logic signals between circuits having a first logic level represented by a voltage near either one of the supply lines and a second logic level represented by the circuit providing a high impedance output (i.e. an open-circuit).

through the resistor 124. Therefore, as with the interface circuit 2 of Figure 1, the output signal from the output terminal 136 will be low.

When the diode is connected having the second polarity of connection, such that its anode is coupled to the input terminal 122 of the logic interface circuit 102 and its cathode is coupled to the signal input terminal 123, the diode 138 will be forward biased for an input voltage near the negative supply line and reversed biased for an input voltage near the positive supply line. As a result, the output logic signals will be the inverse of the input logic signals.

Thus, it will be appreciated that since the diode 138 is external to the logic interface circuit 102, either the first (non-inverting) or second (inverting) polarity of connection of diode 138 can be easily selected, according to the logic level requirements of the logic circuits to be interfaced. The polarity of connection may be, for example, selected at the time of manufacture of the logic interface circuit 103.

The preferred embodiments have been described in bipolar technology. However, it will be appreciated that the invention is not limited thereto and that a realisation of the invention in MOS technology will be apparent to a person skilled in the art.

Claims

1. A logic interface circuit comprising: an interface input for receiving a logic signal; an interface output for providing a logic signal; differential amplifier means coupled to said input and having two outputs; and a logic gate having two inputs coupled respectively to the two outputs of said differential amplifier and an output coupled to said interface output, said differential amplifier being arranged to provide first and second output signals at the two inputs of the logic gate, said first and second output signals having substantially different signal levels in response to said logic signal at said interface input being at either a high or a low level or substantially equal signal levels in response to said logic signal at said interface input being at an intermediate level, whereby said logic gate provides a first polarity logic signal or a second polarity logic signal at said interface output.

2. A logic interface circuit according to claim 1 further comprising a diode coupled in series with the interface input.

3. A logic interface circuit according to claim 2 wherein said diode is connected having a first polarity of connection such that for a logic signal at the interface input having a first polarity, the first and second differential amplifier output signals will have substantially the same signal levels whereby said logic gate provides said first polarity logic signal at said interface output, and for a logic signal at the interface input having a second polarity, the first and second differential amplifier output signals will have substantially different signal levels whereby said logic gate provides said second polarity logic signal at said interface output.

4. A logic interface circuit according to claim 2 wherein said diode is connected having a second polarity of connection such that for a logic signal at the interface input having a first polarity, the first and second differential amplifier output signals will have substantially different signal levels whereby said logic gate provides said second polarity logic signal at said interface output, and for a logic signal at the interface input having a second polarity, the first and second differential amplifier output signals will have substantially the same signal levels whereby said logic gate provides said first polarity logic signal at said interface output.

5. A logic interface circuit according to claim 1, 2, 3 or 4 wherein said differential amplifier comprises two transistors coupled in parallel.

6. A logic interface circuit according to claim 5 wherein said two transistors are bipolar transistors.

7. A logic interface circuit according to claim 5 wherein said two transistors are MOSFET transistors.

8. A logic interface circuit according to any preceding claim wherein said logic gate is a NAND gate.

9. A logic interface circuit substantially as hereinbefore described with reference to the accompanying drawings.