GB2231422A - Computer upgrading - Google Patents

Abstract

A personal computer using an 80386 microprocessor chip on its main board is upgraded by a "turbo" board with an i486 chip and suitable interfacing circuitry. The interfacing circuitry connects the clock signal directly from the main board to the i486, and includes means 42 for dividing the clock by 2 to generate a half frequency clock. The main board thereby effectively runs on the divided-down clock from an 80386, while the i486 runs at twice the speed of the 80386 which it replaces. Some of the remaining signals passing between the main board and the i486 are buffered and a few are modified by the interfacing circuitry, but buffering and retiming requirements are minimized by the use of the main board clock to drive the turbo board. The turbo board can be constructed with the 80386 header and the i486 socket in substantially matching positions on opposite sides of the board, with the interfacing circuitry largely contained within the area of the header and socket. The same technique can be used to upgrade an 80286-based system with an i486. A computer using an i486 can be designed substantially as an 80386 computer with the i486 coupled to the rest of the system by means of the above interfacing circuitry. <IMAGE>

Description

Gornpute# UpSr#a#inS The present invention relates to computers of the type commonly known as personal computers and similar such computers, and is concerned more specifically with the upgrading of existing computers.

The standard design of personal computer consists generally of a monitor, a keyboard, a printer, and a processor unit. There can of course be other units as well, and variations are of course possible - for example, a single printer may be shared between several computers (which may then be referred to as workstations).

The present invention is concerned with the processor unit, which is normally housed in a rectangular box (which often has disc drives built into it as well). More specifically, the processor normally consists of a main board, carrying the microprocessor and a substantial amount of additional circuitry which is virtually indispensible for the essential functions of the computer, and having on it an expansion bus with several connectors into which additional circuit boards (expansion boards) can be plugged. These expansion boards generally provide functions which are not essential but are desired by the particular user, e.g. additional disc drives, an improved video drive to the monitor, modems, etc.

An outstanding feature of personal computer technology is continuing technical advance. This has shown itself in many aspects, but the aspect of most importance here is the development of new microprocessor chips. The type of personal computer being considered here uses a single microprocessor chip for central control of the computer.

The microprocessor chip used in many early personal computers was the 8088, which is an 8-bit chip running at 5 MHz and generally using 4 clock cycles per operation. The next chip to be introduced was the 8086, which is a 16-bit chip; it initially ran at 5 MHz, but was later developed to run at 8 MHz. Next came the 80286 chip, which is also a 16-bit chip running at 6 MHz (then developed to 8 MHz); however, this chip generally uses 2 clock cycles per operation. The main chip at present is the 80386, which is a 32-bit chip; the original version runs at 16 MHz but 20, 25, and 33 MHz versions have been developed. There are also, of course, many 80286-based computers still in use.

There are therefore currently four main classes of personal computer, depending on which chip is used. As each new chip was introduced, so a new class of microcomputer was introduced with it, providing a substantial advance in computing power over the previous class. But within the more recent classes, there have been increases# in computing power due to the increased speed of the corresponding types of chip.

Very recently the i486 chip has been introduced. This can run at up to 33 MHz, the same speed as the latest version of the 80386, and is a 32-bit chip, also as the 80386. However, an i486-based computer normally operates considerably faster than the 80386, for various reasons. The most significant of these is that in the 80386, substantially all operations tate 2 clock cycles (or more than 2); the 80386 chip contains an internal - divide-by-2 clock flip-flop, and its internal timing is governed primarily by that flip-flop. In the i486, most operations take only 1 clock cycle. In addition, the i486 contains an 8k cache memory. It can confidently be predicted that a large number of personal computer designs based on the i486 will become available in the near future.

The cost of personal computers, while small compared to large computer systems (mainframes and minis), is nevertheless substantial in comparison with, for example, calculators - the difference is a couple of orders of magnitude.

Further, personal computers are generally designed to be expandable by the addition of expansion boards. A substantial activity has therefore developed in providing upgrades to existing personal computers. (In some cases, this is done to maintain the "image" of the owner rather than from any pressing need for technical improvement.) Such upgrading is achieved by substituting a newer type of microprocessor for the existing one. This generally involves replacing an 8086 chip by an 80286 chip, or an 80286 chip by an 80386 chip. This technique is commonly termed "turbo-charging"; the replacement chip is mounted with some associated circuitry on a board termed a turbo board.

The computing power of a computer designed to use a given chip will, of course, in general be greater than that of a computer designed for the previous type of chip which has been upgraded by the addition of a turbo board. However, the upgrade will generally provide a good deal of the increased power of the new computer, at a cost of a modest fraction of the cost of the existing computer (while the cost of the new computer is likely to be substantially higher than that of the existing computer).

According to its main aspect, the invention provides a turbo board for replacing the microproces,sor chip on the main board of a personal computer and carrying a microprocessor chip (the turbo chip) which is broadly compatible with the microprocessor chip in the personal computer but is of a more advanced type, together with interfacing circuitry, wherein the interfacing circuitry comprises means for substantially directly connecting the clock, the data bus, and the address bus between the main board and the turbo chip, means for dividing the clock by 2 to generate a half frequency clock, and means for buffering at least some of the status signals between the main board and the turbo chip under control of the half frequency clock.

Thus in the present system, the clock available on the main board 10 is also used to drive the i486 chip on the turbo board 20, at twice the speed of the 80386 chip which the turbo board replaces. As a result, the quantity of interfacing circuitry required is much less than for previous turbo boards (e.g.

for upgrading an 80286-based system with an 80386 chip).

If the turbo chip includes a cache memory, the interfacing circuitry prefer ably includes circuitry which detects when a main memory write is performed by a device on the main board other than the turbo board and thereupon flushes the cache memory in the turbo chip, and it preferably also includes circuitry which makes certain predetermined memory areas uncacheable by the turbo chip. The board may also carry data buffers for performing any required conversion between bus formats of different widths.

Preferably, the turbo board comprises a board having a header for the main board chip and a socket for the turbo chip constructed in broadly matching positions on opposite sides of the board, with the necessary interfacing circuitry preferably being mounted on the board at least largely in the interior areas of one or both of the header and socket.

This construction is possible because the interfacing circuitry can be accommodated in the interior areas of the i486 socket and the 80386 header on the turbo board 30, and this in turn is possible because the quantity of circuitry required is relatively small.

In a modification, the turbo board consists of two sub-boards, one carrying the main board chip header and the other carrying the turbo chip socket. The connections between the two sub-boards may be formed by mating pins and socket elements, which may be extensions of the socket elements and/or pins of the turbo chip socket and the main board chip header, or they may be located around the periphery of the i486 socket, preferably along three sides thereof, and preferably intercalated with the socket elements thereof. Optionally, at least the data bus is coupled between the two sub-boards by bridging them by the chips for the data buffers.

It will also be realized that a computer using the turbo chip can readily be designed by taking a computer designed to use a chip which is broadly compatible with the turbo chip but is of a less advanced type, and replacing, on the main board, the less advanced type of chip by the interfacing circuitry described above as being located on the turbo board.According to this aspect, the main board of a personal computer or the like designed largely to operate with a less advanced chip carries, in place of that chip, a turbo chip and "interfacing" circuitry comprising means for substantially directly connecting the clock, the data bus, and the address bus between the main board and the turbo chip, means for dividing the clock by 2 to generate a half frequency clock which is returned to the main board, and means for buffering at least some of the status signals between the main board and the turbo chip under control of the half frequency clock. Further logical/electrical features of the main aspect of the invention may also obviously be applied to this aspect.

Preferably the chip on the main board is an 80286 or 80386 and the turbo chip is an i486.

A turbo board in accordance with the present invention, and various modifications thereof, will now be described, by way of example, with reference to the drawings, in which: Fig. 1 shows diagrammatically a typical board layout of an 80386-based processor; Fig. 2 shows diagrammatically a typical turbo board for the processor of Fig. 1; Fig. 3 is a section through a turbo board in accordance with the present invention; Fig. 3A is an enlarged view of one corner of the turbo board of Fig. 3; Figs. 4A and 4B together are a block diagram of the circuitry of the turbo board of Fig. 3; Fig. 5 is a block diagram of the circuitry of an expansion and development of the turbo board of Fig. 3; Figs. 6A to 6C shows alternative board arrangements; and Fig. 7 shows an offset adaptor.

Before describing the turbo boards of the present system, it is desirable to consider in more detail the nature of turbo boards in general, and for this it is desirable to consider more closely the structure and organization of a personal computer processor. It will be convenient to consider primarily processors using 80286 and 80386 chips, because these are one of the main areas in which turbo boards have been used; for present purposes, processors using these two types of chip are broadly similar.

Fig. 1 shows a typical main board layout of an 80286-based processor. The board 10 is divided roughly into quarters. An 80286 microprocessor chip 11 is mounted towards the centre of the board. Beside this, in the bottom left-hand quarter, there are several connectors 12 into which memory boards are plugged.

This provides the primary memory, which is connected to the microprocessor 11 by a memory bus (not shown). (Part or all of the memory may be mounted directly on the board, rather than coupled to it via connectors as described.) The - bottom right-hand quarter of the board has various logic units 13 mounted on it, providing a variety of functions such as a real time clock, possible battery back-up for that, timers, mouse control, DMA (direct memory access) control, and system logic. Above this, in the top right-hand quarter of the board, there is a set of expansion connectors, connected to the expansion bus (not shown). In the top left-hand quarter of the board, there is more logic 15, concerned primar ily with interfacing between the microprocessor 11 and the expansion bus and with driving that bus.

The original design of the expansion bus was for processors using the 8088 chip, which is an 8-bit chip. The boards to be plugged into the expansion bus were therefore all originally designed as 8-bit boards, and many current boards are derivatives of these early designs So the logic 15 also carries out any necessary data conversion from 32 bits to 16 bits or 8 bits. There has in fact been a fairly general adoption of a 16-bit expansion bus, but such a bus often has some short connectors on it for use with 8-bit address expansion boards.

As noted above, there have been frequent advances in microprocessor speed.

The expansion bus is physically large and can have various expansion boards of a variety of types plugged into it. The speed at which thfg; bus is operated is therefore generally 8 MHz (which is the same as that used in the faster 8086based processors); serious problems would be encountered in trying to run that bus significantly faster. zoo286 chips, however, run faster than this, and one major function of the logic 13 is to provide the timing conversion between the chip and the expansion bus.

The memory 12 is coupled to the chip 11 by a separate memory bus, and is located physically close to the chip 11. This is to enable memory accesses to be as fast as possible, with the memory bus being run at the speed of the microprocessor. (In practice, it usually takes 3 clock cycles for a memory access.) To turbocharge a processor, the existing microprocessor chip is replaced by a later and larger type of chip, as noted above - say, an 80386 processor.

However, one cannot simply pull the existing chip out of its mounting and plug in the new one, for several reasons. For one thing, the different types of chip have different mountings. But, more important than that, appropriate interfacing has to be provided so that the new chip, which has a larger word length and probably runs at a higher speed, can still drive the existing board. The turbo board therefore carries not only the new chip but also the additional interfacing circuitry.

As with other expansion boards, the turbo board is fitted into one of the expansion slots 14 on the expansion bus. It draws its power supplies from that bus, and can interface directly with the logic signals on that bus. It also, of course, has to interface with the socket of the original microprocessor chip 11, and this is achieved by means of a flying lead from the turbo board, with a connector on its end which plugs into the existing microprocessor chip socket.

It is desirable to minimize the length of the connections to the new chip.

The turbo board normally extends across substantially the full width of the board 10, and the microprocessor chip is therefore normally mounted towards its left-hand end. However, the length of the connections is obviously 'still increased considerably, and the existing chip is being replaced by one which runs substantially faster. The access time from the chip to the memory on the main board 10 (either directly mounted on the board or plugged into the connectors 12, as the case may be) would limit the speed of operation to well below the chip speed. A replacement memory is therefore also mounted on the turbo board, together with circuitry between the chip and the flyin#g lead plug which intercepts memory access attempts and prevents them from reaching the original memory on the board 10, directing them instead to the new memory mounted on the turbo board.That original memory thus becomes inoperative, at any rate for its original purpose. (It may be possible to arrange for it to be used as an additional or extended memory, somewhat as if it were plugged into the expansion bus.) An additional advantage of this arrangement is that the memory on the turbo board can be of a size matching the new microprocessor on that board, i.e.

larger than the original memory on the main board 10.

The organization of such a turbo board is therefore generally as shown in Fig. 2. The board 20 is shown tilted backwards into the flat position; tilting it forwards into the vertical position orients it so that its edge connector 21 can be plugged into one of the expansion sockets 14 of the main board 10 (Fig.

1). The microprocessor chip 22 is mounted towards the centre of the board.

On the right-hand side, there is the primary memory 23 for the chip 22. On the left-hand side, there is interfacing circuitry 24 and the flying lead 25 which plugs into the socket on the main board 10 when the original chip 11 is removed.

Logically, the chip 22 is coupled to the memory 23 on one side and to the interfacing circuitry 24 on the other.

Thus the length of the connections from the microprocessor socket on the main board to the turbo board and the increased speed of the microprocessor on the turbo board have dictated the provision of a memory on the turbo board which effectively replaces the existing memory on the main board.

The interfacing circuitry 24 includes a clock chip to drive the microprocessor 22 at the appropriate speed, together with signal conversion and buffering circuitry. The signals coming from the main board 10 are those appropriate to drive an 80286 processor, and these must be converted to a form appropriate to drive the 80386 processor 22 on the turbo board 20. Similarly, the signals coming from the 80386 processor 22 must be converted to a form which simulates those coming from an 80286 processor when they are passed from the turbo board 20 to the main board 10. In addition to these conversions, the signals must also be buffered, because the clock signals on the main board 10 are independent of those on the turbo board 20.Hence the signals coming from the main board 10 to the turbo board 20 must be retimed to match the turbo board clock before they can be fed to the 80386 microprocessor 22, and those coming from the microprocessor to the main board 10 must similarly be retimed to match the main board clock before they can be received prroperly by the main board.

Turbocharging of the general character described has been widely available for upgrading 8088/8086 processors with 80286 and 80386 chips, and 80286-based processors with 80386 chips. Upgrading of 8088 processors to 8086 processors has not been common, because there is little speed advantage in changing an 8088 chip for an 8086 chip and the doubled word width is of little advantage in a processor designed for the original word width.

The present invention is concerned primarily with the design of a turbo board to replace an 80286 or 80386 chip by an i486 chip (although the principles are also applicable to turbo charging processors using other types of chip, such as Motorola chips), and provides a different approach to the design of a turbo board for such a purpose. The present invention has two major aspects, physical and logical. The physical aspect concerns the physical structure, location, and mounting of the board; the logical aspect concerns the interfacing arrangements.

As will be seen, the logical or electrical aspect of the present system is considerably simpler than for standard turbo boards, and this in turn allows the physical structure and arrangenent of the present board to be con 1dersbly simpler than for standard turbo boards.

Considering first the physical aspect, the present turbo board is designed as a combined 80286 or 80386 header and i486 socket, at substantially the same location on opposite sides of the board, with the interfacing circuitry mounted on the board in the interior region of the sockets.

Fig. 3 shows a section through a turbo board 30 which upgrades an 80386 system with an i486 processor. The board 30 is a multi-layer board, with i486 socket elements 31 projecting on one side and 80386 plug elements 32 projecting on the other side, and with the IC chips 33 of the interfacing circuitry mounted on the board 30. The board 30 also has two flying leads attached to it. one to an expansion bus connector 34 and the other to a pin connector 35. The purpose of these two leads is explained below.

An 80386 chip has its pins arranged around the outer 3 lines of a 14 x 14 square array of points with a point-to-point spacing of 2.5,4 mm. An i486 chip has its pins arranged around the outer 3 lines of a 17 x 17 square array of points with the same point-to-point spacing of 2.54. mm. There are therefore square areas unoccupied in the middle of both the i486 socket and the 80386 header, of about 30 mm2 and 22 mm2 respectively. The area inside the 1486 socket is utilized for the chips of the interfacing circuitry; if necessary, the area inside the 80386 header can be utilized as well.

The 80385 header is placed symmetrically inside the i486 socket such that each pin of the outer line of the 80386 header lies symmetrically between 4 socket points of the two inner lines of the i486 socket, and each socket element of the inner line of the i486 socket lies symmetrically between 4 pins of the two outer lines of the zoo386 header. Fig. 3A shows one corner of the board 30, with the i486 socket elements shown as solid circles and the 80386 header pins shown as open circles. The spacing between the pins of the 80386 header allows connection tracks to pass between them to the socket elements of the i486 socket, and vice versa.

This construction allows the turbo board 30 to be plugged directly into the 80386 socket once the existing zoo386 processor has been removed. Since the turbo board is only slightly thicker than and larger in area than the 80386 processor. there will be very few if any existing computers which it cannot be fitted to. This direct plugging into the existing 80386 socket, combined with the small physical size of the turbo board, means that the signal path lengths will be small and will cause very little loss of speed.

Turning now to the logical aspect, we have realized that the quantity of interfacing circuitry required is much less than for previous turbo boards (e.g.

for upgrading an 80286-based system with an 80386 chip). It is because of this that the interfacing circuitry can be accommodated in the interior areas of the i486 socket and the 80386 header on the turbo board 30. This reduction of the quantity of circuitry required arises because, in the present system, the clock available on the main board 10 is also used to drive the i486 chip on the turbo board 20, at twice the speed of the zoo386 chip which the turbo board replaces.

To explain the interfacing circuitry, it is desirable to consider the signal inputs and outputs of 80386 and i486 chips. To a large extent, the signal inputs and outputs of these two chips match each other. ; For example, both chips are 32-bit chips, and both have a 32-bit data bus A0-31. Both also have a 32-bit address bus, BE0-3 and A2-31. (The addressing scheme is partially byte oriented, with the bits A2-31 addressing 32-bit words and 4 byte enable signals BE0-3 which can select any desired ones of the 4 bytes within the selected word.) The interfacing between the main board 10, which is compatible with an 80386 chip, and the i486 chip on the turbo board therefore has to cope essentially only with the different timing requirements of the two chips.

Fig. 4 is a block diagram of the interfacing circuitry - i.e., a circuit diagram of the turbo board 30. Where appropriate, main board signals are distinguished by an initial "B". The signals pass between the 80386 header 40 and the i486 socket 41.

The main board clock signal BCLK2 is fed direct to the i486 as its clock signal CLK. In this way the i486 will run at twice the clock frequency of the 80386 since the 80385 in effect treats the clock signal BCLK2 as a 2-phase clock which is divided down internally to half frequency.

The signals passing from the i486 to the 80386 header have to be synchronized to this internal 80386 half-frequency clock. Since that internal clock is - not available from the 80486, it has to be generated externally. This is done by e divide-by-2 flip-flop 42, which generates a half-frequency. clock signal BCLK. The phase of this ciock is determined by a reset signal BRESET, which is fed by the system board to flip-flop 42, to reset it. The reset signal BRESET is also passed through the present board to become the reset signal RESET for the i486.

The 80385 receives a hold signal BHOLD, which causes it to stop once it has finished its current operation. This signal BHOLD is valid prior to the rising edge of BCLK2 when BOLK is high. The corresponding signal for the i486 is HOLD, and the i486 samples this on every BCLK rising edge. Hence HOLD must be generated to match BHOLD only when BHOLD is valid. This is achieved by feeding BHOLD to an AND gate 45 which is enabled by BCLK. Gate 45 feeds an OR gate 46 which feeds an AND gate 47 which is enabled by BCLK and feeds OR gate 46. Thus gates 46 and 47 form a latching circuit such that HOLD follows BHOLD when BCLK is high and retains that state when BCLK is low.The output of gate 46 is fed to the i486 as signal HOLD. (The gates 45 to 47 must be such that the state of the signal HOLD cannot be lost on the BCLK falling edge. as gate 45 is disabled and gate 47 enabled; a similar requirement exists for other gate combinations discussed below.) The reset signal BRESET is also fed to the latching circuit of gates 45 to 47, to ensure that the hold signal HOLD to the i486 is correct on reset. The reset signal is similarly fed to the latching circuits for other signals, such as the BHLDA and /BADS signals discussed below. (The "/" indicates that a signal is active low.) The 80386 generates a hold acknowledge signal BHLDA, which goes active when it has received a hold signal and acted on it; this signal is only allowed to change when BCLK is low.The i486 generates a. similar hold acknowledge signal HLDA, and signal BHLDA must be synthesized from HLDA. This is done by means of gates 50 to 52, such that BHLDA follows HLDA when BCLK is low and retain their state during periods when BCLK is high. An inverter 53 inverts the signal BHLDA to produce a signal /BHLDA for use in the generating other signals as discussed below.

The 80386 also generates an address valid signal /BADS, and this must be synthesized from the corresponding signal /ADS from the 1486. The i486 makes /ADS available for only one CLK period, while /BADS has to be active for one BCLK period starting with BOLK low. A latching loop consisting of gates 55 to 59 is set during a BCLK low period and holds its state during the following BCLK high period, so holding its output signal for the required BCLK period. /ADS is fed to gate 55, so the latching circuit operates provided that /ADS appears while BCLK is low. However, /ADS may also appear while BCLK is high. /ADS is fed to a flip-flop 60. which is clocked by BCLK. so that its output /CADS is its input delayed by one BCLK cycle.Flip-flop 60 feeds gate 56, so that if /ADS appears while BCLK is high, its delayed version /CADS appears from flip-flop 60 when BCLK goes low, and so ensures that the gate combination 55 to 59 still produces the signal /BADS as required.

The signal from gate 58 is fed to a tristate gate 59 to produce the signal /BADS. Gate 59 is enabled if the hold acknowledge signal BHLDA is low (/BHLDA high), so floating the /BADS output. (This allows another device on the main board to drive /BADS, as for example in a DMA (direct memory access) system.

The i486 will ensure that BHLDA does not appear during a cycle initiated by /BADS going active.) The 80386 chip has a "generate next address". input NA. The 80386 is sometimes able to generate the next address before the end of the current opera tion: When signal NA is active, it causes the 80386 to do this; if it is not active, the 80386 does not produce the next address until the end of the current operation. The i486 does not have an NA input. If the board 10 generates an NA signal, that is simply ignored, i.e. not passed on to the i486 on the turbo board.

Because of the need to provide compatibility with previous systems, including 8086-based systems, which were 16-bit systems, computers generally need to be able to accommodate areas of memory which are organized on the basis of 16bit words. In some systems, a "bus size 16" signal /BS16 is generated and fed to the zoo386 chip to indicate whether a memory access uses 16-bit or 32-bit words. In the 80386, when /BS16 is active, on a processor read operation data is read only from the bottom half of the data bus, and on a processor write operation the data on the bottom half of the data bus is duplicated onto the top half of that bus. In the i486, this signal merely informs the chip of whether 2 cycles will be needed to complete a 32-bit access; the chip does not read only the lower half of the data bus, nor does it duplicate data on the lower half onto the upper half.

In many systems, however, the /BS16 signal is not used, and that input to the 80386 is tied high. In such systems, any swapping of 16-bit words between the upper and lower halves of the data bus is performed by other logic on the main board 10.

The turbo board 30 shown in Figs. 3 and 4 is designed for use in a system of the latter kind, i.e. in which the signal /BB16 (base board signal bus size 16) is tied high. The i486 has a /BS16 input, which is connected to /BB16 and so forces the i486 to operate permanently in the 32-bit mode.

Although the i486 has a /BS16 input, it does not operate in the same way as the 80386 in response to an active signal at that input. In fact, it interprets that signal only as an indication that two cycles will be required to complete a 32-bit access; unlike the 80386, it does not read the data on only the bottom half of the data bus or duplicate the bottom half of the bus onto the top half for the second cycle. If the system uses the /BS16 signal, therefore, the appropriate manipulation of the data on the data bus must be performed by the interfacing circuitry on the turbo board 30 itself. Additional circuitry (not shown) must be provided for this.This additional circuitry is preferably mounted on the board 30, but can be provided on a separate adaptor board mounted between the turbo board 30 and-the 80386 socket on the main board 10.

The 80386 receives. a ready signal /BRDY. and the corresponding signal /RDY to the i486 must be generated. /BRDY is passed through an OR gate 65 to produce the signal /RDY. Gate 65 is fed with the inverse of CLK, forcing /RDY high - (/RDY is active low) during the first half of the 80386 cycle, as /BRDY is only valid at the end of an 80386 cycle. Gate 65 is also fed with the /BADS signal from gate 59 and /CADS from flip-flop 60, to prevent /RDY from going active when either of those signals is active. This is because the i486 samples /RDY on all CLK2 rising edges after /ADS has gone inactive, wehereas the 80386 would only sample /BRDY when BCLK was high after /BADS went inactive.

There are various further status-type signals which are mainly generated by the i486 and required by the main board. These can generally be passed directly from the i486 to the main board. However, certain types of system require these signals to change only when the clock BCLK is low. The read/write signal W/R' and the data/control signal D/C are therefore preferably passed from the i486 to latching and tristate circuits 61 and 62 as shown to generate the cor responding main board signals BW/R and BD/C. Each of these latching circuits comprises a set of three gates like gates 50 to 52 plus a tristate circuit like circuit 59.

Another signal which has to be passed from the i486 to the main board is the memory or input-output signal. However, there is a slight difference between the M/IO signal produced by the i486 and the BM/IO signal which would be produced by an 80386. ,M/IO has to be inverted to produce BM/IO when W/R is high and D/C is low. M/IO is therefore passed through an XOR circuit 67, controlled by a gate 66 which detects the just-stated combination of signals W/R and D/C, and a latching circuit 68 (like circuits 61 and 62) controlled by /BHLDA and BCLK, to generate BM/IO.

An 80386 microprocessor is designed to perform a range of logical and simple arithmetical operations, but complicated mathematical operations have to be programmed as a sequence of operations which can be performed by the 80386.

Coprocessor chips have therefore been designed, which work in conjunction with the 80386 and are specially adapted to perform complicated mathematical operations. The i486 incorporates coprocessor circuitry, so that no coprocessor is likely to be required to work with it, and it Ls not designed to work with a coprocessor. If the board 10 contains a coprocessor, then that coprocessor may be removed. The i486 produces a signal /FERR, which has to be fed to the interrupt control logic on the board 10. This signal goes low on an error condition and should be connected to the logic to which the original coprocessor was connected. This is achieved by means of the flying lead 35.

As so far described, the main memory 12 on the main board 10 remains fully operational; the only difference resulting from the turbo board, as far as the memory is concerned, is that accesses pass through the turbo board to the i486 instead of going directly to the 80386.

The i486, however, contains a cache memory, and a considerable amount of buffering allowing posted writes. (When a cache memory is used, its contents must be kept consistent with the contents of the main memory. Hence when a word is written into the cache memory, the word must be written into the corresponding address in the main memory as well. A posted write is when a word which has been written into the cache memory is put into a queue for writing into the main memory, and the i486 continues with subsequent operations before that word has actually been written into the main memory.) The use of a cache memory, however, involves certain complications, since the main memory can have its contents used and changed not merely by the microprocessor but also by other units on the main board 10.

The simplest method of dealing with these complications is to disable the cache memory in the i486 entirely. This can be done by tying the /CACH (/KEN) input to the i486 high (this input allows cache operation when low).

In the present turbo board 30, however, circuitry is provided for permitting the use of the cache memory in the i486 but controlling its use so as to overcome the complications just mentioned. This involves two techniques: controlling which addresses are cacheable, and cache flushing when a =cacheable address in the main memory is changed from some source other than the i485.

It is undesirable to allow any cacheing of certain areas of memory, because these areas are liable to frequent change by sources other than the i486. One of these areas is the memory range from 0 to 64 k; the reason ior this is that in many systems, this area can be mapped to the 64 k area just above address 1 M and adjusted by writing to either address. Another of these areas is the address range from 640 k to 1 M; the reason for this is that this area includes the video memory, which is frequently subject to change by sources other than the i486 A decoder 70 is fed from the address bus, and is preprogrammed to detect when the address on the address bus is in one of these uncacheable areas. It feeds the /CACH input of the i486 to prevent such addresses from being cached, Apart from these areas which are made uncacheable, writes into other areas of the main memory may occur from sources other than the i486. If this occurs, then the cache contents must be updated or, in this case, deleted (flushed).

This is achieved by a circuit 71. which feeds the /FLUSH input. This circuit includes a decoder 72 which monitors the status lines between the 80386 header and the i486 socket and detects when a write into the main memory is occurring from a device other that the i486.

For the address bus, most of the lines are connected directly between the 80386 header 40 (as lines BA2-BA31) and the i486 socket 41 (as lines A2 to A31).

However, there is a complication. The bottom 2 bits of the address are produced in decoded form as byte enable signals BEO to BE3 (the ZB" here indicates "byte'1; the base-bourd versions of the signals are distinguished by a second "B".) These signals are incorrect in the first of the four 32-bit accesses required for filling a 128-bit cache word. Most systems automatically provide the full 32 bits of data, but some require the byte enable signals BEO to BE3 to be forced low.

Unfortunately there is no single signal which indicates when the current access is the first one (of a sequence of four 32-bit accesses). However, there is a signal /BLAST (again, the "B" indicated "byte", not a baseboard signal) which is low during the last access of the four. This signal is combined with the ready signal /RDY in a gate 110, the output of which is lqtched in a flip-flop 111 clocked by CLK to produce a signal /FIRST. This is combined with a variety of other status signals by a gate 112, the output of which controls a set of four gates 113 which are fed with the byte enable signals BEO to BE3 from the i486 and produce the byte enable signals BBEO to BBE3 for the baseboard.

If desired, the address signals can be passed through tristate circuits controlled by /BHLDA, like the status signals discussed above.

The present turbo board is mounted in the socket of the existing microprocessor chip 11, to minimize lead lengths. Most of the signals required by the circuit 71 are those which are available on the leads to that socket. However, it is desirable for the circuit 71 to be able to determine when a direct memory access (DMA) involving a main memory write is being performed. The occurrence of this situation cannot be deduced from the states of the signals on the leads to the microprocessor 11 socket alone. The present board therefore also has a flying lead and connector 34 which can be plugged into one of the sockets 14 on the expansion bus, so that it can sense signals on that bus.The signal /BMWR on that bus is combined with the hold signal BHLDA by a gate 73, and the flush control signal /FLUSH to the i486 is produced by a gate 74 which combines the outputs of the decoder 72 and the gate 73.

In certain circumstances, the timing of certain devices on the main board 10 requires the microprocessor operation to be kept below certain limits. The present turbo board may result in the system exceeding those limits. The decoder 72 is also arranged to detect when such devices are operating. and to cause continuous cache flushing in response thereto. This results in slowing down the operation of the system, since every operation will involve a cache access to determine whether or not the required address is in the cache, followed by the accessing of the address from the main memory.

The turbo board 30 obviously requires more power than the 80386 chip, because the board 30 includes the interfacing circuitry 33 and carries the larger and more powerful i486 chip. But the power available from the socket for the 80386 chip will normally be sufficient to drive the board 30. The power requirement of the board 30 is substantially less than that of a normal turbo board, because of the small amount of interfacing circuitry on the present turbo board. However, the flying lead and connector 34 can include power lines to power the board 30 from the expansion bus if desired.

The flying leads 34 and 35 can be omitted if the original board is constructed so that the signals which would be carried the flying leads can instead be passed through spare pins on the microprocessor chip socket. (This would normally require the board to be designed to permit this type of upgrade.) The interfacing logic has been largely shows as discrete components, but it can of course largely be provided by means of logic arrays (programmable or otherwise).

The data signals can be passed directly between the base board and the 1486. However, additional circuitry which may be provided on the board to provide greater functionality than that resulting from effectively ignoring the bus size signal in the manner described above, and this involves buffering the data signals.

In the Fig. 5 system, the data bus BDO-31 on the base board is coupled to the data bus B0-31 on the i486 via three tristate bidirectional buffers 80-82.

Buffers 80 and 82 couple the low-order half of the bus (bits 0-15) and the highorder half of the bus (bits 16-31) respectively, while buffer 81 cross-couples the low-order and high-order halves of the bus. 'A write/read signal W/R, which is one of the status signals. is generated by the it86. This signal is low for reading by the i486 and high for writing from it, and is fed to the direction control input DIR of all three buffers to control the direction of passage of data through them. Each buffer also has an enable control input E, and is enabled when the input to the enable control is low.

For reading. buffer 80 is always enabled. This is achieved by feeding signal W/R to an AND gate 83 which feeds the E control of buffer 80; W/R is low for reading, so gate 83 produces a 0 output which enables buffer 80. If the bus size is 32 bits, EBB16 is 1, and buffer 82 must also be enabled. This is achieved by feeding /BBl6 and W/R to a NOR gate 84, which thus produces a low output which enables buffer 82. Buffer 81 must be disabled for bus size 32.

This is achieved by feeding the outputs of gates 83 and 84 to a NOR gate 85 which controls buffer 81; the low output from gate 83 causes gate 85 to effectively invert the output of gate 84,. so that the enable signals to buffers 81 and 82 are complementary.

For writing, buffer 82 is always enabled (if the write is actually a 16-bit write, data will still be passed through buffer 82 but will be ignored when it reaches the memory). This is achieved by feeding the signal W/R to gate 84, as W/R is high for writing and the output of gate 84 is therefore low, enabling buffer 82. Buffer 80 must be enabled if either of the two low-order bytes is valid. This is achieved by feeding the two low-order byte signals /BEO and /BE1 to gate 83; these two signals are two of the address signal on the address bus.

If either is 0, indicating that the corresponding byte is valid, gate 83 produces a 0, enabling buffer 80. If neither of the two lower-order bytes is valid, then the bytes on the upper half of the data bus must be copied onto the lower half; for this, buffer 81 must be enabled instead of buffer 80. Since, for a write, the output of gate 84 is low, this low signal causes gate 85 to effectively invert the output of gate 83, so that the enable signals to buffers 80. and 81 are complementary.

With this system, the bus size signal /BB15 on the main board is fed directly through as the bus size signal /BS16 to the i486.

The Fig. 5 circuit involves a considerable quantity of buffering, and the additional circuitry required for this may require several extra chips. It may therefore be necessary to change the structure and layout of the board.

One way of doing this is to enlarge the board and locate some of the chips outside the inner areas of the microprocessor chip header and socket. If this is done, it may also be convenient to locate the socket 31 and the header 32 at different locations on the board.

If this is done, then there may be a problem in fitting the turbo board onto the main board, since there may be devices mounted on the main board adjacent to the 80386 socket which would be fouled by the turbo board. To alleviate this problem, an offset adaptor may be used. Fig. 7 shows a suitable arrangement for the adaptor.

The adaptor 90 has an 80386 header 91 on its lower surface which fits into the 80386 socket on the main board, and has an 80386 socket 92 on its upper surface, offset from the header, into which the turbo board can be plugged. It is preferred for the header and socket to be diagonally offset from each other by a distance somewhat less than the diagonal diameter of the header and socket.

This means that the header and socket will partially overlap; the header pins and the socket elements of the socket each form a square band, and these two bands will overlap in two regions. The header pins and socket elements are intercalated in these two regions in the same way as is shown in Fig. 3A for the pins of the 80386 header and the socket elements of the i486 socket. Since the header and socket on the offset adaptor are identical, each pin is connected to the socket element in the corresponding position; so all connecting tracks on the board are essentially parallel to the direction of offset The header 91 and socket 92 are provided with pins in all positions. so that the adaptor can be fitted in any of its 4 possible orientations.The turbo board itself can thus be displaced in 4 possible directions, minimizing the chances that it cannot be fitted to a main board.

If it is desired to keep the size of the turbo board to approximately the size of the i486 socket, then the board can be constructed of two sub-boards one above the other, the lower sub-board carrying the 80386 header and the upper one carrying the i486 socket. The space available for mounting the chips is then the interior of the 80386 header on both sides of the lower sub-board and the interior of the i486 socket on both sides of the upper sub-board.

As shown in Fig. 6A, the connections between the two sub-boards 95 and 96 can then be formed by pins 97 mounted on say the upper side of the lower subboard and socket elements 98 mounted on the lower side of the upper sub-board.

These connecting 97 pins may be intercalated among and outside the elements of the i486 socket 31 on the upper sub-board in the same way as shown in Fig. 3A.

In this case, the connecting pins are preferably arranged along three sides of that socket. There are 17 pins along each edge of the i486 socket. so two rows of connecting pins along three sides of the outer part of the i486 socket provide roughly 100 Cs x 17) pins. The number of signal connections required between the two sub-boards is about 80, so these 100-odd pins provide the required number of signal connections plus about 20 connections for power and ground. (The i486 chip has some 168 pins; most of those in excess of these 100 connections are not required in the present system, or do not yet have functions designated.) This layout leaves the fourth side of the upper sub board free beneath of i486 socket, so that a cooling element can be inserted from that side between the two sub-boards if desired, to reach the chips mounted on the facing sides of the two sub-boards.

In an alternative arrangement shown in Fig. 6B, connections between the two sub-boards 100 and 101 may be made by pin-and-socket connectors 102-103, but with the pins 102 of these connections being continuations of socket elements of the i486 socket 31, carried through the upper sub-board 100. In addition to this way of providing connections between the two sub-boards, it is possible to mount some of the chips 104 around the periphery of the two sub-boards so as to bridge them. It is convenient to use the data buffer chips for this, as those chips form a natural interface between the 80386 header and the i486 socket.

If desired, dummy chips may be used to provide further interconnections. It would be possible to provide all interconnections between the two sub-boards 100 and 101 in this way, but it is preferred to use some pin-and-socket interconnections as well, so that the two sub-boards 100 and 101 can be held together with the appropriate spacing for the chips 104 to be attached to them.

The above principles and techniques can also be used to provide a turbo board which upgrades an 80286-based computer to use an i486 chip. This is because an 80286 microprocessor operates in a very similar manner to an 80386 microprocessor.

However, certain modifications and changes to the details of the circuitry described above are obviously necessary.

The status signals M/IO, D/C, and W/R from the i486 have to be converted to the status signals BCOD/INTA, BM/I0, S1, and SO which an 80286 produces. This can conveniently be done by means of a PLA (programmed logic array). The conversion table is as follows: M/IO D/C W/R . BCOD/INTA BM/IO /S1 /SO O 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0 1 1 0 The signals /ADS and /CADS are ORed together and fed to the gate array so that the outputs /S1 and /SO will only go high when /ADS and/or /CADS are high.

The 80286 has a pair of status lines SO and S1 which together correspond to the ADS signal used by an 80386. In the 80286, these signals appear one clock after the addresses appear: SO goes low for a write, S1 for a read, and both for an interrupt acknowledge. Two signals BSO and BS1 thus need to be generated, for feeding to the baseboard, more or less corresponding together to the signals BADS and BW/R for an 80386. To produce these signals, the two signals SO and S1 are produced as just described and fed to a pair of flipoflops which are clocked by the signal /BCLK (i.e. the falling edge of BCLK), and the outputs of these two flip-flops are passed through tristate circuits controlled by /BHLDA. The signal /BADS is not available; instead, the two signals IBSO and /BS1 have to be effectively ANDed for feeding to gate 65 to disable /RDY. It is however unnecessary to feed the reset signal to the divide-by-2 clock flip-flop 42.

Further, the 80286 is a 16-bit chip. In the data buffering shown in Fig.

5, the buffer 82 is therefore not required; also, the 'BS16 signal to the i486 is permanently tied to 0.

Structurally, the turbo board for an 80286-based system is preferably constructed largely as shown in Figs. 6A and 6B. However, if the turbo board is intended for use with an 80286-based system using a PLCC 80286 chip, the 80286 plug on the board can be formed by a PLCC chip 104 soldered to the board in an inverted position, as shown in Fig. 6C. The chip 104 can be used to provide some or all of the interfacing circuitry.

Claims (15)

C l a i m E3

1 A turbo board for replacing the microprocessor chip on the main board of a personal computer and carrying a microprocessor chip (the turbo chip) which is broadly compatible with the microprocessor chip in the personal computer but is of a more advanced type, together with interfacing circuitry, wherein the interfacing circuitry comprises means for substantially directly connecting the clock, the data bus, and the -address bus between the main board and the turbo chip, means for dividing the clock by 2 to generate a half frequency clock, and means for buffering at least some of the status signals between the main board and the turbo chip under control of the half frequency clock.

2 A turbo board according to claim 1 wherein the turbo Vhip includes a cache memory and the interfacing circuitry includes circuitry which detects when a main memory write is performed by a device on the main board other than the turbo board and thereupon flushes the cache memory in the turbo chip.

3 A turbo board according to claim 2 wherein the interfacing circuitry further includes circuitry which makes certain predetermined memory areas uncacheable by the turbo chip.

4 A turbo board according to any previous claim wherein the board also carries data buffers for performing any required conversion between bus formats of different widths.

5 A turbo board according to any previous claim wherein the turbo board comprises a board having a header for the main board chip and a socket for the turbo chip constructed in broadly matching positions on opposite sides of the board.

6 A turbo board according to claim 5 wherein the interfacing circuitry is mounted on the board at least largely in the interior areas of one or both of the header and socket.

7 A turbo board according. to either of claims 5 and 6 wherein the board consists of two sub-boards, one carrying the main board chip header and the other carrying the turbo chip socket.

8 A turbo board according to claim 7 wherein the connections between the two sub-boards are formed by mating pins and socket elements,

9 A turbo board according to claim 8 wherein the connections are extensions of the socket elements and/or pins of the turbo chip socket and the main board chip header.

10 A turbo board according to either of claims 8 and 9 wherein the connections are located around the periphery of the turbo chip socket.

11 A turbo board according to claim 10 wherein the cognections are located along three sides of the turbo chip socket.

12 A turbo board according to any one of claims 7 to 11 when dependent directly or indirectly on claim 4, wherein at least the data bus is coupled between the two sub-boards by bridging them by the chips for the data buffers.

13 A turbo board according to any previous claim wherein the microprocessor socket on the main board is a PLCC type, and the turbo board carries, attached to it in an inverted position, a chip acting as the plug to the main board socket and including at least part of the interfacing circuitry.

13 A turbo board according to any previous claim wherein the chip on the main board is an 80286 or 80386 and the turbo chip is an i486.

14 A turbo board substantially as herein described with reference to Figs. 4 to 7.

15 A computer using the turbo chip comprising a computer designed substantially to use a chip broadly compatible with the turbo chip but of a less advanced type, and including, on the main board, interfacing circuitry as defined in any one of claims 1 to 4 connected between the turbo chip and the remainder of the main board.