GB2231186A - Normaliser circuit - Google Patents

Abstract

A normaliser removes an unwanted amplitude-modulation and is capable inter alia of handling higher-frequency modulations than analogue dividers previously used. An input detector feeds both a long time-constant integrator 2 and a short time-constant integrator 3 whose outputs are subtracted in a circuit 4. the output of which is inverted in a circuit 5 and fed to a network of interconnected multipliers 6/1, 6/2 etc which generate successive powers of the negative signal from circuit 5. These powers are added in parallel at 8 to the output of integrator 2 and the sum fed to a multiplier 9 where it is multiplied with the normaliser input. The unwanted modulation is thereby substantially removed from the multiplier output, although circuits for removing any residuum are also described. Wanted modulations are preserved either by connecting a filter 30 to precede the network and allow only the unwanted modulation to pass, or by feeding to the network. Instead of the output of subtractor 4, the output of a detector 31 which receives a separate sample of the input signal lacking the wanted modulation. <IMAGE>

Description

Normaliser circuits This invention relates to normaliser circuits, in particular to normaliser circuits in which an AC signal is divided by a control amplitude to give, as quotient, an AC signal whose amplitude is related, as a multiple or fraction, to the control amplitude. Such a normaliser circuit is described in our copending GB Appln No 8712556 (Publn No 2,191,321A) in which the control voltage is termed a reference amplitude; normaliser circuits which can additionally filter out selected amplitudemodulating frequencies of the AC carrier signal while normalising others are described in our copending GB Appln No 8828173.

The normaliser circuits described in these two Applications have two main disadvantages as follows: (i) They are limited in the amplitude-modulating frequencies they can handle because of the limited frequencyresponse (up to 10 or 20 kHz) of commercially available analogue dividers, although higher frequencies can be obtained by substituting digital dividers. Sometimes a response up to 10 KH; would be desirable, which may not be obtainable even with digital dividers.

(ii) They reduce the amplitude of the normalised output signal, and of any wanted modulation sidebands not subjected to the normalising process, to a level equal to or determined by the modulation depth of any unwanted modulation which is subjected to the normalising process. It can be shown that this is an inevitable consequence of using a conventional square-law balanced mixer as the multiplier which yields the final output.

These disadvantages are of particular concern when the wanted modulation is very much smaller than the unwanted modulation.

The present invention provides forms of normaliser circuit which alleviate these two disadvantages.

The present invention is based upon the same general principle as the aforesaid two Applications, in which the normaliser multiplier (via the divider in those two cases) is fed with signals whose amplitude depends on the control voltage amplitude and which are derived in one of the following situations: (i) from the detected amplitude-modulation on the normaliser input; (ii) as for (i) but only from selected parts of the frequency spectrum of said modulation; (iii) from the detected amplitude-modulation on a separate sample of the normaliser RF input, but where this sample does not contain some wanted modulation which is present on the above normalised input; (iv) as for (iii) but where the sample contains some wanted modulation although in a ratio to the unwanted modulation which is different from that present on the above normaliser input.

According to the present invention a normaliser circuit comprises: a linear amplitude-detector having an input connection for a modulated carrier signal of the form A(l+a)cos Qt, where A = A(l+c) and A, a and c are as hereinafter defined; a long time-constant integrator and a short time-constant integrator each connected to receive the detector output and to produce outputs corresponding to A and A(l+a) respectively; circuit means for subtracting said integrator outputs and producing an output corresponding to -Aa; a network for producing powers of said output (-Aa)n ascending by unity from n = 1 to n C:: 2, said ascending powers being fed in parallel to an adder together with the output A from said long time-constant integrator; and a multiplier connected to multiply together the modulated carrier input and the adder output whereof the product is the normaliser circuit output with the modulation a substantially removed.

A filter may be connected between said subtracting means and said network to exclude a modulation b as hereinafter defined.

A present normaliser circuit usable when a separate sample of the input signal, of the form A(l+a)cos Qt but lacking a modulation b as hereinafter defined is available, may comprise a second linear amplitude-detector having an input connection for said separate sample and means for feeding a modulation -a derived from said second linear detector to said network in place of the output from said subtraction circuit in substantially the same phase as the modulation a in the first-mentioned input signal and at an amplitude substantially to cancel the modulation a therein.

A circuit as defined aforesaid may further include means for pre-processing the first-mentioned input signal to reduce the amplitude of the modulation a therein. Said means may comprise means for deriving a version of said input signal in which the carrier is phase-reversed and for combining said version with said input signal to effect subtraction therefrom.

Alternatively said pre-processing means may comprise means for extracting the carrier from said input signal or from a separate sample thereof lacking modulations b or c; a modulator connected to receive the extracted carrier; means, including a linear amplitude-detector connected to receive the input signal or the separate sample, and arranged to modulate the extracted carrier in said modulator with the modulation a in antiphase with the modulation a in the input signal; and means for combining the modulator output with the input signal in a sense to reduce the modulation a therein. Said preprocessing means may be arranged to deliver the extracted carrier to said modulator in antiphase and to modulate said carrier therein with the modulation a in phase with the modulation a in the input signal.When no separate sample is available said modulator and said means including said linear detector may be omitted, and the circuit arranged to combine said extracted carrier with the input signal in a sense to increase its carrier content relative to its modulation a content.

A circuit as aforesaid may include means for reducing residual modulation a in the output from said multiplier, said means comprising: a further stage of said network arranged to produce the next n highest power of said output (-Aa) means for extracting the carrier and a second multiplier arranged to multiply together said extracted carrier and said next highest power; and means for combining the outputs of said two multipliers in a sense to reduce said modulation a.

Alternatively said means for reducing residual modulation a in the output from said multiplier may comprise means for combining a portion of the input signal to the normaliser with the output of said first-mentioned multiplier at such phase and amplitude as effects said reduction.

The present invention will now be described, by way of example, with reference to the accompanying drawings wherein: Fig 1 is a block schematic circuit diagram of a normaliser circuit embodying the invention; Figs 2, 3 and 4 are such diagrams of circuits preceding the normaliser circuit per se for modifying the input thereto to give improved performance; Figs 5 and 6 are such diagrams of circuits following the normaliser circuit per se for modifying the output therefrom to give improved performance.

In Fig 1 the input signal to be normalised is shown as A(l+a)cos Ot, where A = A(l+c). In this description: A = amplitude of unmodulated input signal of angular RF frequency Q, a = time-variant modulation index of unwanted modulation (eg an interfering signal), b = time-variant modulation index of wanted modulation which is added to the unwanted modulation a but, unlike c, does not modulate a, c = time-variant modulation index of wanted modulation which is imposed on the input signal as a whole, including any unwanted modulation a thereon.

The main objective in Fig 1 is to eliminate as far as possible the (l+a) component of the input signal in the situations set out in (i) to (iv) above.

First consider situation (i), where b and c are zero. In this situation the above input signal becomes A(l+a)cos Qt which is applied to a linear amplitude-detector 1, from which outputs are taken via an integrator 2 having a relatively long timeconstant and an integrator 3 having a relatively short timeconstant to a subtraction circuit 4. (In the present Application the term "amplitude-detector" denotes a circuit which, in most practice, includes sufficient filtering to remove the RF components and preferably any noise above the modulation band of interest. However, on occasion such filtering may incidentally be provided by a subsequent integrator circuit fulfilling another function). The inputs to circuit 4 from these integrators are A and A(l+a) respectively, and its output is Aa.The timeconstant of integrator 3 is made sufficiently short to pass the highest unwanted frequency involved in a.

In this situation points X and Y are joined directly and the output of circuit 4 is phase-inverted in circuit 5 to produce -Aa, and this component is applied to multipliers 6/1, 6/2, 6/3 ... connected as shown to generate the terms k(Aa), k2(-Aa)3, k3(Aa)4 ... where k is a characteristic of the multiplier, ie output = k(input) 2 These terms are fed to an adder 8 via amplifier/attenuators 7/3, 7/4, 7/5 ..., to which are also fed the terms -Aa and A via respective amplifier/ attenuators 7/1, 7/2. These elements have respective gain/ attenuation factors of gO, gl, g2, g3, g4 ... as shown.

The output of the adder 8 is thus: 2 2 3 n-1 ...+(-1) gnk where n is the number of terms of the series fed to the adder 8.

Signal (1) is multiplied by the input signal A(l+a) cos Qt in a multiplier 9 to give:

If go' go, g2 = - ~ g3 = go s ...,andA is kept kA k A relatively constant by preceding AVC action on the inputs to detector 1 and multiplier 9 or by pre-processing them with two simpler normaliser circuits capable of handling only relatively low-frequency modulation, eg as described in the aforesaid Appln No 8712556, then the output from multiplier 9 becomes: Ago[ 1+(-1)n(a)n+1] l+(-l)n(a)n+l ] cos Qt ... (3) Equation (3) represents an amplitude-modulated signal having an unwanted modulation index, (-l)nan 1, which can be very small if n is made large, since a is less than unity.For large values of a, approaching unity, n would have to be very large in order to reduce the modulation index substantially.

In Fig 1 there is no direct equivalent of the control voltage V fed as numerator to the divider circuits in the two Applications referred to in the present introduction. However, the effect of a control voltage can be obtained by varying the gain gO (and subsequently gl, g2, g3 etc.),ie gO in equation (3) controls the final amplitude as does V in those two Applications.

Alternatively, a preferred way of controlling the final amplitude is to insert an amplifier or attenuator 30 (as required) between adder 8 and multiplier 9, or after multiplier 9 (not shown).

Now consider the case where a wanted modulation b is present, ie modulation within a defined frequency band as in situation (ii) above, or which, as in situation (iii) is present in the normaliser input signal but absent in a separate sample of the input signal. Modulation c is assumed absent in this case.

The basic arrangement for achieving the aforesaid main objective, viz elimination of the (lEa) component, involves either connecting an appropriate filter 30 between points X and Y in Fig 1 in situation (ii), or by leaving X and Y unconnected and feeding a detected version of the separate sample into point Y in situation (iii). This detected version is obtained by applying the separate sample to a linear amplitude-detector 31 followed by a band-pass filter 32 whose pass-band is that of the unwanted modulation, ie that having index a, followed by an amplifier/ attenuator 34 which is adjusted to obtain optimum cancellation of the unwanted signal.Since the phase of the unwanted modulation added at Y should be as close as possible to that of the input signal to detector 1, a variable delay circuit may be required at 33, or at the input to detector 1, in order to match the timing of the two signals. If the output of detector 1 is of the appropriate phase, inverter 5 can be omitted. In the alternative arrangement, filter 30 can be either a band-pass filter for modulation a or a band-stop filter for modulation b.

The filter can either follow or precede inverter 5.

The arrangements described in the immediately preceding paragraph are similar to those described in the aforesaid Appln No 8828173 and the theory is similar. However, it requires to be restated because of the replacement of the simple divider therein by the arrangements of Fig 1.

Let the input signal to detector 1 in this case be A (l+a+b) cos at ... (4) and let the input to point Y be devoid of modulation b components, either by the inclusion of filter 30 or by the application of a signal to detector 31 in which modulation b is absent, as described above. Then the normaliser output from multiplier 9 can be expressed as: A(l+a+b) g0A-g1(Aa)+g2k(Aa) l(Aa)n ] cos Qt = A2g0 [ i+(-i)nan+i Ab-[goA-g1)+g2k(Aa2 etc cos at ... (5) The first factor in equation (5) is the same as in equation (3) whereas the second factor contains the b-based signal.

By substitution of g1, g2 etc as following equation (2), equation (5) can be written as ... +(-1) a ] cos Qt which can be shown to approximate to

As in equation (3), if n is sufficiently large this becomes approximately 2 A l+a cos Qt ... (6) ie the wanted b modulation contaminated by (i+a). This contamination can be removed by arrangements corresponding to those described in Appln No 8828173 comprising circuits 20, 21 and 22 therein, to give an ultimate output of bgo cos Qt. If, however, the wanted modulation is of the form c instead of b, it can be shown that there is no contamination whether c is absent at point Y by virtue of a filter 30 or via application of a separate sample lacking c to detector 31.

Now consider situation (iv). In this case, for a b-based modulation, c absent, the input signal to detector 1 can be expressed as A(i+a+b+rb) cos Qt and that of the separate sample as A(l+a+b) cos Qt, where r + 0. These can be rewritten as A(l+a+b) cos Qt and A(i+a) cos at respectively, where a = a+b and b = rb.

Thus this situation becomes equvalent to situation (iii), equation (6), viz A2br l+a cos Qt ... (7) and can provide an ultimate output of br cos #t.

Where the modulation is c-based the input signal to detector 1 can be expressed as A(l+c)(l+a) cos #t and the separate sample as A(l+pc)(l+a) cos Qt, where p # 1. These can be re-expressed as AL+a+(i+a)pc - (I+a)pc+c(l+a) ] cos #t = A(l+d+e) cos #t ... (8) and AF+a+(i+a)pc ] cos #t = A(l+d) cos #t respectively, where l+d = l+a+(l+a)pc = (l+pc)(l+a) and e = -(l+a)pc+c(l+a) = pc(l+a)(l-p) From the similarity of equations (4) and (8), equation (7) can be used to express the normaliser output as 2 2 cos cos nt... (9) l+d cos #t = ~~~~~~~~~~~~ If pc is small, output (9) is proportioned to c.

In all the foregoing it is essential that the modulation indices a, b or c are reasonably small. In practice it is the unwanted modulation index a which can tend to high values, ie approaching unity or even exceeding unity. Its value can be reduced by pre-processing the signal A(l+a) cos Qt before it is fed to the normaliser. This not only reduced the residual modulation expressed by equation (3), but also reduces the normalising losses at large modulation depths referred to at (ii) in the introduction.

One form of pre-processing circuit is shown in Fig 2. The signal A(l+a) cos at is additionally fed via an amplitude-control circuit 10 (amplifier or attenuator) and a phase-control circuit 11 to a subtraction circuit 12 which receives the input signal A(l+a) cos Qt to be normalised. The circuit 11 is adjusted so that the carrier components, cos Qt, are in antiphase in circuit 12 to effect the subtraction. The output from circuit 12 is fed to the multiplier 9 in Fig 1. This known form of cancellation ideally can eliminate the unwanted input signal component completely, but in practice it is expensive and complex to achieve more than about lOdB cancellation.However, even a lOdB reduction of the unwanted modulation enables the normaliser of Fig 1 to handle the resultant input signal more easily, in particular without the large insertion loss referred to at (ii).

Another way of effectively reducing the modulation depth of the unwanted component a, with or without the availability of a separate sample A(l+a) cos Qt not containing the wanted modulation, is to increase the amplitude of the carrier component, using eg the kind of techniques described in our copending GB Appln No 8705428, (Publn No GB 2,187,907A). In the latter the carrier is extracted and added to the original modulated signal to produce this effect. In this way even an overmodulated signal (a > 1) can be reduced to one which the normaliser can handle. Furthermore, if the above separate sample is available, the extracted carrier can be remodulated with a phase-reversed version of the detected modulation of this sample to produce a composite waveform which is thereby further reduced in its modulation content.

Two principal ways of extracting the carrier are: (i) using a phase-lock loop oscillator as described with reference to Fig 4 of GB Appln No 8705428.

(ii) hard-limiting ("squaring") of the modulated carrier followed by restoration of the carrier to sinusoidal form via a tuned circuit.

A pre-processing circuit of this kind is shown in Fig 3.

Here the input signal to the normaliser or from the separate sample A(l+a) cos Qt is fed to a carrier-extraction circuit 13, eg of the phase-lock loop type shown in Fig 4 of our copending GB Appln No 8705428. The separate sample is fed to a linear amplitude-detector 14 which extracts the modulation a. The modulation is phase-inverted in an inverter 15 whose output is applied to a modulator 16 (neglecting the interrupted-line connection) to remodulate the extracted carrier from circuit 13.

The remodulated carrier is fed via an amplitude controller (amplifier or attenuator) 17 and carrier-frequency phase-controller 18 to an adder 19 which receives the inptt signal. Since the two carriers are in phase but their modulations a are in antiphase, the latter are effectively subtracted in the adder 19 and the unwanted modulation depth thereby reduced before the input signal is fed to the multiplier 9.

Fig 4 shows a modification of Fig 3 in which the extracted carrier is phase-inverted in an inverter 20 instead of the detected modulation, the remainder of the circuit being similar to Fig 3. The effect is now similar to Fig 2, but both Fig 4 and Fig 3 have the advantage that the output level and the modulation spectrum fed to multiplier 9 can be more carefully controlled than in Fig 2. However, in Fig 2 the use of an AVC arrangement or a low-frequency normaliser, eg as described in the aforesaid Appln 8712556, connected between subtraction circuit 12 and multiplier 9 (not shown) will provide a fine amplitude control and make the circuit less dependent on the setting of circuit 10, which need only be a coarse control.

It will be understood that the position of the phasecontrollers 11, 18 and 181 is not critical, eg they can be connected either before or after the amplitude-controllers 10 17, 171.

In modifications of Figs 3 and 4, the imputs to the detectors 14, 141 can be the input signal to the normaliser itself, ie A(1+a) cos Qt, provided the unwanted modulation a cam be isolated from wanted modulation b eg by inserting a filter (not shown) in the output of the detectors 14, 141 to stop the wanted frequency but pass the unwanted frequency a, eg if frequency a frequency c.

If, in Fig 3, the separate sample is not available, the elements 14, 15 and 16 are omitted and the extracted carrier fed direct to the amplitude controller 17 (as shown by the interrupted line), the unwanted modulation depth can be effectively reduced by the resulting increase in the carrier content of the output from adder 19.

The carrier extraction technique can also be used to cancel the the residual modulation term (-l)nan a in equation (3). A circuit having this function is shown in Fig 5. In the example of Fig 1, the terms shown generated end at gO(Aa)4, ie n = 4.

(In other embodiments n may be < 4 or > 4; in one embodiment constructed, n = 2, ie elements 6/1 and 7/3 were the last of the series, which is the minimum usable arrangement.) A further multiplier 6/4 and amplifier/attenuator 7/6 (not shown) are added 5 to generate the next term g (-Aa) which is led to a multiplier 20 (Fig 5). The latter also receives the extracted carrier from a circuit 21 via amplitude and phase controls 22 and 23 similar to elements 13, 17 and 18 in Fig 3. The multiplier output is fed, via carrier-frequency phase-inverter 24 if necessary, to a hybrid 25 where it is subtracted from the output of multiplier 9.

Whether or not element 24 is required depends on the phase of the extracted carrier after fine adjustment in element 23; it must be in antiphase with the output of multiplier 9 to effect subtraction. (A phase-inverter corresponding to element 24 may also be required in Figs 3 and 4 in series with the fine phase-controllers 18 and 181, depending on the phase of the extracted carrier.) In the arrangement of Fig 5 it may be convenient to use equation (5), ie the output from multiplier 9, as the input to the carrier extractor 21, provided the wanted modulation component in A does not adversely affect its operation.

Another arrangement for cancelling the residual modulation is shown in Fig 6, corresponding roughly to "hum-bucking" in audio amplifiers. The signal to be normalised is now fed to the detector 1 of Fig 1 via a hybrid 26, whose other output is fed, if necessary via a carrier-frequency phase-inverter 27 (cf element 24 in Fig 5) and an attenuator 28 (which may be included in hybrid 26) to a hybrid 29 in which it is subtracted from the output of multiplier 9. This arrangement and that of Fig 5 allow ultra-fine adjustment of the cancellation of the unwanted modulation a, in comparison with the arrangements of Figs 2, 3 and 4 which give relatively coarse cancellation; the Fig 1 arrangement per se gives a fine degree of cancellation between these extremes.

Following equation (2), it will be seen that if, additionally, Ak can be made equal to unity, then gO e gl - g2 = g3 etc, ie all the elements 7/1, 7/2, 7/3, etc have the same gain and can be replaced by a single amplifier/attenuator (not shown) connected either before or after detector 1.

Claims (11)

Claims

1. A normaliser circuit comprising: A linear amplitude-detector having an input connection for a modulated carrier signal of the form (l+a) cos Qt, where A = A(l+c) and A, a and c are as herein

defined; a long time-constant integrator and a short time-constant integrator each connected to receive the detector output and to produce outputs corresponding to A and A(l+a) respectively; circuit means for subtracting said integrator outputs and producing an output corresponding to -Aa;; a network for producing powers of said output (-Aa)n ascending by unity from n = 1 to n I 2, said ascending powers being fed in parallel to an adder together with the output A from said long time-constant integrator, and a multiplier connected to multiply together the modulated carrier input and the adder output whereof the product is the normaliser circuit output with the modulation a substantially removed.

2. A circuit as claimed in claim 1 wherein a filter is connected between said subtracting means and said network to exclude a modulation b as hereinbefore defined.

3. A circuit as claimed in claim 1 usable when a separate sample of the input signal, of the form A(l+a) cos at but lacking a modulation b as hereinbefore defined is available, comprising a second linear amplitude-detector having an input connection for said separate sample and means for feeding a modulation -a derived from said second linear detector to said network in place of the output from said subtraction circuit in substantially the same phase as the modulation a in the first-mentioned input signal and at an amplitude substantially to cancel the modulation a therein.

4. A circuit as claimed in claim 1 or claim 2 including means for pre-processing the first-mentioned input signal to reduce the amplitude of the modulation a therein.

5. A circuit as claimed in claim 4 comprising means for deriving a version of said input signal in which the carrier is phase-reversed and for combining said version with said input signal to effect subtraction therefrom.

6. A circuit as claimed in claim 4 comprising: means for extracting the carrier from said input signal or from a separate sample thereof lacking modulations b or c; a modulator connected to receive the extracted carrier; means, including a linear amplitude-detector connected to receive the input signal or the separate sample, and arranged to modulate the extracted carrier in said modulator with the modulation a in antiphase with the modulation a in the input signal; and means for combining the modulator output with the input signal in a sense to reduce the modulation a therein.

7. A circuit as claimed in claim 6 arranged to deliver the extracted carrier to said modulator in antiphase and to modulate said carrier therein with the modulation a in phase with the modulation a in the input signal.

8. A circuit as claimed in claim 6 usable when no said separate sample is available wherein said modulator and said means including said linear detector are omitted and arranged to combine said extracted carrier with the input signal in a sense to increase its carrier content relative to its modulation a content.

9. A circuit as claimed in any preceding claim for reducing residual modulation a in the output from said multiplier comprising: a further stage of said network arranged to produce the next highest power of said output (-Aa)n means for extracting the carrier and a second multiplier arranged to multiply together said extracted carrier and said next highest power; and means for combining the outputs of said two multipliers in a sense to reduce said modulation a.

10. A circuit as claimed in any of claims 1 - 8 for reducing residual modulation a in the output from said multiplier comprising means for combining a portion of the input signal to the normaliser with the output of said first-mentioned multiplier at such phase and amplitude as to effect said reduction.

11. A normaliser circuit substantially as hereinbefore described with reference to the accompanying drawings.