GB2222924A - Message broadcasting - Google Patents

Abstract

Message broadcasting apparatus comprises a generator to generate an automatically repeating analogue message and a transmitter 30 to broadcast the repeating message for reception in the vicinity of the broadcast apparatus. The message generator comprises digital storage means 11-15 for storing the message as a series of digital words. The digital words are successively read from the storage means and converted to analogue form at 28 to reconstitute the message. The system is reset at the end of each stored message to start again at the beginning. The digital message is recorded by analogue to digital converting and storing in RAM in real time and then transferring groups of digital words simultaneously in parallel to ROM at a slower transfer rate. The receiver may be a conventional receiver including a timer circuit for cutting off power to at least parts of the receiver after a predetermined period. The receiver antenna may be in the form of a flexible strap for carrying the receiver. <IMAGE>

Description

MESSAGE BROADCASTING The present invention is concerned with message broadcasting, in particular repeatedly broadcasting prerecorded messages. Installations for this purpose are known for use for example as automatic tour guides and tourist information transmitters. Commonly, short range transmitters may be used for broadcasting the repeating message so that the message can be picked up by specially adapted portable receivers. The transmission medium may be purely inductive or may be low power radio transmission.

Hitherto, such installations have normally stored the message to be repeatedly broadcast on an endless tape loop contained in the transmitting apparatus. The disadvantage of tape based systems however is that they do not have suitable long term reliability. The tape itself may wear or become damaged through continuous use and the mechanical tape transport mechanism is also prone to breakdown when used continuously or over extended periods of time. Furthermore, mechanical tape transport arrangements produce a significantly increased power drain which can be a problem if the broadcast apparatus is to be battery powered, e.g. when installed at a remote location.

In one aspect, the present invention provides message broadcast apparatus comprising a generator to generate an automatically repeating analogue message and a transmitter to broadcast the repeating message for reception in the vicinity of the broadcast apparatus, wherein said message generator comprises digital storage means for storing the message as a series of digital words represent successive values of the analogue message sampled at a sampling rate, reading means to read successive said digital words in said series from the storage means at the sampling rate, a digitial to analogue converter to reconstitute said analogue message from the successively read digital words, and reset means to reset the reading means on reaching the end of the stored message to start reading again at the beginning of said series of digital words to repeat the message.With such an arrangement employing digital storage means, the short comings of the previously used magnetic tape loops can be avoided.

Solid state digital memory may be employed to store the message with no problems of wear or mechanical breakdown during playback. By providing the reset means continuously repeating replay can be ensured.

Conveniently, said reading means includes an address generator to generate address codes uniquely addressing bytes of the digital storage means containing the successive digital words of the series for reading, and said reset means then comprises a comparator to compare the generated address codes with a preset code representing the address of a byte at the end of the stored message and to produce a reset signal on reaching said end of message address to reset the address generator to the beginning of the message.

In another possible arrangement, a digital word which is recognisably different from those employed-to represent said successive values of the analogue message may be stored in the storage means at the end of the message, and said reset means may then be arranged to recognise this different stored word and react thereto by resetting to the start of the message. For example, the word comprising all l's in binary code may be the recognisably different code word recorded at the end of the message.

However, when the aforementioned comparator is employed, this may be arranged to compare only the most significant bits of the address codes with the preset code. For example, if the address generator can address up to 64 x 32,768 (64 x 32K) bytes the comparator may be arranged to compare only the six most significant bits of the address codes with a six bit preset code.

Conveniently said comparator may include manually settable switch means for setting up said preset code.

In another aspect the invention provides a method of digitally recording an analogue signal of predetermined duration in Read Only Memory (ROM) comprising sampling the analogue signal at a sampling rate which is at least twice the maximum frequency to be recorded in the analogue signal, digitising the samples to produce digital words representing the sampled values of the analogue signal, writing the digital words successively at the sampling rate in successively addressed bytes of a Random Access Memory (RAM) until the full duration of the analogue signal is digitally recorded in the RAM, and then reading the stored words from the RAM in successive parallel sets from simultaneously addressed bytes and at a repetition rate for the successive sets which is less than said sampling rate, and writing the successive parallel sets of words at said repetition rate into corresponding bytes of the ROM. This procedure enables relatively high frequency analogue signals to be recorded in RAM. If for example speech is to be recorded, the sampling rate should be at least 5kHz or more preferably 6kHz so that an upper frequency band limit of about 3kHz can be appropriately sampled. Thus, speech sampled at 6kHz can be loaded in real time into RAM with a write cycle time of about 166pus. However the typical minimum load cycle time for electronically programmable ROM is about 3OmS. Thus the maximum repetition rate for loading a parallel set of data into ROM is typically 33Hz. If a five minute message recorded in real time in RAM was then transferred byte by byte into ROM the total loading time into ROM would be about fifteen hours.By loading the data in parallel sets of bytes at the repetition rate, the ROM loading time can be significantly reduced.

In a further aspect, the invention provides a portable radio broadcast message receiver comprising a radio receiving and demodulating circuit to produce an audio signal representing a received message, an audio amplifying circuit to amplify the audio signal to drive an audio transducer, and power supply means for supplying electrical power to said circuits from a battery or cell, and further including an electronic timer powered from said battery or cell, inhibit means responsive to the timer timing out to inhibit continued operation of the receiver and reset means arranged for co-operation with a separate initiating means to reset the timer to initiate operation of the receiver for a period determined by the timer. With this arrangement, the receiver will operate once reset only for the predeterined period until the timer times out.Resetting of the timer can be achieved with the separate initiating means. In this way, the receiver may for example be rented out to a user and arranged to provide a maximum period of use of say two days as determined by the timer. On supplying the receiver to a new user, the supplier can reset the timer using the separate initiating means which is then retained by the supplier.

In one arrangement, the inhibit means comprises an electrically operable switch in the power supply means cutting off power to at least said receiving and demodulating circuit. By cutting off power only to the receiving and demodulating circuit, the current rating of the electrically operable switch can be kept to a minimum. It will be understood that the receiving and demodulating circuit of the receiver may require rather less current from the battery or cell than the audio amplifying circuit.

The reset means may comprise an electrical contact point accessible from outside the receiver, whereby reset is effected by applying a predetermined signal to said contact point. In a simple embodiment this predetermined signal may be a voltage comparable to the supply voltage from the battery or cell contained in the receiver.

In yet a further aspect of the invention there is provided a portable radio broadcast message receiver incorporating an antenna in the form of a flexible strap suitable for carrying the receiver.

Examples of the present invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block diagram of a message broadcast apparatus embodying the present invention; Figures 2 and 3 are block diagrams illustrating an arrangement for digitally recording a message in Read Only Memory; and Figure 4 is a block diagram of a portable message receiver circuit for use with the broadcast apparatus of Figure 1.

Referring to Figure 1, the message to be broadcast is stored in Read Only Memory contained on up to eight memory boards 11 to 18. Each board may carry up to eight 32K byte memory chips with eight bit byte length. The total of 64 memory chips are arranged in an eight by eight matrix of columns and rows for access to an eight bit output databus 19.

The eight chips on any one board may be regarded as forming a column of the matrix and a corresponding chip from each of the eight boards may be regarded as forming a row of chips.

In operation during playback of the message stored in the memory, sucessive bytes of the memory are read onto the databus 19 at a rate corresponding to the sampling rate employed when digitising and recording the message in the memory. For example if the message is speech with a bandwidth up to 3kHz, the sampling rate may have been 6kHz. Then the addressing of the respective bytes of memory is controlled from a clock 20 having a period of 166pus. Clock pulses from the clock 20 are counted initially by a fifteen bit counter 21 and changes in the state of the most significant bit of the counter 21 are themselves counted in a six bit counter 22.

In this way a complete address code of 21 bits word length can be generated to identify uniquely each one of the bytes contained in the memory. The output state of the counter 21 is supplied over a fifteen bit address bus to each of the 32K chips contained in the memory. At the same time, the least significant three bits of the six bit counter 22 are supplied to a three to eight decoder 24 to select one of eight output lines 25 from the decoder. The eight output control lines are supplied respectively to the enable inputs of the eight chips contained on each of the memory boards 11 to 18. At the same time, the three most significant bits from the six bit counter 22 are supplied to a second decoder 26 to produce an enable signal on one of eight output lines 27 from the decoder 26.The output lines 27 from the decoder 26 are fed as enable signals to the respective memory boards 11 to 18.

A chip of a particular memory board is enabled for the reading of its contents on to the databus 19 only when the memory board containing the chip is selected by an enable signal from the decoder 26 and the chip in question on that board is enabled by an enable signal from the decoder 24.

It can be seen that, with this arrangement, the fifteen bit counter cycles through a complete set of 32K addresses during the selection of each chip in turn on the selected board. Thus the bytes in the memory are read at a sampling rate of about 6kHz (corresponding to a period of 166pS) and supplied in succession at this sampling rate on the output databus 19. The successive eight bit words on the databus are supplied to a digital to analogue converter 28 which reproduces therefrom the original recorded audio message on an output line 29. This audio signal is supplied on the line 29 to a radio transmitter 30 which transmits the signal from an antenna 31. In the described example the radio transmitter is a low power frequency modulated transmitter operated at 46MHz.

It can be seen that the above described transmitter arrangement has a total digital memory capacity of 64 x 32K bytes. With a cycle time of 166pS, one 32K byte chip can provide 5.4 seconds of message. Thus the full 64 memory chips can provide about 5 minutes of message. However, it is a requirement of the described apparatus that any recorded message is continuously repeated and it will be understood that the recorded message may be of any length up to the maximum capacity of 5 minutes.

During the process of recording the message into the memory (which will be described in more detail later herein), the number of 32K byte chips employed to contain the whole desired message is noted. When the prerecorded chips are installed in the broadcast unit illustrated in Figure 1, the number of chips used, corresponding to the length of the message, is coded into the broadcast unit by means of a set of Dual In Line (DIL) switches 32.

There are six such Dual In Line switches provided for coding six binary bits. During playback of the message, the status of the six most significant bits of the complete address code, that is the six bit output from the counter 22, is compared in a comparator 33 with the six bit word set by the Dual In Line switches. In this way, after selection by the broadcast apparatus of the last memory chip, a reset signal is generated by the comparator 33 on a line 34 which resets the counters 21 and 22 back to the start of the message.

Referring now to Figure 2, a block schematic diagram is illustrated of part of the apparatus for digitising and recording a desired audio message.

The intended message to be recorded, which may be a speech commentry perhaps with background music, is fed on a line 40 to a low pass filter 41 which substantially removes any frequency components above 3kHz. The filtered audio signal is supplied to a sample and hold circuit 42 via a level indicator 43 to enable the level of the audio signal to be adjusted to a predetermined level. The sample and hold circuit 42 receives sample pulses on a line 44 from a timer 45 driven from a clock 46. The sample pulses have a period of about 166pS providing a sampling rate of about 6kHz. The analogue signal samples are supplied to a digital to analogue converter 47 which provides on eight output lines 48 an eight bit binary word corresponding to the sampled level.Each of the successive eight bit words on the lines 48 are written into successive locations or bytes of Random Access Memory (RAM) 49. The Random Access Memory 49 comprises 64 chips each of 32K eight bit bytes. The bytes in each chip are addressed simultaneously by the fifteen bit output from address counter 50 on lines 53. The address counter 50 is clocked by a pulse from timer 45 synchronised with the clock 46. An overflow pulse from the address counter 50 is supplied on line 54 to a group enable generator 51 which applies an enable signal successively to each of 64 enable lines 52 to enable a selected one of the 64 32K chips in the memory 49.

In this way the eight bit bytes in the memory are successively enabled in synchronism with the eight bit words supplied on the data input lines 48 so that these words can be written into the memory in real time.

The operation of the sample and hold circuit 42, the digital to analogue converter 47, the provision of write pulses to the memory 49 and the clocking of the address counter 50 are all synchronised by the timer 45 with the clock 46.

As explained previously, the maximum length of message which can be stored in real time in the memory 49 with the capacity described above is about 5 minutes. However, if the message is shorter than this, the clock 46 is effectively stopped once the complete message has been recorded. A memory counter 55 counts the number of overflow pulses from the address counter 50 to provide an indication of the number of 32K byte chips which have been selected during the recording process. Thus, if the clock is stopped after three minutes, the memory counter 55 will indicate that 33 of the 64 chips have been selected. This number is important for two reasons.

Firstly, this is the number which may be encoded into the Dual In Line switches 32 of the broadcast unit to ensure the broadcast unit resets at the right position at the end of the message. Secondly, if only 33 chips are employed, then only 33 memory chips need be inserted on the memory boards employed in the broadcast units with attendant saving in costs.

The recording system described so far with reference to Figure 2, has the effect of recording the message in real time into Random Access Memory.

With the present state of technology, it is not possible to record into Read Only Memory with the necessary cycle time of 166us.

Figure 3 illustrates a convenient arrangement for selecting the various chips of the memory 49, by arranging the 64 chips in an eight by eight matrix of rows and columns. The group enable generator 51 includes a row decoder 60 and a column decoder 61 which have the effect of selecting the memory chips column by column, so that the incoming data on lines 48 can be written into the selected memory chips starting with the 32K bytes of memory chip M1 and continuing with chips M2, M3 etc., to the last chip M8 of the first column, before continuing with the first chip M9 of the second column and so forth.

Once the complete message is recorded in the Random Access Memory chips, it is necessary for this digital data to be loaded into Read Only Memory. The typical cycle time for writing into electrically programmable Read Only Memory is about 30mS. If the Read Only Memory was loaded byte by byte from RAM, a five minute message would take some fifteen hours to load.

In order to load the ROM from RAM more quickly, data lines from each column of RAM are connected to each member of a corresponding column of ROM. Then data is read from each of the columns of RAM and written into corresponding locations in the columns of ROM simultaneously. This is achieved by selecting all eight columns of RAM during the reading out procedure and addressing the bytes of each chip whilst successively selecting the various rows of chips. In this way, on each data transfer involving a ROM writing cycle, eight separate eight bit words of data are simultaneously written into selected bytes in each of the eight columns of ROM. As a result the time taken to load the ROM can be reduced by a factor of eight.

Figure 4 illustrates a form of receiver which may be employed with the broad cast unit for receiving the broadcast messages. It should be appreciated that the receiver should be small, lightweight, battery operated and easily carried. In operation, the transmitter units will be at fixed locations, e.g. at tourist interest points, and the message transmitted will include information on the particular tourist attraction.

The receiver units may for example be provided for a rental payment which will typically enable their use for say one day at the end of which they should be returned.

Each receiver unit has an antenna which may be incorporated in the neck strap of the unit. The antenna 60 supplies received radio signals via a matching circuit 61 to a radio receiving and demodulating unit 62. The received signal will normally be at a single known frequency and so the receiving circuits in 62 may be pretuned. The receiving circuitry 62 receives a Local Oscillator signal from a crystal oscillator 63. The output from the receiving and demodulating circuit 62 is fed via an audio filter 64 to remove any IF content in the detected signal, to an audio amplifier 65 via a volume control 66. The amplified audio signal may be heard from a loud speaker 67.

Power supply to the receiving and demodulating circuit 62 and the amplifier 65 is fed from an internal battery 68 via a push button switch 69. Thus the receiver unit is energised only on depression of the push button switch 69. Typically the push button will be spring loaded so that continued pressure on the push button is required to energise the unit to receive the broadcast message.

Instead of a push button switch, a tilt switch may be used to energise the unit automatically when lifted by the user to his or her ear.

Power from the battery 68 is supplied continuously via a protective diode 70 to a timer circuit 71. The timer circuit 71 is arranged to time out after a preselected period which may be for example one, two or four days in accordance with links connected at 72. On timing out, the timer circuit applies a control signal on line 73 to open an electronic switch 74 provided in the power supply line to the receiving and demodulating circuit 62.

Thus, once the timer circuit times out, the receiving and demodulating circuit is disabled so that the unit is no longer functional. The timer circuit 71 may be reset by applying a reset signal on line 75, e.g. by capacitive coupling from outside the unit. In practice, the line 75 may terminate at a conductive plate on the surface of the casing of the unit to which the reset signal may be coupled capacitively when the unit is first supplied to a customer. As explained above, the normal terms for use of the unit will be rental for a limited period of time and the operation of the timer circuit ensures that the unit becomes useless to the person hiring it once the duration of the rental has expired.

By arranging the electronic switch 74 to control the power supply only to the receiving and demodulating circuit 62, the power rating of the switch 74 is kept to a minimum, since the supply requirements of the circuit 62 is commonly much less than that required by the audio amplifier 65.

Claims (11)

1. Message broadcast apparatus comprising a generator to generate an automatically repeating analogue message and a transmitter to broadcast the repeating message for reception in the vicinity of the broadcast apparatus, wherein said message generator comprises digital storage means for storing the message as a series of digital words representing successive values of the analogue message sampled at a sampling rate, reading means to read successive said digital words in said series from the storage means at the sampling rate, a digital to analogue converter to reconstitute said analogue message from the successively read digital words, and reset means to reset the reading means on reaching the end of the stored message to start reading again at the beginning of said series of digital words to repeat the message.

2. Apparatus as claimed in claim 1, wherein said reading means includes an address generator to generate address codes uniquely addressing bytes of the digital storage means containing the successive digital words of the series for reading, and said reset means comprises a comparator to compare the generated address codes with a preset code representing the address of a byte at the end of the stored message and to produce a reset signal on reaching said end of message address to reset the address generator to the beginning of the message.

3. Apparatus as claimed in claim 2, wherein the comparator compares only the most significant bits of the address codes with a preset code.

4. Apparatus as claimed in claim 3, wherein the address generator can address up to 64 x 32,768 (64 x 32K) bytes and the comparator compares only the six most significant bits of the address codes with a six bit preset code.

5. Apparatus as claimed in any of claims 2 to 4, wherein said comparator includes manually settable switch means for setting up said preset code.

6. A method of digitally recording an analogue signal of predetermined duration in Read Only Memory (ROM) comprising sampling the analogue signal at a sampling rate which is at least twice the maximum frequency to be recorded in the analogue signal, digitising the samples to produce digital words representing the sampled values of the analogue signal, writing the digital words successively at the sampling rate in successively addressed bytes of a Random Access Memory (RAM) until the full duration of the analogue signal is digitally recorded in the RAM, and then reading the stored words from the RAM in successive parallel sets from simultaneously addressed bytes and at a repetition rate for the successive sets which is less than said sampling rate, and writing the successive parallel sets of words at said repetition rate into corresponding bytes of the Read Only Memory.

7. A method as claimed in claim 5, wherein said sampling rate is not less than 5kHz, and said repetition rate is not more than 1k Hz.

8. A portable radio broadcast message receiver comprising a radio receiving and demodulating circuit to produce an audio signal representing a received message, an audio amplifying circuit to amplify the audio signal to drive an audio transducer, and power supply means for supplying electrical power to said circuits from a battery or cell, and further including an electronic timer powered from said battery or cell, inhibit means responsive to the timer timing out to inhibit continued operation of the receiver and reset means arranged for co-operation with a separate initiating means to reset the timer to initiate operation of the receiver for a period determined by the timer.

9. A message receiver as claimed in claim 8, wherein the inhibit means comprises an electrically operable switch in the power supply means cutting off power to at least said receiving and demodulating circuit.

10. A message receiver as claimed in either of claims 8 and 9, wherein said reset means comprises an electrical contact point accessible from outside the receiver, whereby reset is effected by applying a predetermined signal to said contact point.

11. A portable radio broadcast message receiver incorporating an antenna in the form of a flexible strap suitable for carrying the receiver.