GB2222741A - HDTV circuit for deriving line, field and picture sync pules from a three-level sync signal - Google Patents

Description

A ( '1 '27 4 1 2 22-

CIRCUIT FOR DERIVING LINE7 FIELD AND PICTURE SYNC PULSES FROM A HIGH DEFINITION TV SYNC SIGNAL.

This invention relates to a circuit for deriving line, field and picture sync pulses from a high definition TV sync signal.

For synchronising the equipment in a television transmission chain a sync signal is required, which is normally contained in the television signal and must be separated therefrom for synchronisation purposes. This sync signal comprises two components, the horizontal component for the synchronisation of the line deflection and the vertical component for synchronising the picture deflection. The horizontal component is used to form line-frequency or H-frequency pulses, also called line sync pulses, whilst the vertical component is used to form V-frequency pulses, also called picture frequency pulses. These two components must be separated in each television receiver. Methods and circuits are known by means of which it is possible to separate the sync signal hitherto used in standard television and having only two different levels. However, for highdefinition television (HDTV) systems sync signals which have three different levels are preferred (cf. e.g. SMPTE Journal, November 1987, pp.1150 to 1152). The advantage of such sync signals is that they are free from mean values, i.e. they contain no d.c. voltage component.

A The object of the present invention is to provide a circuit for processing HDTV sync signals having three levels to rpovide line, field and picture sync pulses.

Accordingly, the"present invention provides a circuit for deriving line, field and picture sync pulses from a three-level sync signal of a highdefinition television signal, comprising means responsive to rising edges of the sync signal to generate respective pulses each having a leading edge defined by a rising edge crossing the zero level of the sync signal and a trailing edge defined by the rising edge crossing a reference level intermediate the zero level and the maximum positive level of the sync signal, such means being enabled at the beginning of each line to generate a line sync pulse in response to a rising edge of the sync signal then oc-urring but being inhibited from responding to any further rising edges of the sync signal occurring thereafter for greater than half a line duration whereby only one line sync pulse is generated per line, the circuit further comprising means for detecting end-of-field and endof-picture defining components of the sync signal occurring during the first half of the last line of each field and for generating a field sync pulse when either such component is detected, the field sync pulse being substantially longer when such-end- of-field defining component is also an end-of-picture defining component than when it is not, and means for detecting each such longer field sync pulse to generate a respective picture sync pulse.

c The circuit according to the present invention has the advantage that it is very flexible and reliable, that is it operates in a satisfactory manner in the presence of noise.

An embodiment of a circuit according to the present invention will now be particularly.described with reference to the accompanying drawings, wherein:

Figure 1 is a block diagram of a circuit according to the present invention, Figure 2 is a block circuit diagram of the logic circuits shown in Figure 1, and Figure 3 comprises pulse diagrams to explain the operation of Figures 1 and 2.

Referring to the drawings, the block circuit diagram of Figure 1 for deriving line, field and picture sync pulses from a threelevel HDTV sync signal S applied to a terminal 1 essentially comprises a peak value rectifier circuit 2, to which the sync signal S is supplied, a comparator stage 3 which is also supplied with the sync signal S, and a logic circuit 4 at whose outputs 6,7 and 8 are available the line, field and picture sync pulses H, V and 2V respectively. The rectifier circuit 2 comprises two active peak value rectifiers with alarge dynamic range. By means of these rectifiers reference d.c. voltage levels are obtained from the input sync signal S at -50%, 0% and +50% of the sync signal, that is half way between the zero level and the. maximum negative level of the sync signal S, at the zero level, and half way between the zero level and the maximum positive level-of the sync signal. The reference d..c. voltage levels are supplied to the comparator stage 3, which contains three comparators for comparing the input sync signals with the three reference voltage levels. Thus. at the outputs of the comparator stage 3 there are three TTL-compatible signals (.R, h and c of Figure 3)for further processing in the logic circuit 4. The logic circuit 41s timed with two 'Clock signals T1 and T2 supplied at terminals 9 and 10 respectively.

Figure 2 is a detailed block circuit diagram of the logic circuit 4, which essentially comprises a counter 11, a D-Flip-Flop 12 and a programmable logic component 13 (e.g.PAL or GAL)._Counter 11 is timed with the clock signal T1, whose frequency is e.g. 3.375 MHz, and is reset with the line sync pulses H. The counter 11, which serves to produce all the-time relationships required in the circuit, must not overflow during a line period at the clock frequency T1 used. The clock frequency need not be coupled with the line frequency. The logic component 13 is timed with the clock signal T2, whose frequency is e.g. twice T1, i.e. 6.75 MHz.

The operation of the circuit of Figure 2 will now be explained in connection with the pulse diagrams of Figures 3a to 3c, in which Figure 3a shows the form of the three-level HDTV sync-signal for line 625 (end of field), Figure.3b the form of the sync signal for for line 1250 (end of field and end of picture), and Figure 3c the form of the sync signal for all other lines. The foregoing assumes 625 lines per field, and 2 fields per picture.

The short sync signal shown in Figure 3c, which occurs at the beginning of each line, is used, as will be described, to derive a line sync pulse at the beginning of each line, and since it forms a component of the more complex extended sync signals present during the first half of lines 625 and 1250. a line sync pulse is derived also in respect of these lines.' Further, as will be described, each of the extended sync signals present during lines 625 and 1250 are used to derive a respective field sync pulse, but the different form of the extended sync signals for lines 625 and 1250 provides a means for distinguishing between lines 625 and 1250 to permit a picture sync pulse to be derived for line 1250 as well as a field sync pulse.

As can be seen by inspection of Figure 3, the pulse train a is derived in the comparator 3 by comparison of the sync signal with the zero level of the sync signal, the pulse train b is derived by comparison with the +50% level of the sync signal, and the pulse train b is derived by comparison with the -50% level of the sync signal.

The hatched regions of the pulse trains a represent an undefined state of the pulse train.

In the pulse train a. leading edges, indicated by the arrows, are produced when a rising edge of the sync signal S crosses the zero reference level. The pulse train a is supplied to the clock input of the D-FlipFlop 12, which has a logic-'T' applied at Its D-input. Thus in each line the first leading edge in the pulse train a produces at the output Q of the flip-flop a positive-going pulse (a line sync pulse H) whose trailing edge is produced by the trailing edge of pulse d resettin g the flip-flop 12. The trailing edge of pulse d is obtained from the leading edge of pulse b in the logic component 13.

In addition, a time condition is derived from the counter 11. so that the flip-flop 12 is held reset for longer than half a line by the pulse train d. Thus the leading edge of the pulse train a located in the centre of line 625 cannot activate the flip-flop 12, so that consequently no further line sync pulse can be produced at the output 6 for that line. The reset input remains active until the next positive pulse c, whereupon the foregoing cycle starts again. Thus line sync pulses are available.at the output 6 of the flip-flop 12, which are free from all V and 2Vcomponents. The length of these pulses is undefined and is dependent on the rise time of the input sync signal and the delay times of the circuits. Therefore only the leading adge of the line sync pulses should be used as a reference.

1 :1 For deriving the field and picture sync pulses V and 2V respectively, in each line the sync signal S is checked during the time in which a field or picture component can be expected to occur, i.e. during the first half of each line..If such a component is detected, during the line 625 or 1250, then a pulse e is derived in the logic component 13 from the pulse train c. The trailing edge of the pulse e occurs simultaneously with the trailing edge of pulses c, so that for line 625 the pulse e terminates in the middle of-the line, whereas for line 1250 the pulse e terminates at the end of the line or the start of line 1. The pulses e, one for each line, are the field sync pulses V.

For producing the picture sync pulse 2V, during the second half of each line the pulse e in the logic component 13 is examined and if the pulse e is present during this time a pulse f is derived as shown in Figure 3B.Pulse f is only active during line 1250 and ends at the start of line 1. From the trailing edge of this pulse f there is derived in the logic component 13 the picture sync pulse E, which becomes active with the start of line 1. Depending upon requirements, the duration of this 2V pulse a can either be derived from the counter 11 or from the H-component of the sync signal.

It is pointed out that the above-described arrangement can also be used for separating a conventional bipolar sync signal, if the programming of the logic component 13 is correspondingly modified. It is naturally also possible to use such an arrangement in systems, in which both sync signals can occur. However, it would then be necessary to provide a further input line of 5 logic component 13, in order to permit switching.

Claims (6)

CLAIMS.

1. A circuit for deriving line, field and picture sync pulses from a three-level sync signal of a high definition television signal, comprising means responsive to rising edges of the sync signal to generate respective pulses each having a leading edge defined by a rising edge crossing the zero level of the sync signal and a trailing edge defined by the rising edge crossing a reference level intermediate the zero level and the maximum positive level of the sync signal, such means being enabled at the beginning of each line to generate a line sync pulse in response to a rising edge of the sync signal then occurring but being inhibited from responding to any further rising edges of the sync signal occurring thereafter for greater than half a line duration whereby only one line sync pulse is generated per line, the circuit further comprising means for detecting end-of-field and endofpicture defining components of the sync signal occurring during the first half of the last line of each field and for generating a field sync pulse when either such component is detected, the field sync pulse being substantially longer when such end-of-field defining component is also an end-of-picture defining component than when it is not, and means for detecting each such longer field sync pulse to generate a respective picture sync pulse.

2. A circuit according to Claim 1. in which a first pulse signal a is derived by comparing the sync signal with a first reference level corresponding to the zero level of the sync signal, a second pulse signal b is derived by comparing the sync signal with a second reference level located between the first reference voltage and the maximum 'positive level of the sync signal, a third pulse signal c is derived by comparing the sync signal with a-third reference voltage located between the first reference voltage and the maximum negative level of the sync signal, the line sync pulses being derived from the first and second pulse signals, and a fourth pulse signal d is derived from the leading edge of the second and the third pulse signals, the.

fourth pulse signal inhibiting the derivation of more than one line -sync pulse per line.

3. A circuit according to Claim 2, wherein the reference levels are derived by rectification of the three-level sync signal, the second..and third reference levels being at approximately+50% and -50% of the sync signal amplitude referred to the zero level.

4. A circuit according to Claim 3, including a peak value rectifier circuit at whose output is applied the three-level sync signal And at whose output are derived the three reference levels, a comparator stage with three comparators for comparing the level of the input sync signal with the thr ee reference levels for. deriving the three pulse signals a, h, and c, and a logic circuit at.whose inputs are applied the three 1 3 pulse signals a, b, and c and at whose outputs are provided the line, field and picture sync pulses.

5. A circuit according to Claim 4, wherein the logic circuit comprises'a D-Flip-Flop whose D-input is set to logic 'T', whose clock input is supplied with the first pulse signal a, and whose resetting input is supplied with the fourth pulse signal d, whereby the Flip-Flop supplies at its output the line sync pulses, and a programmable logic component which is timed with a first clock signal and to whose inputs are applied the second and third pulse signals and the output of a counter which is timed with a second clock signal and at whose resetting input is applied the line sync pulse, the output of the programmable logic component supplying the field and picture sync pulses and the fourth pulse signal.

6. A circuit as claimed in Claim 1, substantially as hereinbefore described with reference to the accompanying drawings.

Published 1990 It The Patent OffiCe. State House, 8#17 t Ha9hHolburn. landon WC1R4TP_ Furtl%ercoples maybe obwnedftlom The PILtentOMes. sr- nim. -im?) Pim,.a ivw muitinlextechnIQU" Itd. StMWT Cray. Unt. Com 1,87 Tr112R.ItIz?) ivw muitinlex technum" Itd. StMary Cray. Xent. Con. 1,87