GB2222305A

GB2222305A - Integrated injection logic circuit

Info

Publication number: GB2222305A
Application number: GB8819948A
Authority: GB
Inventors: Peter Henry Saul
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-08-23
Filing date: 1988-08-23
Publication date: 1990-02-28
Also published as: GB8819948D0

Abstract

The I<2>L circuit comprises a lateral injection current source transistor (11, 7, 9) and an integrated vertical drive transistor (13, 9). The latter transistor has a number of emitters (13). The structural implementation of this circuit includes a buried layer (7) of enriched doped material, which latter may be entirely isolated from external electrical contact. This circuit has a regenerative action and with appropriate biasing will provide latching. It is suitable for manufacture on small geometry bipolar standard processes. A resistor (15) may be connected between the emitter (11) and collector (9) of the injection current source transistor (T1) to compensate for the effects of spurious leakage current at input. <IMAGE>

Description

1N l EGRATED INJECTION LOGIC CIRCUIT The present invention concerns improvements in or relating to integrated injection logic circuits, and, more particularly circuits designed with very small feature size geometry.

A typical integrated injection logic (I2L) structure is shown in cross-section in figure 1. In this structure a pair of transistors Tl, T2 are defined, specifically an injection current source transistor Ii, and, an output drive transistor T2. These transistors T1, T2 are integrated, i.e. of merged structure. As shown in figure 1 the structure comprises a silicon crystal substrate 1 in which an active area 3 of a first polarity type (e.g. n-type), is delineated and is isolated by an isolating trench 5 or other means. Incorporated in the active area 3 is a buried layer 7 of enriched doped material. Overlying this buried layer 7 are two enriched doped regions 9, 11 of a second opposite polarity type - (e.g. p-type). These two regions 9, 11 are spaced vertically from the enriched doped buried layer 7.One of these two regions, region 9, is of significant lateral extent. A plurality of transistor emitters 13 are defined in, or immediately vertically adjacent to, this laterally extended region 9. As shown, these emitters 13 are defined by enriched doped regions of the first polarity type (e.g. n-type). Alternatively the emitters 13 may be defined by Schottky metal contacts (not shown) vertically adjacent to the surface of the extended region 9. Typically, the doped regions 9, 11 and 13 shown may be produced by standard implantation and diffusion techniques. The emitter, the base, and the collector of the injection current source transistor T1, a lateral transistor, are thus provided by the region 11, the regions 1 and 7, and the region 9, respectively.The emitters, the base, and the collector of the drive transistor T2, a vertical transistor, are thus provided by the emitters 13, the extended region 9, and the regions 1 and 7, respectively. It will be noted that in this integrated merged structure the region 9 and the regions 1 and 7 are common to the structure of the two transistors T1 and T2. In this structure an enriched doped diffusion (not shown), of the first polarity type, is invariably provided to allow external electrical contact to be made to the buried layer 7. This requires additional layout area at the surface of the structure.

The conventional circuit arrangement for the abovedescribed structure is shown in figure 2. In this circuit the emitter 11 of the injected current source transistor T1 is connected to a first voltage rail which is maintained at a reference high voltage, that is, the supply voltage Vcc provided for the level of logic in which this structure is employed. Notably, the base 7 of this transistor T1, and, in common therewith, the collector 7 of the drive transistor T2, are connected to a second voltage rail which is maintained at a lower reference voltage, which is for example, as shown, the circuit earth voltage Ov. The collector 9 of the injected current source transistor T1, and in common therewith, the base 9 of the drive transistor T2, are connected to receive input signal I/P from the output of a preceding stage of logic circuitry.Also noted, each of the emitters 13 provide fanned-out output signals OIP and are connected to inputs of the next successive stage of logic circuitr#-.

The above structure and circuit are viable on many integrated bipolar processes of ordinary feature size capability. It is a problem.

however, that as this structure is scaled down to very small feature size geometries - i.e. micron and especially sub-micron feature size, a condition can arise in which the forward bias voltage required to turn on the base-emitter junction of the injected current source transistor T1 is necessarily smaller than that required to turn on the drive transistor T2. At best, this can result in the dissipation of injected current; at worst, it can lead to an inoperative condition.

The present invention is intended to provide a solution to the problem aforesaid. A circuit reconfiguration is provided that is compatible with very small feature size geometry integrated circuit bipolar processing.

In accordance with a first aspect of the invention there is provided an integrated injection logic circuit comprising: first and second voltage rails; and an integrated transistors structure including: a semiconductor substrate in which an active area is delineated and isolated; an injection current source transistor having an emitter, a base, and a collector; and, a drive transistor having a plurality of emitters, a base, and a collector; wherein, the collector of the injection current source transistor and the base of the drive transistor are of common structure; the base of the injection current source transistor and the collector of the drive transistor are also of common structure, comprising a buried layer of enriched doped material; the emitter of the injection current source transistor is connected to the first voltage rail and via this to a source of reference high voltage; and, the collector of the injection current source transistor is connected to receive an input logic signal; characterised in that: one of the emitters of the drive transistor is connected to the second voltage rail and via this to a source of reference low voltage The circuit defined will provide a regenerative action as described more fully below and given appropriate biasing will also provide a latching response to changes in the state of the input logic signal.

The circuit may be improved to afford better immunity to the effects of leakage current by including a resistive connection between the emitter and collector of the injection current source transistor.

In the integrated transistors structure, part of this circuit, the buried layer of enriched doped material may be isolated from all external electrical contact.

In accordance with a second aspect of the invention there is provided an integrated injection logic circuit comprising: first and second voltage rails; an injection current source transistor having an emitter, a base, and a collector, of which the emitter is connected to the first voltage rail; a drive transistor having a plurality of emitters, a base, and a collector, of which the base is connected to the collector of the injection current source transistor, and of which one of the emitters is connected to the second voltage rail; and, a third transistor having an emitter, a base, and a collector, of which the collector and base are connected, respectively, to the base and collector of the injection current source transistor, and of which the emitter is connected to the second voltage rail.

As will be shown below, this latter is the electronic circuit equivalent of the circuit first defined.

In the drawings accompanying this specification: Figure 1 is a cross-section view of a known, merged transistor, integrated injection logic structure; Figure 2 is a circuit diagram showing a known circuit implementation of the structure of the preceding figure; Figure 3 is a cross-section view of an integrated injection logic structure modified in accordance with this invention; Figure 4 is a circuit diagram showing the equivalent circuit and modified circuit configuration of the structure shown in the preceding figure; and, Figure 5 is a circuit diagram showing a variant of the circuit configuration shown in the preceding figure.

In order that this invention may be better understood, embodiments thereof will now be described and reference will be made to figures 3 to 5 of the accompanying drawings. The description that follows is given by way of example only.

The structure shown in figure 3 is essentially similar to the structure already shown and described with reference to figure 1 and the same reference numerals are adopted in this figure. A principal distinction is the omission of the connective enriched doped diffusion between the substrate surface and the buried layer 7.

Notably this buried layer 7 is effectively isolated from external electrical contact. A major modification is provided in the connection of the structure to the second voltage rail - one of the emitters 13 is connected to this rail "Ov" and the voltage on the base 7 of the injected current source transistor is allowed to float. This is depicted in the equivalent circuit shown in figure 4.

In this equivalent circuit a third transistor T3 is depicted. The collector of this transistor T3 is shown connected to the base of the injected current source transistor T1. In fact this collector and the base mentioned are provided by common structure, the substrate vertical spacing material 1 and the buried layer 7. The base of this third transistor T3 is shown connected to the base of the drive transistor T2 and again these are of a common structure as provided by the enriched doped region 9, which is also the collector of the injected current source transistor T1, as previously stated. The emitter 13 of this third transistor is the one emitter referred to, which emitter 13 is connected to the second voltage rail "Ov". In order to provide equivalent fan-out an additional emitter is provided.Thus to provide a fan-out of three output signals, three emitters 13 are provided for this purpose, and an additional emitter is provided for connection to the second voltage rail, i.e. four emitters 13 in all, are provided, as shown.

The operation of this circuit will now be detailed. If initially the input signal I/P is pulled low (i.e. below the forward bias potential of the drive transistor T2 and the third transistor T3) then both transistors T2, T3 will be biassed in an "off" condition. The injection current source transistor T1 will also be in this "off" condition. It will be noted that in this condition the input pull-up current is substantially zero, avoiding loading of the preceding stage of logic circuitry and the wasteful dissipation of current hitherto a characteristic of the known circuit of figure 2. If now the input signal level is raised to a value above the threshold of the turn-on voltage of the drive transistor T2 and the third transistor T3, these transistors T2, T3 are then switched to an "on" condition, as is the injection current source transistor T1.This is a regenerative action and in appropriate bias conditions this will result in latching.

The advantages of this circuit arrangement is summarised as follows: (i) Manufacture using an unmodified (i.e. standard) small feature size geometry bipolar process is possible; (ii) Supply current corresponding to the input low state may be reduced to zero, with a consequent saving in power consumption; (iii) The action of the circuit is regenerative; The The circuit, with appropriate biasing, will exhibit latching action, and thus can have application as a latch element requiring only very small layout area; and, (v) Since the base of the injection current source transistor T1 is operated at a floating potential, connection to the buried base layer 7 is not required and the connective diffusion and contact may be omitted with a significant saving in layout area.

In circuit implementations in which the output of the preceding logic circuitry is not clamped to ground, a condition can occur wherein leakage currents will cause the injection current source transistor T1, the drive transistor T2 and the third transistor T3 to turn on. This may be remedied, in some processes, by the provision of a resistive connection R1 made between the emitter 11 and collector 9 of the injection current source transistor T1. This could be provided by a small filament of base substrate p-type high resistance material in the substrate. Alternatively, a specific thin high resistivity p-type layer 15 may be implanted at the surface of the substrate 1 or an epitaxially grown resistor may be provided to ensure corrective operation. This is shown in broken outline in figure 3 and the resistor R1 is shown in figure 5.

Claims

What I/We claim is: 1. An integrated injection logic circuit comprising: first and second voltage rails; and an integrated transistors structure including: a semiconductor substrate in which an active area is delineated and isolated; an injection current source transistor having an emitter, a base. and a collector; and, a drive transistor having a plurality of emitters, a base, and a collector; wherein, the collector of the injection current source transistor and the base of the drive transistor are of common structure; the base of the injection current source transistor and the collector of the drive transistor are also of common structure, comprising a buried layer of enriched doped material; the emitter of the injection current source transistor is connected to the first voltage rail and via this to a source of reference high voltage; and, the collector of the injection current source transistor is connected to receive an input logic signal; characterised in that: one of the emitters of the drive transistor is connected to the second voltage rail and via this to a source of reference low voltage.
2. A circuit, as claimed in claim 1, when biassed to provide a regenerative and latching action responsive to a change in state of the input logic signal.
3. A circuit, as claimed in either one of the preceding claim 1 or 2, including a resistive structure located across the emitter and the collector of the injection current source transistor.
4. An integrated injection logic circuit constructed adapted and arranged to perform substantially as hereinbefore described with reference to and as shown in figures 3 and 4 or in figures 3 and 5 of the accompanying drawings.
5. An integrated transistors structure, for use in the circuit as claimed in claim 1, including: a semiconductor substrate in which an active area is delineated and isolated; an injection current source transistor having an emitter, a base, and a collector; and, a drive transistor having a plurality of emitters, a base, and a collector; wherein, the collector of the integration current source transistor and the base of the drive transistor are of common structure; the base of the integration current source transistor and the collector of the drive transistor are also of common structure, comprising a buried layer of enriched doped material; characterised in that: the buried layer of enriched doped material is isolated from external electrical contact.
6. An integrated transistors structure, as claimed in claim 5, including a resistive structure located across the emitter and the collector of the injection current source transistor.
7. An integrated transistors structure, as claimed in claim 6, wherein the resistive structure aforesaid is a filament of base substrate high resistance material.
8. An integrated transistors structure, as claimed in claim 6 wherein the resistive structure aforesaid is a surface implanted diffusion.
9. An integrated transistors structure, as claimed in claim 6, wherein the resistive structure aforesaid is of epitaxial high resistance material.
10. An integrated transistors structure constructed and adapted substantially as described hereinbefore with reference to and as shown in figure 3 of the accompanying drawings.
11. An integrated injection logic circuit comprising: first and second voltage rails; an injection current source transistor having an emitter, a base, and a collector, of which the emitter is connected to the first voltage rail; a drive transistor having a plurality of emitters, a base, and a collector, of which the base is connected to the collector of the injection current source transistor, and of which one of the emitters is connected to the second voltage rail; and, a third transistor having an emitter, a base, and a collector, of which the collector and base are connected, respectively, to the base and collector of the injection current source transistor, and of which the emitter is connected to the second voltage rail.
12. A circuit, as claimed in claim 11, including a resistor connected across the emitter and collector of the injection current source transistor.
13. A circuit, as claimed in either one of claims 11 or 12, in which the injection current source transistor is of pnp type and the drive and third transistors are of npn type.

13. A circuit, as claimed in either one of claims 11 or 12, in which the injection current source transistor is of pnp type and the drive and third transistors are of npn type.

Amendments to the claims have been filed as follows What I/We claim is: 1. An integrated injection logic circuit comprising: first and second voltage rails; and an integrated transistors structure including: a semiconductor substrate in which an active area is delineated and isolated; an injection current source transistor having an emitter, a base, and a collector; and, a drive transistor having a plurality of emitters, a base, and a collector; wherein, the collector of the injection current source transistor and the base of the drive transistor are of common structure; the base of the injection current source transistor and the collector of the drive transistor are also of common structure, comprising a buried layer of enriched doped material; the emitter of the injection current source transistor is connected to the first voltage rail and via this to a source of reference high voltage; and, the collector of the injection current source transistor is connected to receive an input logic signal; characterised in that: one of the emitters of the drive transistor is connected directly to the second voltage rail and via this to a source of reference low voltage; and, voltage on the base of the injection current source transistor is allowed to float.

a drive transistor having a plurality of emitters, a base, and a collector, of which the base is connected to the collector of the injection current source transistor, of which the collector is connected to the base of the injection current source transistor, and, of which one of the emitters is connected to the second voltage rail; and, a third transistor having an emitter, a base, and a collector, of which the collector and base are connected, respectively, to the base and collector of the injection current source transistor, and of which the emitter is connected to the second voltage rail.

12. A circuit, as claimed in claim 11, including a resistor connected across the emitter and collector of the injection current source transistor.