GB2221806A - Inverter short circuit protection - Google Patents

Abstract

The output semiconductors 36-44 of an inverter are protected from damage from short circuits by a combination of subcircuits that interact with each other to control the timing and magnitude of the current and voltage at the semiconductors to limit maximum current and instantaneous power to safe levels. A conventional series-connected choke 10 between the DC source and the output semiconductors has a conventional back-connected diode 16 in parallel with it. At the output of the choke is a capacitive snubber circuit 18, comprising a parallel arrangement of a resistor 24 and rectifier 20, which is connected to the capacitor 26, the other end of the capacitor being connected to the other DC bus. The protective circuits cooperate with each other as follows. The main semiconductor eg. 44 is biased to non-conduction promptly when a fault is sensed at 28, 28A; the choke 10 limits the current and the capacitor 26 is substantially discharged early in the fault. The capacitor 26 is, therefore, in a condition to receive current and does receive it later in the fault when the voltage across the semiconductor is rising. In this way the semiconductor's maximum current is reduced, and the semiconductor is protected from having its maximum current occur at the same time that the voltage is highest. <IMAGE>

Description

INVERTER SHORT CIRCUIT PROTECTION METHOD AND APPARATUS BACKGROUND OF THE DISCLOSURE This invention relates to protection of the power semiconductors of inverters during a short circuit at the load terminals and during recovery thereafter. Inverter power semiconductors such as transistors have a nominal safe operating area of simultaneous voltage and current. The safe operating areas of currently available high-voltage Darlington transistors (such as Mitsubishi, Fuji and Toshiba transistors) are only marginally rated to handle output short circuits at normal to high line conditions when they are utilized as output switching devices in inverters having 460 volt and 575 volt AC outputs.In protection circuits of the prior art, when a short circuit occurs at the load terminals the limits of the safe operating area are sometimes greatly exceeded during the time of the short circuit or the recovery interval, damaging the power transistors.

SUMMARY OF THE INVENTION Applicants' invention reduces the maximum current and the product of voltage times current in inverter transistors during short circuit faults and during fault recovery, enabling the transistors to survive short circuits with higher reliability.

It reduces the amount by which the current boundary-of the nominal safe operating area is exceeded; (transistor specifications permit the current boundary to be exceeded momentarily on the current axis only, by three to four times rated current). The circuit performs its protective function by reducing the peak value of collector current and preventing the collector current from being high at the same time that the collector-to-emitter voltage is high.

One object of the invention is to protect inverter power transistors against destruction from short circuits.

Another object is to provide protection by which the current boundary is exceeded less than in prior systems, and only while the transistor is experiencing low voltages.

Another object is to provide a combination invention that includes a control circuit for turning off the power transistors upon sensing of a short circuit fault, a choke and diode in a DC bus of the inverter, and a "snubber" having a diode, resistor and capacitor connected across the inverter's DC buses. Forms of these subcircuits have been used individually in previous inverter equipment. The present invention is a combination of three particular subcircuits that, because of their cooperation involving timely interchange of energy between them, accomplishes a remarkable and unexpectedly great reduction of current peak and of instantaneous power dissipation in the output transistors upon load short circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram of the preferred embodiment of the invention, including relevant portions of an inverter with which it is used.

FIG. 2 has time graphs showing voltage and current waveforms in an inverter equipped with the invention, during and after a short circuit at the output.

FIG. 3 is a graph of the nominal safe operating area, i.e., current as a function of voltage, of a semiconductor of a type that is commonly used in the output circuits of static inverters. Another graph on the same scales shows the voltage and current at a semiconductor of an inverter having the invention, during and after a short circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT Three subcircuits in combination form the invention: Control subcircuit.

Series choke subcircuit.

Shunt snubber subcircuit.

CIRCUIT CONNECTIONS These subcircuits and their inverter circuit environment are connected as follows (FIG. 1): (a) Control Subcircuit. A control subcircuit 28 senses the collector-to-emitter voltage of a semiconductor 44 or 28A, the fault current in the semiconductor, or the current in the bus leads or the output leads or other means, and recognizes a fault when it occurs. Upon a short circuit, the fault sensing control subcircuit 28 produces an output signal that controls a gate terminal of the transistor 44,for switching the power semiconductor 44 to a non-conductive state.

Subcircuit 28 has other connections that are not shown. The other main power semiconductors are equipped with similar control subcircuits, which are.

omitted from FIG. 1 for clarity.

The control subcircuit 28 is in the prior art. It is fully described in U.S. Patent No. 4,651,252, issued March 17, 1987, entitled "Transistor Fault Tolerance Method and Apparatus" of inventor Thomas E. Babinski.

FIG. 4 and the appurtenant detailed description of that patent apply to this situation.

(b) Series Choke Subcircuit. In the preferred embodiment a DC power source (not shown) such as a rectifier or battery has its positive and negative output terminals, 2,4 connected to opposite ends of a capacitor 6. Positive terminal 2 is also connected to the input end 8 of the series choke subcircuit 10. In this embodiment the series choke 12 is connected from terminal 8 to an output terminal 14 of the series choke subcircuit; terminal 14 is a positive bus for the transistor output circuit. A diode 16 is provided in parallel with the choke 12, with its anode at terminal 14 and its cathode at terminal 8. Series choke subcircuits of several types are well known in the prior art. The invention involves this subcircuit in combination with other subcircuits.

(c) Snubber Subcircuit. The shunt snubber subcircuit 18 comprises a diode 20 whose anode is connected to bus 14 and whose cathode is connected to a junction 22. A resistor 24 is connected in parallel with the diode 20. The junction 22 is connected to a capacitor 26, whose second terminal is connected to the negative DC bus 4.

Main power semiconductors of this three-phase inverter are designated on FIG. 1 by reference numerals 36, 38, 40, 42, 44 and 46. The order in which they are numbered indicates their firing sequence during normal operation. The inverter can be a pulse-width modulated type that has notches in the conduction pattern of the main semiconductors.

In parallel with each power semiconductor is connected a diode; they are respectively designated 48, 50, 52, 54, 56 and 58. The collectors of the positive-connected power transistors 36, 40 and 44 and the cathodes of the diodes 48, 52, 56 are all connected to the positive bus 14. The emitters of the negative-connected transistors 38, 42, 46 and the anodes of diodes 50, 54, 58 are all connected to the negative DC bus 4.

The emitter of transistor 36, the collector of transistor 42, the anode of diode 48, and the cathode of diode 54 are all connected together and to an AC output terminal 60. Terminal 60 is the phase A terminal of the three-phase output of the inverter as a whole. Typically the inverter would provide single or three-phase power to an induction motor (not shown), but of course other types of loads can be served.

In a similar way the emitter of transistor 40, the collector of transistor 46, the anode of diode 52, and the cathode of diode 58 are connected to a terminal 62 which is the phase B output of the inverter. The emitter of transistor 44, the collector of transistor 38, the anode of diode 56, and the cathode of diode 50 are all connected to a terminal 64 which is the phase C output of the inverter.

CIRCUIT OPERATION An output short circuit can connect the inverter's positive bus 14 through a conducting positive-connected transistor 36,40,44 and a conducting negative-connected transistor 38,42,46 to the negative DC bus 4 shown occurring at time to in FIG. 2. The action of the combined protection subcircuits 10,18,28 during such a short circuit, for example a short from phase A terminal 60 to phase C terminal 64, is as follows.

An abnormal voltage from collector to emitter of a transistor such as transistor 44 is sensed by the control subcircuit 28. The fault is sensed at about time tl of FIG.

2, when the voltage has risen only as much as 5 or 10 volts.

Alternative ways of sensing a short circuit in other embodiments are to sense current in the transistor, in the DC bus, or in the output leads 60,62,64. The fault sensing circuit 28 produces a signal to cut off the base drive of the affected transistor 44. It accomplishes this preferably without any negative base drive, as described in the patent 4,651,252.

The snubber capacitor 26 discharges (in about 15 microseconds) through the snubber resistor 24 and through the short circuit. This time interval is shown on FIG. 2 as tl to t2. The series choke 12 holds off the DC supply voltage of terminal 8 from the DC bus terminal 14, keeping the high voltage off of the output transistors. Curve 70 shows the collector current, using a scale of amperes as percentage of the transistor rating to the left of FIG. 2. It rises to only about three times the transistor's current rating in about 25 microseconds, from to to t3. Its rate of rise is limited mainly by the choke 12.

After passage of a storage time to clear out charges in the output transistors, the current in the transistors falls, starting at about time t4, and continues to time t5.

At time t2 some of the current flowing in the choke 12 transfers from the transistors 44, etc., to the snubber capacitor 22, via the snubber diode 20. Curve 71 of FIG. 2 shows the voltage drop across the 5 ohm snubber resistor 24, using a scale of voltage shown at the right side of FIG. 2. A flat portion of the curve 71 from t2 to t5 is the time interval during which the capacitor 26 receives recharging current through diode 20; the small negative voltage represented by curve 71 in that interval is only the forward drop of the snubber diode 20.

During that same interval t2 - t5, the voltage on the snubber capacitor 26 rises at a rate proportional to the rate at which the snubber capacitor receives current. Because the diode 20 is conducting, the inverter bus voltage across buses 18,4, and the sum of voltages across the conducting transistors 44, etc. rises at that same rate. This is shown in'FIG. 2, where curve 68 shows the collector-to-emitter voltage of transistor 44 and any other transistor that may then be conducting in series with transistor 44. The right-hand voltage scale of FIG. 2 applies.

The voltage of transistor 44 is therefore rising in interval t3 to t5 as its current is falling. As a result of the interaction of the control subcircuit, choke subcircuit, and snubber subcircuit, the relative timing of the rise in the voltage of curve 68 and the decrease of current of curve 70 are such that the current 70 is significantly diminished from its highest value (at t3) by the time the voltage 68 has reached its highest value at t5. The transistor does not experience high current and high voltage simultaneously. Consequently the instantaneous power dissipation of the transistor is relatively low.

The collector-to-emitter voltage of transistor 44, curve 68, has a plateau starting shortly after t5; this is the bus 18 voltage. The plateau is reached after an overshoot of curve 68 near a point 74, during which the transistor voltage 68 rises above that which would correspond to the voltage at the DC bus 14. Parasitic inductance causes the overshoot, whose effect is visible also on curve 71. Shortly before time t5 the capacitor 26 starts conducting again through resistor24 for a short time, as shown by an upward step in curve 71 at that time.

SAFETY MARGIN With this invention the transistors 36, etc. are relatively safe during both the short circuit and the recovery interval that follows it. FIG. 3 illustrates this. The nominal safe operating area of the transistors 36, etc., is illustrated by the area under boundaries 78 of FIG. 3, for conditions of reverse bias of the the transistor. The collector-to-emitter voltage of a transistor is shown on the abscissa of the graph and its collector current is shown on the ordinate.

The nominal safe operating area is bounded at the top by a collector current of 100 amperes, and at the right (77) by a collector-to-emitter voltage of 1000 volts. The steady state current rating of this transistor is 50 amperes, i.e., half of the current boundary. A further restriction is a curvilinear portion 79 of curve 78 at the upper right of the graph, which is imposed by the maximum instantaneous power dissipation capability of the transistor. The amount of reverse base current has a slight effect on that curved portion but its effect is disregarded here for clarity.

Operating conditions that lie in the region to the lower left of this curve 78 are not likely to damage the transistor; those that lie above or to the right of it may cause damage.

However, although there is great risk of damage in exceeding the nominal safe operating region by excessive voltage (at the right side 77, 79, of the curve), there is very little risk of damage in exceeding it by excessive current (within specified limits) at low voltages for brief times.

The curve 76 of FIG. 3 is a time-sequential portrayal of the instantaneous collector current of the transistor 44 as a function of its instantaneous voltage from collector to emitter. The event represented by curve 76 is a turning off of transistor 44. The points in time on this curve 76 that correspond to the times of occurrences of the current peak 72 and the voltage peak 74 are marked as points t3 and t5 on FIG. 4.

Clearly, the instantaneous voltage of curve 76 remains well below the 850 volt to 1000 volt upper boundaries of the safe operating region, curve 78. The maximum current (130 amperes.) of curve 76 is only about 2.6 times the rated continuous current of 50 amperes. Three times the continuous current rating is acceptable for the time durations of this situation, which are affected by the prompt action of the sensing subcircuit 28. If the transistor drive is controlled, as in the cited patent, the overload time is shortened. Without the current limiting feature of the invention the current often rises to five or six times the continuous current rating of the transistor. The instantaneous power and the total energy dissipation represented by curve 76 are at safe levels.

The safe operating area rating of the transistor must still be sufficient to recover from normal commutation, that is from turning on while the opposite back diode is conducting and from turning off from transistor conduction. During these conditions the transistors can experience full bus voltage and up to rated current at the same time, but the normal commutation-induced levels are considerably lower than at short circuit recovery.

A side effect of the circuit is that for transient voltages on the inverter bus 14, the series choke 12 limits instantaneous energy to the output transistors while the inverter bus diode 16 provides an immediate return path to the bus capacitor 6.

COMPONENT REQUIREMENTS For proper operation of the invention attention must be paid to some guidelines in choosing the sizes of the components The snubber resistor 24 should be a non-inductive type whose initial short circuit surge discharge current, i.e., the maximum bus voltage divided by the snubber resistance value, is less than twice the transistor's current rating.

The snubber capacitor 26 should be such that the product of the snubber resistance 24 and the snubber capacitance 26 is less than one third of the minimum short circuit pulse time of 15 to 25 microseconds. This insures that the snubber capacitance 26 is substantially discharged at fault recovery time. The value of capacitor 26 in the embodiment described is 1 microfarad.

The snubber diode, in order properly to handle fault discharge current, should have a (25 microsecond) current capability of at least the maximum DC bus voltage divided by the parasitic resistance of the snubber capacitance 26.

The series choke 12 should have an inductance that is at least half of the maximum bus voltage at the time of a fault pulse times the pulse time divided by the current rating of a power transistor, in order to limit the fault current to less than 3 times the transistor's current rating. In the embodiment described above, the choke 12 has an inductance of 200 microhenrys.

The inverter bus diodes 48, etc., should be of a fast recovery type, (e.g., 0.75 microsecond), and be capable of handling continuously the transistor current rating and three times the transistor single-shot current rating. Moreover, the path from the inverter transistors' positive bus rail 18 through the diode 16 to the bus capacitor 6 and back from the negative terminal of capacitor 6 to the negative transistor bus rail 4 must be designed for minimum parasitic inductance.

It is also desirable to have minimum parasitic inductance in the path from the transistor bus rails 18, 4 through the snubber diode 20 and the snubber capacitor 26.

SUMMARY OF OPERATION The next few paragraphs are a brief recapitulation of the chronological operation of the invention. When a fault is sensed at time tl, the faulted transistors are biased off.

The choke 12 starts protecting the transistors from high voltage and limiting the rate of rise of current to enable capacitor 26 to discharge before transistor current becomes too great. The snubber capacitor 26, which has had bus voltage across it, is rapidly discharged during time interval tl to t2 to prepare it to accept current later. Consequently, in the later interval t2 to t5, capacitor 26 is able to and does accept current from choke 12 through the diode 20, thereby diminishing the amount of current that passes through the transistors during that crucial interval.

As charge accumulates on capacitor 26, increasing its voltage, the voltage on the transistors follows the voltage of capacitor 26 upward. By the time (t4), that the collector voltage has increased to about half of its bus voltage plateau, the collector current has diminished to about half of the maximum value that it had at time t3. Thus high voltage and high current do not occur at the same time in the transistors.

As a result of this sequence of events, curve 76 exceeds the current level of the safe operating area curve 78 by only about 30 percent, and only while the collector-to-emitter voltage is at very low voltage between 40 volts and 350 volts (only 5% to 40% of the permissible voltage). This is relatively conservative operation of the power semiconductors, which does not endanger them, and which is made possible by the interacting combination of the invented circuitry. The transistors are safe.

Representative values for the circuit components have been illustrated in the preferred embodiment. It should be recognized, however, that the invention can be practiced using other circuit configurations with other circuit components. It is intended that the invention include all such modifications and variations falling within the spirit or scope of the claims

Claims (11)

CLAIMS:

1. A combination of protective subcircuits for use in an inverter having at least one output semiconductor (44) for switchably connecting a DC power source having two DC terminals (2,4) with AC output terminals (60,62,64), said combination being provided to reduce the risk of damage to the semiconductor during a short circuit and recovery at the AC output terminals, comprising:: (a) a control subcircuit (28) having means connected for sensing the occurrence of a fault and producing a signal thereupon connected with said semiconductor (44) for switching said semiconductor to a non-conductive state; (b) an inductive subcircuit (10) having an inductance (12) and being connected in series intermediate a first terminal (2) of said DC power source and said output semiconductor, said inductive subcircuit comprising first means for rectifying current (16) connected in parallel with said inductance; and (c) a snubber subcircuit (18) connected to a point (14) intermediate said inductive subcircuit and said output semiconductor, and to the other DC bus (4), said snubber subcircuit comprising means (26) for providing capacitive action (26) and means (20, 24) for charging said capacitive means faster than discharging it.

2. A combination of protective subcircuits as in claim 1 and wherein said first rectification means comprises a rectifier connected to conduct when current flowing through said inductive subcircuit in the direction from the DC source to the power semiconductors diminishes; said means for charging faster than discharging is connected in series with said capacitance means and includes a parallel combination of second means (20) for rectifying current during charging and resistive means (24) for impeding current flow therethrough during discharging of said capacitance means.

3. A combination of protective subcircuits as in claim 1 and wherein said control subcircuit comprises means for sensing at least one of (a) the current in a DC bus (18) leading toward said semiconductor, (b) current in said semiconductor (44), (c) current at an output AC terminal; and (d) voltage across two terminals of said semiconductor (44); and wherein said sensing means for switching said semiconductor comprises circuit means for controlling at least one of the base voltage and base current of said semiconductor (44),

4. A combination of protective subcircuits as in claim 1 and wherein said capacitive means and said resistive means have a time constant less than one half of the minimum short circuit pulse time to insure that the capacitive means is discharged when the transistor current starts to rise at said recovery time.

5. A combination of protective subcircuits as in claim 1 and wherein said resistive means comprises a resistor (24) of value chosen such that an initial short circuit surge discharge current, i.e., the quotient of initial bus voltage divided by snubber resistor value, is less than twice the transistor's current rating.

6. A combination of protective subcircuits as in claim 1 and wherein said inductive circuit means comprises a choke having inductance at least as great as the quotient of maximum bus voltage (18-4) at the time of the fault divided by twice the current transistor rating times the fault pulse time, whereby the transistor current is maintained less than three times the transistor's current rating.

7. A method for protecting an inverter that has at least one output semiconductor (44) for switchably connecting a DC power source having two DC terminals (2,4) with AC output terminals, comprising the steps of: sensing (28) an occurrence of a short-circuit fault; biasing the output semiconductor (44) toward non-conduction; holding off some of the voltage of the DC source (2) from the semiconductor by dropping some voltage across a series-connected inductive circuit (10); providing a capacitive circuit (18) connected from the output (18) of the inductive circuit to the other DC terminal (2); substantially discharging the capacitive circuit (18) during a first time interval (tl - t2) starting upon the short circuit; and flowing current from said inductive circuit (10) into said capacitive circuit (18) during a subsequent time interval (t2 -t5) in which the voltage on the semiconductor is rising.

8. A method as in claim 7 and wherein said steps of providing a capacitive circuit and discharging the capacitive circuit comprise providing a capacitor (26) in series with a resistor (24) and discharging the capacitor through said resistor.

9. A method as in claim 8 and wherein said step of flowing current from said inductive circuit (10) into said capacitive circuit (18) comprises flowing it through a rectifier (20), in a forward-conducting direction, connected in parallel with said resistor (24), so as to prevent voltage drop through said resistor during said subsequent time interval (t2 -t5).

10. A combination of protective subcircuits for use in an inverter, substantially as hereinbefore described with reference to the accompanying drawings.

11. A method for protecting an inverter, substantially as hereinbefore described.