GB2221767A

GB2221767A - Bi-level resist etch process

Info

Publication number: GB2221767A
Application number: GB8818863A
Authority: GB
Inventors: Norman Frank Jackson; Brian Martin
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-08-09
Filing date: 1988-08-09
Publication date: 1990-02-14
Also published as: GB8818863D0

Abstract

A subtstrate is coated with a planarising layer (3) of masking material and with a layer (5) of photo-resist. Each layer (3, 5) is spun-coated and is baked to remove solvent; the first layer being baked at a high temperature (150-200 DEG C) to render the masking material (3) insensitive to silylation treatment. The second layer is baked at a lower temperature (90-140 DEG C). Following resist patterning, the substrate 1 and coating layers (3, 5) are exposed to a silylation reagent - e.g. a silane vapour and the patterned resist silylated preferentially. The exposed areas of layer (3) are then oxygen plasma etched but the silylated areas of resist layer are oxidised (9) and not etched. Layer (3) may be a photoresist. <IMAGE>

Description

BT-LEVEL RESIST ETCH PROCESS The present invention concerns integrated circuit lithographic etch processes, in particular, etch processes that employ two levels of resist for improved etch contrast and control for small geometry (1 micron, and submicron size) feature definition.

Hitherto, oxygen plasma erosion of the photoresist mask during etch processing has been a problem, this resulting in feature size enlargement and poor pattern transfer. Recently this problem has been addressed by incorporating silicon into the surface layers of the mask. During oxygen plasma etching this silicon rich material is converted to oxide. This converted material thereafter is highly resistant to further erosion and serves to mask underlying material during continued oxygen plasma etching.

One such alternative improved etching process is described for example in the following article: "The mechanism of the DESIRE Process" by Roland, B., et al., S.P.I.E. (1987) pages 69 to 76. In this known process a layer of photoresist is selectively exposed to light and thereafter silylated in the presence of an organo-silicon vapour reagent. This silylation is selective, silicon being taken up preferentially in the photochemically reacted, - i.e. exposed, region of the photoresist layer. However, due to some silylation occuring, albeit at a much reduced rate, and also as a result of diffusion, the contrast can be less than sharp and a preliminary back-etch is therefore often a requisite, to improve the profile prior to subsequent oxygen plasma etch. It is also a disadvantage that a special purpose photoresist is required, a resist that is not available as yet on a commercial scale.

The present invention provides an alternative process. It has been found, as will be discussed in detail hereinbelow, that resist silylation can be thermally differentiated, enabling the oxygen plasma erosion rates of the resist materials to be strongly contrasted A notable advantage of this effect is that it can be applied to commercially available conventional novolac-type positive resists and resins.

In accordance with the invention thus there is provided a bilevel resist etch process including the following steps: firstly, coating a substrate with a planarising layer of oxygen plasma erodable masking material, and thereafter baking the same at a relatively high temperature, this being a temperature that is sufficiently high to render the masking material essentially insensitive to silylation but not so high as to render the masking material insoluble in an appropriate solvent; secondly, coating the substrate and planarising layer with a layer of resist material, and thereafter baking at a relatively low temperature, this being a temperature that is sufficiently high to drive off solvent but not so high as to render the resist material insensitive to silylation; thirdly, exposing the resist material to patterned radiation and developing the same to define a structured mask;; fourthly, exposing the structured mask of resist material to a silylation reagent at a relatively low temperature, this being a temperature that is sufficiently high to promote silylation of the resist material but not so high as to cause the resist material to flow; and, fifthly, exposing the twice coated substrate to an oxygen plasma and conducting an anisotropic reactive ion etch to transfer mask pattern to the underlying masking material.

In the drawings accompanying this specification: Figure 1 is a schematic cross-section of semiconductor substrate coated with two levels of resist, the upper level thereof being patterned following exposure to radiation and development; Figure 2 is a schematic cross-section of the semiconductor substrate coated as in figure 1, showing the effect of silylation; and, Figure 3 is a schematic cross-section of the semiconductor substrate coated and silylated as in figure 2, following exposure to an oxygen plasma reactive ion etchant.

In order that the foregoing invention might be better understood, embodiments thereof will now be described and reference will be made to the accompanying drawings. The description that follows is given by way of example only.

The process to be described here is based upon a bilevel system (Figure 1) in which silylation, i.e. reaction with silicon, is determined by thermal pretreatment, i.e. the reaction is thermally differentiated. As shown in figure 1, a substrate wafer 1 has been provided with a spun-coated layer 3 of a masking material, baked, covered with a spun-coated layer 5 of a photoresist material, baked, exposed to light pattern and developed to define the mask structure shown. The bottom planarising layer 3, which may or may not be photosensitised, e.g.Mega 320D (a photoresist available from Spectrum Resists), RG-3900B (a resin available from Hitachi, Japan), is from 13clam in thickness and is baked at a relatively high temperature, e.g. 150-200 C. This temperature should be sufficiently high to render the resist material essentially insensitive to silylation, but not too high to cause subsequent solubility problems. The upper layer 5 is a standard photoresist (e.g. Mega 12, Mega 91C (both these photoresists are available from Spectrum Resists Inc), which is exposed and developed in the normal way, but baking is restricted to a relatively low temperature, e.g. 90-140 C.

On reaction with a suitable silicon compound, silicon is deposited in the surface 7 of the upper layer 5 only (Figure 2). When this structure is oxygen plasma etched, good pattern definition with a high aspect ratio profile is obtained (Figure 3). The silylated material 7 is converted to oxide 9.

Silylation may be accomplished with a low boiling organosilicon liquid of the type, hexamethyldisilazane (HMDS), vinyltriethyoxy silane (VTES), amino-propyltriethoxy silane (APTES), or trimethylsilyldimethylamine (TMSDMA). The substrate wafer 1 to be treated is placed in a vacuum chamber, and maintained at a temperature in the range 90-1400C. A small volume of the silane is introduced into the chamber for a reaction period ranging from 5180 minutes, as required. Typical etch rates are shown in Table 1.

TABLE 1 Etch Rates in Oxvgen Plasma Silylation performed in APTES or TMSDMA at 11 00C Treatment Etch Rate (um min-1) NON Mega 1.2 (1100C) 0.24 Mega 320D (110 C) 0.24 Mega 320D (200 C) 0.21 APTES: Mega 1.2 (1100C) 0.07 Mega 320D (2000C) 0.21 TMSDMA: Mega 1.2 (1100C) < 0.001 Mega 320D (2000C) 0.22 Note: Figures in brackets indicate baking temperatures.

In addition to the results tabulated, preliminary results have also been obtained for the photoresist material Mega 91C, a photoresist available from Spectrum Resists. This material, which is a high molecular weight polymer, exhibits excellent thermal stability. For this material, the silylation may be conducted at a higher temperature of 120-130 C (compare with Mega 1.2 at temperature 110 C), thereby offering the possibility of more efficient silylation with a consequent improvement in mask erosion hardness and pattern transfer.

Bilevel systems, based upon the schedules described, have exhibited ready removal of material from the lower layer 3 whilst leaving the upper layer 5 substantially intact.

Claims

What we claim is: 1. A bi-level resist etch process including the following steps: firstly, coating a substrate with a planarising layer of oxygen plasma erodable masking material, and thereafter baking the same at a relatively high temperature, this being a temperature that is sufficiently high to render the masking material essentially insensitive to silylation but not so high as to render the masking material insoluble in an appropriate solvent; secondly, coating the substrate and planarising layer with a layer of resist material, and thereafter baking at a relatively low temperature, this being a temperature that is sufficiently high to drive off solvent but not so high as to render the resist material insensitive to silylation; thirdly, exposing the resist material to patterned radiation and developing the same to define a structured mask;; fourthly, exposing the structured mask of resist material to a silylation reagent at a relatively low temperature, this being a temperature that is sufficiently high to promote silylation of the resist material but not so high as to cause the resist material to flow; and, fifthly, exposing the twice coated substrate to an oxygen plasma and conducting a plasma etch to transfer mask pattern to the underlying masking material.
2. A process, as claimed in claim 1, wherein silylation is performed in the vapour-phase of a low boiling point organo-silicon liquid.
3. A process, as claimed in claim 2, wherein the organo-silicon liquid is selected from one of the following: hexamethyldisilazane; vinyltriethoxy silane; amino-propyltriethoxy silane; or, trimethylsilyldimethylamine.
4. A process, as claimed in any one of the preceding claims, wherein the masking material and the resist-material are both materials of novolac type, the first being baked at a temperature of between 150 and 2000C, and, the second being baked at a temperature of between 90 and 140 C, silylation being conducted at a temperature of between 90 and l400C.
5. A process, as claimed in claim 1, when performed substantially as described hereinbefore with reference to and as shown in figures 1 to 3 of the drawings.