GB2218872A

GB2218872A - Overvoltage protectors

Info

Publication number: GB2218872A
Application number: GB8811883A
Authority: GB
Inventors: Derek Colman; Andrew Marshall; Mick John Maytum; Frank Raoul Fattori; Phil Cavanagh
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1988-05-19
Filing date: 1988-05-19
Publication date: 1989-11-22
Anticipated expiration: 2008-05-19
Also published as: GB8811883D0; GB2218872B

Abstract

An overvoltage protector includes a controllable impedance (1,2) connected to a first port (7,8) for receiving an applied voltage (Vapp) that, in the use of the overvoltage protector, is a supply voltage for components to be protected, and a control device (3) connected between a control terminal of the overvoltage protector and an impedance controlling electrode of the controllable impedance. The controllable impedance changes state abruptly from having a high to having a low impedance for applied voltages exceeding a transition voltage that is controlled by and varies in the same sense as a reference voltage applied to the control terminal, and the controllable impedance reverts abruptly from the low to the high impedance state when the flow of current at the first port falls below a holding current level for the overvoltage protector. <IMAGE>

Description

IMPROVEMENTS IN AND RELATING TO OVERVOLTAGE PROTECTORS The invention relates to overvoltage protectors.

Overvoltage protectors, known also as transient suppressors, are used to protect electrical components from damage by voltages that exceed one or more of the voltage limitations of the components and to which the components would be exposed, but for the presence of the overvoltage protectors, because of short-term disturbances or faults in a system to which the electrical components belong.

A common type of short-term disturbance in a system which includes electrical components is a very-short-term rise in the voltage on one of a pair of voltage supply lines for electrical components of the system. Such very-short-term voltage rises are known as transients and would cause considerable damage to electrical components of a system that did not include overvoltage protection.

One known overvoltage protector is a device which appears as a high impedance in response to applied voltages from zero to a breakdown voltage (its transition voltage) and which, in response to an applied voltage in excess of the transition voltage, appears as a very low impedance.

This known overvoltage protector is effective against transient voltage disturbances when the overvoltage protector is so positioned in a system subject to transient voltage distrubances as to appear as a low impedance load shunting a component or components of the system, in the presence of a transient voltage disturbance exceeding its transition voltage and to appear as a high impedance load at times when the voltage level is lower than its transition voltage.

An overvoltage protector may be used to protect components individually, but it is more economical to protect groups of electrical components by connecting overvoltage protectors, to the voltage supply ports of the electrical system, in which case each overvoltage protector is required to exhibit a high impedance when subjected to supply port voltages from zero to slightly more than the normal voltage for the supply port, and to exhibit a low impedance to voltages substantially in excess of the normal supply voltage for the port. A further requirement of an overvoltage protector is that, having been driven to its low impedance state by an applied voltage in excess of the normal voltage such as, for example, a transient voltage disturbance, it should revert to its high impedance state once the disturbance has died away.

Another requirement of an overvoltage protector is that it should change in impedance rapidly enough, when the voltage applied to it rises from a voltage below, to a voltage above, its transition voltage, to present a low impedance load to the source of the excess voltage before any component for which it is intended to provide protection could itself react to the voltage rise and be damaged by it.

The electrical components that respond most rapidly to supply voltage changes are semiconductor components and an overvoltage protector is required to respond rapidly enough to transient voltage disturbances to protect semiconductor components.

The increasing use of semiconductor components has resulted in their inclusion in systems such as telephone networks, which are especially subject to transient voltage disturbances caused by lightning strikes, for example, or which may include electromechanical components that generate transient voltage disturbances likely to damage semiconductor components belonging to the system.

An example of the use of semiconductor components in a system subject to transient voltage disturbances is the introduction of semiconductor integrated subscriber line interface circuits (SLIC) in telephone networks. The increased use of semiconductor components in those circumstances has resulted in increasing demands on overvoltage protectors used in the system.

A device meeting the requirements of an overvoltage protector is described in U.K. Patent No. 2,113,907. The device described in the patent is a single port semiconductor device that has respective high and low impedance states separated by a negative impedance state.

The device is switched from its high to its low impedance state by increasing the voltage applied to it to the voltage load at which its high impedance state meets its negative impedance state, at which point it traverses its negative impedance state to switch abruptly to its low impedance state. The device is returned to the high impedance state from the low impedance state (in which state its current is determined largely by the impedance of the circuit supplying the current) by reducing the current supplied to it to the current load at which its low impedance state meets its negative impedance. state, at which point it traverses its negative impedance state to switch abruptly to its high impedance state.The device therefore exhibits, in the high impedance state, a transition voltage beyond which there is a change to the low impedance state and, in the low impedance state, a holding current below which there is a change to the high impedance state.

The device described in U.K. Patent No. 2,113,907 is intended for operation connected between a pair of voltage supply lines for conveying electrical energy to a group of components also connected for operation between the voltage supply lines. The components are protected by the device, when it is connected between the voltage supply lines, by virtue of its connection in parallel with them and the ability of the device to act as a current shunt during transient voltage disturbances that drive it to its transition voltage. Recovery of the device to its high impedance state is effected by ensuring that its holding current is such as to exceed the current level available from the energy supply to the voltage supply lines.

All known overvoltage protectors, including the device described in U.K. Patent No. 2,113,907, have transition voltages that are fixed, which means that manufacturers of the known devices must provide a range of such devices to meet the needs of circuit designers and, inevitably, overvoltage protectors may not be available, or readily available, for some supply voltages.

It is an object of the invention to provide an overvoltage protector that is capable of alleviating possible difficulties as regards availability of devices for some supply voltages.

In accordance with the invention, an overvoltage protector includes a controllable impedance connected to a first port for receiving an applied voltage that, in the use of the overvoltage protector, is a supply voltage for components to be protected, and a control device connected between a control terminal of the overvoltage protector and an impedance controlling electrode of the controllable impedance, wherein the controllable impedance changes state abruptly from having a high to having a low impedance for applied voltages exceeding a transition voltage that is controlled by and varies in the same sense as a reference voltage applied to the control terminal, and the controllable impedance reverts abruptly from the low to the high impedance state when the flow of current at the first port falls below a holding current level for the overvoltage protector.

In use, the overvoltage protector switches rapidly from its high to its low impedance state on the arrival of a transient voltage disturbance that causes the applied voltage to rise to the transition voltage and switches rapidly back to its high impedance state once the transient voltage disturbance passes and the current available no longer exceeds the holding current for the overvoltage protector, the transition voltage being adjustable by means of the reference voltage in accordance with the needs of components connected in parallel with and requiring the protection provided by the overvoltage protector.

Preferably, the semiconductor overvoltage protector includes a switch device, connected to the first port, capable of switching abruptly between high and low impedance states at a transition voltage, and the control device is connected between the control terminal and a control electrode of the switch device.

In the preferred arrangement, the reference voltage is applied between the control terminal and a terminal of the first port that is not an impedance controlling electrode of the controllable impedance, and the transition voltage is substantially equal to the reference-voltage.

The switch device is advantageously a four-region PNPN device with a low efficiency charge-carrier injection region that provides a PNPN device with a high holding current, the outer P and N regions of the PNPN device constituting the first port of the overvoltage protector.

Preferably, the four-region PNPN device has one of its outer regions and the inner region adjacent to that outer region formed as respective layers each with a free major surface, and the other two regions of the four-region PNPN device are formed as respective P type and N type islands, one within the other, in the free major surface of the said inner region.

That one of the other two regions of the four-region PNPN device that is formed as the inner of the two island regions may be penetrated by projecting parts of the region formed as the outer of the island regions, which projecting parts extend to the electrical contacts for the inner of the two island regions to provide a low efficiency charge-carrier injection region.

When the switch device is a PNPN device, the control device preferably comprises a transistor so connected as to enable it to inject current into the inner P region of the PNPN device when the voltage applied at the first port exceeds the reference voltage.

Preferably, the control device comprises a bipolar transistor, and a resistor connected between the base electrode of the transistor and the control terminal of the overvoltage protector and preferably the transistor has a low-gain at low currents, in order to minimise the chances of temperature-dependent transistor currents influencing the overvoltage protector.

Preferably, the control device is formed in the said inner region of the four-region PNPN device, in which case the control device includes respective P type and N type regions formed as islands, one within the other, in the free major surface of the said inner region, and, in which case the said inner region functions as a third region of the control device.

In the arrangement where P type and N type regions of the control element are formed as islands, the control terminal of the overvoltage protector may be connected to the outer of the two island regions, and the two island regions may be so positioned, one relative to the other, that the bulk resistance of part of the outer island region lies between the control terminal of the overvoltage protector and the active part of the interface between the two regions. In that arrangement, the active part of the interface between the two regions is the active base region of the control element and the bulk resistance of part of the base region between the active region and the control terminal functions as a resistor connected between the control terminal and the active part of the transistor base region.

Preferably, in the arrangement where the P type and N type regions of the control element are formed as islands, one of the two island regions is a low efficiency charge-carrier injection region, that provides a bipolar transistor with low gain at low currents, and the inner island region may then be penetrated by projecting parts of the outer island region, which projecting parts extend to the electrical contacts for the inner of the two island regions, to provide a charge-carrier injection region with low efficiency at low currents.

Preferably, when the switch device is a PNPN device, a diode is connected to the first port of the overvoltage protector with such polarily that it is conductive for an applied voltage in the sense opposite to that of transition voltage for the overvoltage protector. The diode may be a PN diode connected to the four-region PNPN device, the P region of the diode being connected to the outer N region of the PNPN device, and the N region of the diode connected to the outer P region of the PNPN device.

Preferably, a first region of the PN diode is of the same conductivity and conductivity type as the said inner region of the four-region PNPN device and is connected to the outer region of the PNPN device that is formed as a layer, and the second region of the diode is connected to the other outer region of the four-region PNPN device.

Preferably, the first region of the PN diode is a part of the inner region of the four-region PNPN device enclosed by a barrier of conductivity type opposite to that of the inner region and connected to the outer region of the four-region PNPN device that is formed as a layer.

The switch may, instead of being a PNPN device, be a device with a lightly doped layer in which respective NPN and PNP transistors are formed, one of the transistors having a low gain at low currents and the transistors being so interconnected that they behave as provide a PNPN device with a high holding current, the respective emitter regions of the transistors being the first port of the overvoltage protector.

Preferably, the lightly doped layer serves as the collector region of a first of the transistors and the base region of the second of the transistors and, preferably, the first of the two transistors includes respective base and emitter regions formed as two islands, one within the other, in the lightly doped layer, that is formed as a transistor with "vertical" current flow.

The second of the two transistors may include an emitter region formed as an island and a collector region separated from the emitter region by the material of the lightly doped layer, that is, the transistor is a device with "lateral" current flow.

The emitter region of the first transistor may be penetrated by projecting parts of the base region of the transistor, which projecting parts extend to the electrical contacts for the emitter region, to provide a transistor with low gain at low currents.

When the switch is a device with a lightly doped layer, the control device advantageously comprises a transistor connected to inject current into the switch device and, preferably, the control device comprises a further bipolar transistor with a resistor connected between its base electrode and the control terminal of the overvoltage protector, the control device preferably being formed in the lightly doped layer.

The control device preferably includes respective P type and N type regions formed as islands, one within the other, in the lightly doped layer and, preferably, the outer of the two islands includes an elongate extension at the end of which is connected the control terminal of the overvoltage protector, the elongate extension functioning as the base resistor.

Preferably, the lightly doped layer functions as a third region of the control element.

The overvoltage protector may include a PN diode connected to the NPN and PNP transistors, the P type region of the diode being connected to the emitter region of the NPN transistor, and the N type region of the diode being connected to the emitter region of the PNP transistor.

Preferably, the PN diode comprises a region diffused deeply into the lightly doped layer, of conductivity type opposite to that of the lightly doped layer, and the other region of the diode is formed as an island in the deeply diffused region.

The overvoltage protector is, preferably, formed as a monolithic integrated circuit and a plurality of overvoltage protectors in accordance with the invention may be formed together as a monolithic integrated circuit.

Where, in each of the overvoltage protectors that are so formed together, the switch device is a PNPN device, the outer region formed as a layer may be common to all the devices. In the case of overvoltage protectors, in each of which the switch is a device with a lightly doped layer, the lightly doped layer may be common to all the devices.

The lightly doped layer may be an epitaxial layer.

The availability of an overvoltage protector with a control terminal permits the circuit designer to set the transition voltage for the device as dictated by the circuit condition whereas, previously, the circuit designer was required to choose from a range of standard overvoltage protectors with respective transition voltages, as set by the device designer, in attempting to provide overvoltage protection for in-circuit components.

Two forms of overvoltage protector in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a diagram of the circuit of the overvoltage protector; Figure 2 is a sectional representation of a first semiconductor integrated circuit form of the overvoltage protector of Figure 1; Figure 3 is a sectional representation of a second semiconductor integrated circuit form of the overvoltage protector of Figure 1; and Figure 4 is a part plan view of the surface of the semiconductor body in which the integrated circuit form, represented by Figure 2, is formed.

Referring to Figure 1 of the accompanying drawings, the overvoltage protector includes a bipolar PNP transistor 1, a first bipolar NPN transistor 2, a second bipolar NPN transistor 3, a resistor 4, and a PN junction diode 6. One end of the resistor 4 is connected to the base electrode of the second NPN transistor 3. The PNP transistor 1 and the first NPN transistor 2 are interconnected as a regenerative switch in which the collector electrode of the PNP transistor 1 is connected to the base electrode of the NPN transistor 2 and the collector electrode of the NPN transistor 2 is connected to the base electrode of the PNP transistor 1. The collector electrode of the second NPN transistor 3 is connected to the base electrode of the PNP transistor 1 and the emitter electrode of the second NPN transistor 3 is connected to the base electrode of the first NPN transistor 2.The anode electrode of the diode 6 is connected to the emitter electrode of the first NPN transistor 2 and the cathode electrode of the diode 6 is connected to the emitter electrode of the PNP transistor 1. The common connection of the anode electrode of the diode 6 and the emitter electrode of the first NPN transistor 2 is a first terminal 8 of the device and the common connection of the cathode electrode of the diode 6 and the emitter electrode of the PNP transistor 1 is a second terminal 7 of the device. A third terminal 5 of the device is provided by that end of the resistor 4 that is remote from the second NPN transistor 3. The terminal pair 5-8 provide a control port and the terminal pair 7-8 provide another port, of the device.

In the operation of the overvoltage protector represented by Figure 1, the device is connected by way its terminals 7 and 8 between a pair of electrical supply lines that provide a voltage Lapp, the sense of the connection being such as to make the terminal negative relative to the terminal 7. A reference voltage Vref applied between the terminal 7 and the control terminal 5 of the device is effective to set the applied voltage Vapp at which the first NPN transistor 2 and the second NPN transistor 3 will become conductive. The transistors 2 and 3 remain non-conductive so long as the condition Vref + Vbe2 +Vbe3 Vapp 0 holds, where Vbe2 and Vbe3 are the app forward breakdown voltages for the base-emitter junctions of 6 the transistors 2 and 3, respectively.Once the condition Vref + Vbe2 + Vbe3 Vapp O no longer holds, the transistors 2 app and 3 become conductive and the combination of the transistors 1 and 2 switch rapidly from their non-conductive :to their conductive states. Conditions capable of causing the switching on of the transistors 1, 2 and 3 includes transient voltage disturbances at the terminals 7 and 8 where the voltage Vapp is applied. Any current resulting from a transient overvoltage is routed through the overvoltage protector when the transient overvoltage causes the overvoltage protector to become conductive. The overvoltage protector, in effect, acts as a low impedance to the transient overvoltage and thereby suppresses it.

The voltage at which the overvoltage protector will switch on is dependent on the bias voltage applied between the terminals 5 and 7, and, therefore, the control terminal 5 is used to set the voltage at which the device will switch in response to a rise in the voltage applied to its terminals 7 and 8. The overvoltage protector is so constructed as to have a high holding current when in the low impedance state, that is, it is so constructed that the current available from the intended energy source cannot maintain it in its low impedance condition and it reverts to its high impedance condition once the excess energy provided by a transient overvoltage has been dissipated. The high holding current characteristic is achieved by making the first NPN transistor 2 a transistor with a low gain at low currents. The NPN transistor 3 may also be a device having a low gain at low currents in order to ensure that it does not inject excessive currents into the transistors 1 and 2 because of a rise in the operating temperature. The diode 6 suppresses transient overvoltages that would make the terminal 8 positive relative to the terminal 7.

Referring to Figure 1, it will be understood that although the operation of the overvoltage protector has been explained in terms of the functioning of transistors, the functions of the PNP transistor 1 and the NPN transistor 2 may be performed by a PNPN device.

Referring to Figure 1, the NPN transistor 3 is arranged to behave as a controllable current source and - the function of the NPN transistor 3 may be performed by other devices capable of acting as controllable current sources, for example, other forms of transistors.

Referring to Figure 2, the first semiconductor integrated circuit form of the overvoltage protector comprises a silicon body with a P+ type region 10 and an N type region, that are in the form of layers. The silicon body is bounded by a deep P+ type diffusion 100 which extends through both the P+ type region 10 and the N type region and also separates the N type region into two parts 11 and 61. The part 11 of the N type region accommodates, in its surface opposite the P+ region 10, first and second P type islands 40 and 12 which, in turn, accommodate respective N+ type islands 30 and 12. The type island 30 is not located centrally within the P type island 40 and lies near a part of the edge of the P type island 40. The N+ type island 20 is located centrally within the P type island 20.The part 61 of the N type region accommodates a P type island 60 at the surface remote from the P+ type region 10. The P type island 40 is provided with an electrical connector 50 positioned towards its edge and away from the N+ type island 30, the N type island 30 is joined to the P type island 12 by an electrical connector 90, the N+ type island 20 is joined to the P type island 60 by an electrical connector 80, the part 61 of the N region is joined to the P+ type diffusion 100 by an electrical connector 71, and the P type diffusion is provided with an electrical connector 72 at its surface common with that of the P+ type region 10.

The N+ type island 30 has shorting dots 130 which are projecting parts of the P type material, belonging to the P type island 40, which extend through to the electrical connector 90. The N+ type island 20 has shorting dots 120 which are projecting parts of the P type material of the P type island 12 which extend through to the electrical connector 80. The N type region is covered by a silicon dioxide layer 13 which is penetrated only by the connectors 50, 71, 80 and 90.

Referring to Figures 1 and 2, the electrical connector 50 of Figure 2 corresponds to the terminal 5 of Figure 1, the bulk resistance of the P type island 40 between the contact 50 and the N+ type island 30, of Figure 2, corresponds to the resistor 4 of Figure 1, the electrical connector 80 of Figure 2 corresponds to the terminal 8 of Figure 1, the electrical connector 71 of Figure 2 corresponds to the terminal 7 of Figure 1, and the electrical connector 72 of Figure 2 is an alternative to the connector 71. In respect of the devices shown in Figure 1, the regions 30, 40 and 11 of Figure 2 provide the NPN transistor 3, the regions 10, 22, 12 and 20 of Figure 2 provide the transistors 1 and 2, and the regions 60 and 61 of Figure 2 provide the PN junction diode .6.

Referring to Figure 2, the regions 10, 11, 12 and 20 form a four-layer (PNPN) structure in which the P type layer 12 and the N type layer 20 are fabricated with curved boundaries, as islands, and in which the N and P regions of an NPN transistor and its base resistor are fabricated as the additional islands 40 and 30.

Also, the inner N region of the four-layer (PNPN) structure is divided into two parts by the deep P+ isolating diffusion 100 to permit the fabrication of the PN junction diode 60-61 in the layer structure. The formation of the isolating diffusion 100 does not require additional process steps. The process steps involved in arriving at the structure represented by Figure 2 are standard four-layer (PNPN) device steps with the incorporation of extra diffusion windows in masks for the NPN transistor, the transistor base resistor, and the diode.All the fabrication steps are well understood and are cheap and, in addition, the device is of relatively small area compared with alternative processes for producing a four-layer overvoltage protector, giving advantages not only in terms of minimising the amount of semiconductor material needed but also permitting the use of small packages which are available in a wider range of shapes than large packages.

The integrated circuit overvoltage protector represented by Figure 2 includes the electrical connectors 71 and 72 as alternative electrical terminals.

In the case where the electrical connector 72 is used as an electrical terminal, electrical contact may be made along the surface of the P+ type region 10, and, since adjacent devices on a wafer will also have the surface of the type region 10 as an electrical terminal, overvoltage protectors comprising two adjacent devices, or more than two adjacent devices, may be provided together as a chip with the electrical terminal provided by the connector 72 as a terminal shared by the devices.

Referring to Figure 3, the second semiconductor integrated circuit form of the overvoltage protector comprises an N+ type substrate region 301 adjacent to which is an N type region 302, both regions being formed as layers. The N type region 302 may be an epitaxial region.

A ring 303 of P type material surrounding, and separated from, a P type island 304, is accommodated by the N type region 302 in its surface remote from the substrate region 301. Next to the P type ring 303, and in the same surface of the N type region 302 as that occupied by the ring 303, a P type island 305 in the central region of which there is an N type island 306 is accommodated by the N type region 302.

Next to the P type island, and, again, in the same surface of the N type region 302 as that at which the ring 303 lies, there are, accommodated by the N type region 302, a P type island 307 in the central region of which there is an N type island 3081and a further P type island 309 which abuts the P type island 307. There is, next to the P type island 309., a deep P type region 310 extending into the N type region 302 and an N type island 311 in the surface of the P type region 310. The P region 310 extends only partly across the N type region 302. An electrical connector 312 contacts the P type island 309 at its edge remote from the P type island 307, an electical connector 313 contacts the P type deep region 310 and the N type island 306, and an electrical connector 314 contacts the P type island 304 and the N type island 311.

The N type island 306 has shorting dots 1305 which are projecting parts of P type material, belonging to the P type island 305, which extend through to the electrical connector 313. The N type region 302 is covered by a layer 316 of silicon dioxide which is penetrated only by the connectors 312, 313, 314 and 315.

Referring to Figures 1 and 3, the connector 312 of Figure 3 corresponds to the terminal 5 of Figure 1, the bulk resistance of the P type region 309 of Figure 3 corresponds to the resistor 4 of Figure 1, the connector 313 of Figure 3 corresponds to the terminal 8 of Figure 1, and the connector 314 of Figure 3 corresponds to the terminal 7 of Figure 1. In respect of the devices shown in Figure 1, the regions 307, 308 and 302 of Figure 3 provide the NPN transistor 3, the regions 302, 205, and 306 of Figure 3 provide the NPN transistor 2, the regions 303, 304 and 302 provide the PNP transistor 1, and the regions 310 and 311 of Figure 3 provide the PN junction diode 6. The N+ layer 301 is effective as an electrical connection between the collector electrode of the NPN transistor 302-305-306 and the base electrode of the PNP transistor 302-303-304.

Referring to Figure 3, the integrated circuit structure is a three layer structure as used in the fabrication of planar power transistors. The transistors provided by the regions 302-305-306 and the regions 307-308-302 are conventional planar transistors known in the art as vertical transistors. The transistor provided by the regions 302-303-304 is known in the art as a lateral transistor. The presence of the deep P type region 310 for the PN junction diode serves a dual purpose, that of providing a diode with a reverse breakdown voltage appropriate to the function of the overvoltage protector and also of preventing transistor action with the adjacent N region 302.The type region 301 is not an external node of the integrated circuit (which it would be in a conventional planar integrated circuit) and the integrated circuit may be housed in packages not providing the conventional back-contact of planar-power integrated circuits.

Planar power transistor processes are very low cost processes requiring relaxed tolerances compared with integrated circuit processes and, consequently, the integrated circuit described is made at low cost.

Referring to Figure 3, overvoltage protectors comprising two adjacent devices, or more than two adjacent devices, may be provided together as a chip with a common connector 314. In such a double, or multiple, arrangement the N+ region 301 will be common to the devices, this common connection representing connection together of the base electrodes of the PNP transistor 1 of Figure l. A result of the presence of the common connection is that all the devices will become activated whenever any one of the devices is activated. The region 301 may include a metallised surface to reduce its resistance.

The integrated circuit arrangements represented by Figures 2 and 3, respectively, are alternative integrated circuit forms of the overvoltage protector represented by Figure 1. The integrated circuit form represented by Figure 2 is based on four-layer device processes whereas the integrated circuit form represented by Figure 3 is based on three-layer device processes. As is known in the art, three-layer device that provide an epitaxial layer processes/yield faster devices than four-layer device ,these being non-epitaxial-layer processes.

processes,/ In each case, shorting dots are included in the switch device to provide an overvoltage protector with the high holding current necessary for its function, and the input control transistor may also have shorting dots in each case, in order to prevent device activation by the higher leakage currents which occur at high temperatures.

Referring to Figure 4, the lateral PNP transistor 302-303-304 has concentric emitter and collector regions while the other, vertical structure, components have rectangular electrode regions, all formed by diffusions into the surface of the N region 302. The lateral PNP transistor 302-303-304 may have regions of other shapes (rectangular, hexagonol, etc.) and the vertical structure may have electrodes of shapes other than a rectangle. The shorting dots 1305 are evident in the regions 306 of the vertical NPN transistor 302-305-306.

Claims

Claims:

1. A semiconductor overvoltage protector including a controllable impedance connected to a first port for receiving an applied voltage that, in the use of the overvoltage protector, is a supply voltage for components to be protected, and a control device connected between a control terminal of the overvoltage protector and an impedance controlling electrode of the controllable impedance, wherein the controllable impedance changes state abruptly from having a high to having a low impedance for applied voltages exceeding a transition voltage that is controlled by and varies in the same sense as a reference voltage applied to the control terminal, and the controllable impedance reverts abruptly from the low to the high impedance state when the flow of current at the first port falls below a holding current level for the overvoltage protector.

2. A semiconductor overvoltage protector as claimed in claim 1, including a switch device, connected to the first port, capable of switching abruptly between respective high and low impedance states at a transition voltage, wherein the control device is connected between the control terminal and a control electrode of the switch device.

3. A semiconductor voltage protector as claimed in claim 2, wherein the switch device is a four-region PNPN device with a low efficiency charge-carrier injection region that provides a PNPN device with a high holding current, the respective outer P and N regions of the PNPN device being the first port of the overvoltage protector.

4. A semiconductor overvoltage protector as claimed in claim 3, wherein the four-region PNPN device has one of its outer regions and the inner region adjacent to that outer region formed as respective layers each with a free major surface, and the other two regions of the four-region PNPN device are formed as respective P type and N type islands, one within the other, in the free major surface of the said inner region.

5. A semiconductor overvoltage protector as claimed in claim 4, wherein that one of the other two regions, of the four-region PNPN device, that is formed as the inner of the two island regions is penetrated by projecting parts of the region formed as the outer of the two island regions, which projecting parts extend to the electrical contacts for the inner of the two island regions, thereby to provide a low efficiency charge-carrier injection region.

6. A semiconductor overvoltage protector as claimed in any one of claims 2 to 5, wherein the control device comprises a transistor so connected as to enable it to inject current into the control electrode of the switch device when the voltage applied at the first port exceeds the reference voltage.

7. A semiconductor protector as claimed in claim 6, wherein the control device comprises a bipolar transistor, and a resistor connected between the base electrode of the transistor and the control terminal.

8. A semiconductor overvoltage protector as claimed in claim 6 or claim 7, wherein the transistor is a transistor with low gain at low currents.

9. A semiconductor overvoltage protector as claimed in any one of claims 4 to 8, wherein the control device is formed in the said inner region of the four-region PNPN device.

10. A semiconductor overvoltage protector as claimed in claim 9, wherein the control device includes respective P type and N type regions formed as islands, one within the other, in the free major surface of the said inner region.

11. A semiconductor overvoltage protector as claimed in claim 10, wherein the said inner region functions as a third region of the control device.

12. A semiconductor overvoltage protector as claimed in claim 10 or claim 11, wherein the control terminal of the overvoltage "protector is connected to the outer of the two island regions of the control device, and the two island regions are so positioned, one relative to the other, that the bulk resistance of a part of the outer island region lies between the control terminal of the overvoltage protector and the active part of the interface between the two regions.

13. A semiconductor overvoltage protector as claimed in any one of claims 9 to 12, wherein one of the two island regions of the control device is a charge-carrier injection region that provides a low-gain bipolar transistor at low currents.

14. A semiconductor overvoltage protector as claimed in claim 13, wherein the inner island region of the control device is penetrated by projecting parts of the outer island region of the control device, which projecting parts extend to the electrical contacts for the inner of the two island regions, thereby to provide a charge-carrier injection region of low efficiency at low currents.

15. A semiconductor overvoltage protector as claimed in claim 1 or claim 2, wherein a diode is connected to the first port of the overvoltage protector with polarity such as to be conductive for an applied voltage in the sense opposite to that of the transition voltage for the overvoltage protector.

16. A semiconductor overvoltage protector as claimed in any one of claims 3 to 14, wherein a PN diode is connected to the four-region PNPN device, the P region of the diode being connected to the outer N region of the PNPN device, and the N region of the diode being connected to the outer P region of the PNPN device.

17. A semiconductor overvoltage protector as claimed in any one of claims 4 to 14, wherein a PN diode is connected to the four-region PNPN device, a first region of the diode being of the same conductivity and conductivity type as the said inner region of the four-region PNPN device and connected to the outer region of the PNPN device that is formed as a layer, and the second region of the diode being connected to the other outer region of the four-region PNPN device.

18. A semiconductor overvoltage protector as claimed in claim 17, wherein the-~first region of the PN diode is a part of the inner region of the four-region PNPN device enclosed by a barrier of conductivity type opposite to that of the inner region and connected to the outer region of the four-region PNPN device that is formed as a layer.

19. A semiconductor overvoltage protector substantially as herein described with reference to, and as shown in, Figure 1, of the accompanying drawings.

20. A semiconductor overvoltage protector substantially as herein described with reference to, and as shown in, Figure 2 of the accompanying drawings.

21. A semiconductor overvoltage protector as claimed in claim 2, wherein the switch device includes a lightly doped layer in which respective NPN and PNP transistors are formed, one of the transistors having low gain at low currents and the transistors being interconnected to provide a PNPN device with a high holding current, the respective emitter regions of the transistors being the first port of the overvoltage protector.

22. A semiconductor overvoltage protector as claimed in claim 21, wherein the lightly doped layer serves as the collector region of a first of the transistors and the base region of the second of the two transistors.

23. A semiconductor overvoltage protector as claimed in claim 22, wherein the first of the two transistors includes respective base and emitter regions formed as two islands, one within the other, in the lightly doped layer.

24. A semiconductor overvoltage protector as claimed in claim 22 or claim 23, wherein the second of the two transistors includes an emitter region formed as an island and a collector region separated from the emitter region by the material of the lightly doped layer.

25. A semiconductor overvoltage protector as claimed in claim 23 or claim 24, wherein the emitter region of the first transistor is penetrated by projecting parts of the base region of the transistor, which projecting parts extend to the electrical contacts for the inner of the two island regions, thereby to provide a low-gain transistor.

26. A semiconductor overvoltage protector as claimed in any one of claims 21 to 25, wherein the control device comprises a transistor so connected as to enable it to inject current into the control electrode of the switch device, when the voltage applied at the first port exceeds the reference voltage.

27. A semiconductor overvoltage protector as claimed in claim 26, wherein the control device comprises a bipolar transistor, and a resistor connected between the base electrode of the transistor and the control terminal of the overvoltage protector.

28. A semiconductor overvoltage protector as claimed in claim 27, wherein the control device is formed in the lightly doped layer.

29. A semiconductor overvoltage protector as claimed in claim 28, wherein the control device includes respective P type and N type regions formed as islands, one within the other, in the lightly doped layer.

30. A semiconductor overvoltage protector as claimed in claim 29, wherein the outer of the two islands includes an elongate extension at the end of which is connected one terminal of the second port of the overvoltage protector, the elongate extension functioning as the base resistor.

31. A semiconductor overvoltage protector as claimed in any one of claims 28 to 30, wherein the lightly doped layer functions as a third region of the control device.

32. A semiconductor overvoltage protector as claimed in any one of claims 21 to 31, wherein a PN diode is connected to the NPN and the PNP transistors, the P type region of the diode being connected to the emitter region of the NPN transistor, and the N type region of the diode is connected to the emitter region of the PNP transistor.

33. A semiconductor overvoltage protector as claimed in claim 32, wherein the PN diode comprises a region diffused deeply into the lightly doped layer, of conductivity type opposite to that of the lightly doped layer, and the other region of the diode is formed as an island in the deeply diffused region.

34. A semiconductor overvoltage protector substantially as herein described with reference to, and as shown in, Figure 3 of the accompanying drawings.

35. A semiconductor overvoltage protector as claimed in any one of the preceding claims in the form of a monolithic integrated circuit.

36. A monolithic integrated circuit comprising a plurality of overvoltage protectors as claimed in any one of claims 1 to 35.