GB2216662A

GB2216662A - Detecting heartbeats

Info

Publication number: GB2216662A
Application number: GB8804917A
Authority: GB
Inventors: Edmund Sydney Smith; John Davies
Original assignee: Densa Ltd
Current assignee: Densa Ltd
Priority date: 1988-03-02
Filing date: 1988-03-02
Publication date: 1989-10-11
Also published as: GB8804917D0

Abstract

A heartbeat monitor (e.g. of the transthoracic impedance type) comprises: (a) a plurality of inputs for electrodes positioned on the patient's abdomen; (b) an operational amplifier for amplifying the input signal Vm; (c) a full wave rectification circuit 44 and 45 to reduce the effect of unwanted signal pick up from the electricity supply frequency on the ouput of the operational amplifier and to deliver a DC signal V7 whose magnitude is dependent on the unwanted signal element and on which there is superimposed the wanted signal indicative of the patient's heart beats, and (d) counting and display means arranged to display parameters associated with the heart rate of the patient. The apparatus may include alarms activated in the event of the heart rate exceeding a pre-determined upper limit or falling below a predetermined lower limit, or the heart rate suffering a 20% reduction over a 30 second period. <IMAGE>

Description

MEDICAL APPARATUS This invention relates to medical apparatus which consists of, or incorporates, a heart beat detection system based on a transthoracic impedance technique.

More particularly, the invention provides medical monitoring apparatus comprising means for detecting and displaying data relating to a patient's heart rate, wherein said heart rate monitoring means comprises: (a) a plurality of inputs for electrodes which, in use, are positioned on the patient's abdomen; (b) an operational amplifier for amplifying the signal fed to said inputs by the electrodes; (c) a full wave rectification circuit arranged to act upon the output of the operational amplifier so as to reduce the effect of unwanted signal pick up from the electricity supply frequency and to deliver a DC signal whose magnitude is dependent on the unwanted signal element and on which there is superimposed the wanted signal indicative of the patient's heart rate; and (d) counting and display circuits and display means arranged to display parameters associated with the heart rate of the patient.

Advantageously, the alarm is both visual and audible. If, on having raised the alarm, the monitoring circuit then detects a heart beat, the audible alarm may be cancelled but the visual alarm continued for a predetermined period. If heart function does not recommence, both audible and visual alarms preferably continue until reset by an investigating person.

Preferably, the monitoring circuit includes a level detector which is adapted to detect changes in the prevailing output level of the sensor, irrespective of what the prevailing output level might be. For this purpose, the level detector comprises a comparator, the reference level of which is preferably provided by a square wave signal supplied by an oscillator.

Preferably, the level detector includes two series connected comparators, the first comparator receiving at its one input the voltage output of the sensor and at its other (a) the integrated output of the sensor and (b) said square wave signal, the output of the first comparator being coupled to the input of the second comparator by way of a diode pumping circuit and a parallel capacitor, the other input of the second comparator being provided with a fixed reference level, whereby when the sensor output remains constant an oscillating output is obtained from the first comparator which charges said parallel capacitor and holds the second comparator in one switching state, but when a change in sensor output occurs a steady signal is temporarily obtained from the first comparator which causes the voltage on the parallel capacitor to decay and the second comparator to change switching states, thereby indicating that heart function has occurred.

In one preferred embodiment, the sensor is arranged to count and to display the heart rate of a patient. A display of beats/min is preferably provided which is updated every 30 secs.

An alarm is raised if the beat rate drops below a pre-settable value (say 40 beats/min) or if it rises above a pre-settable value (say 180 beats/min for an adult or 240 for an infant).

On raising an alarm the display is preferably latched so that the offending rate is held on the display, until reset by the operator.

Details of the operation of this heart rate monitor will be given hereinafter with reference to the accompanying drawings.

The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings, wherein: Figure 1 is a block circuit diagram showing part of the circuitry in one embodiment of a heart monitor in accordance with the present invention; Figure 2 shows a detail of the circuit diagram of Figure 1; Figures 3a and 3b are diagrammatic graphs for use in explaining the operation of the portion of the circuit shown in Figure 2; Figure 4 shows a block circuit diagram of a heart rate count/display circuit of this invention; Figure 5 shows the basic first stage amplification circuit used in a heart monitor; Figure 6 shows a typical signal from the output of the amplification circuit of Figure 5; Figure 7 shows in block form an averaging circuit of this invention; Figure 8 shows part of a circuit for generating a high heart rate alarm;; Figure 9 shows part of a circuit for generating a low heart rate alarm; and Figure 10 shows a circuit for detecting a decelerating heart rate.

With reference first to Figure 1, the monitor uses a sensor 1 which is attached to a patient's body to generate electrical signals responsive to the heart beat of the patient, and transmits an electrical signal to monitoring electronics. The latter part of the system can be located at a position remote from the sensor 1.

The sensor signal is applied to a level detector 2 which, as described further hereinafter with reference to Figures 2 and 3, is provided with a floating reference level by means of an oscillator 10. The output of the level detector forms one input of a NAND gate 3 whose other input is connected to a fixed supply voltage VDD. The output NAND gate 3 is connected to the control input of an electronic timer 4 and also the trigger input of a monostable 8.

The output of the NAND gate 3 is normally low and this is arranged to cause the timer 4 to time out. As explained further hereinafter, each time a heart beat action is sensed by the level detector 2, the output of the NAND gate 3 is caused to go high so resetting the timer and initiating another timing period. Each time the output of NAND gate 3 goes high, the monostable 8 is triggered. This is arranged to produce an audible "click" from an electronic sounder 9, together with a flash of green light from a green LED 12. The purpose of the click and flash is to indicate to a person monitoring the alarm that heart action is taking place and that the electronics is functioning.

If heart function fails and the timer 4 times out, then the alarm is raised by the timer energizing a buzzer 14. At the same time a latch 5 is set which causes a red LED 15 to flash. If then heart function should recommence, the audible alarm 14 is stopped as a result of the timer being reset. At the same time, the output of a further NAND gate 6 is arranged to go low to cause a further timer 7 to time out. Oh timing out, for example after one minute, the output of the timer 7 resets the latch 5 so turning off the red flashing indicator 15. Thus, even though heart functionrecommences, the red indicator 15 flashes for a period of one minute to indicate to the person monitoring the alarm that a break in normal heart function has occurred.

The structure and operation of the level detector 2 are now described in more detail with reference to Figures 2 and 3.

The sensor signal Vin is applied to the noninverting input (+) of an operational amplifier comparator 21 by way of a resistor R1 and to the inverting input (-0) by way of the series combination of two resistors R2 and R3. The junction of the resistors R2 and R3 is coupled to the Ov line 23 by way of a capacitor C1.

The inverting input of comparator 21 is also connected to the 0v line by way of the series combination of a capacitor C2 and a variable resistor Rvl. A square wave derived from the oscillator 10 is injected at the junction of the capacitor C2 and variable resistor Rvl by way of a resistor R4 The output of the comparator 21 is led to the noninverting input of a second operational amplifier comparator 22 by way of the series combination of a capacitor C3 and a diode D1. The junction of the capacitor C3 and the diode D1 is coupled to the 0v line by way of a diode D2. The non-inverting input of the comparator 22 is connected to the 0v line by way of the parallel combination of a capacitor C4 and a resistor R5. The inverting input of a comparator 22 is provided with a d.c. reference level Vre by means of a variable resistor RV2 connected across the supply voltage. The output of the comparator 22 provides the output of the level detector coupled to the NAND gate 3, in accordance with Figure 1.

In operation, in order to prevent the timer 4 timing out, the output of comparator 22 must be arranged to go low each time a heart beat occurs. For the output of comparator 2 to go low, the voltage Vout at its non-inverting input must drop below Vre. This is achieved as follows: The input voltage Vin applied to the comparator 21 is the amplified output of the sensor 1 (i.e. the output from the circuit illustrated in Figs. 5 and 7).

This voltage Vin can be at any value (within the linear range of the sensor output) depending on the degree of compression of the sensing diaphragm. However, a heart beat will always result in at least a small change in Vin.

It will be appreciated that a conventional comparator arrangement cannot be used to detect such changes since such an arrangement would normally use a fixed reference against which the input voltage Vin would have to be compared. To overcome this problem, the present circuit provides a reference which floats with the prevailing level of Vin, the magnitude of the reference being set by RV1.

The floating reference is achieved by use of the square wave applied across the potential divider formed by R4 and RV1. The capacitor C2 decouples the voltage across RV1 and impresses it upon the voltage appearing at the inverting input of the comparator 21. If Vin is constant (i.e. no heart function is occurring), the voltage applied to the inverting and non-inverting inputs of comparator 21 would be the same (ignoring for the moment the impressed voltage coupled by C2). Under these conditions, when the impressed voltage is taken into account, the output of comparator 21 switches at the oscillator frequency as the voltage at the inverting terminal swings above and below the voltage at the non-inverting terminal. This situation is illustrated in Figure 3a.

The components C3, D1, D2, act as a so-called diode pump circuit serving to charge capacitor C4. It will be appreciated that, providing the output of comparator 21 continues to oscillate, the voltage Vout across the capacitor C4 will be maintained. However, if the output of comparator stops oscillating and is either permanently high or low, then the voltage Vout across C4 will disappear (reduce to zero).

Now Vin changes each time a heart beat takes place. The voltage at the non-inverting terminal of comparator 21 follow Vin instantly, whereas the voltage at the inverting terminal does not, due to capacitor C1 charging or discharging. The effect is illustrated in Figure 3b for an imagined step change in Vin.

Referring to Figure 3b, over the period T, the voltage at the non-inverting terminal always exceeds that at the inverting terminal, so that the output of comparator 21 is permanently high for this period.

Since no pumping voltage is applied to the circuit C3, D1, D2, the voltage Vout decays to zero. As soon as Vout falls below Vre, the output of comparator 22 is caused to switch to its low value, signifying that a heart beat has taken place.

It was assumed above that the change in Vin was a step rise. It will be appreciated that a step fall in Vin would cause the output of comparator 21 to go low but again Vout would decay to zero, signifying heart function.

The sensitivity of the comparator 21 is set by the voltage appearing across RV1. In practice this can be set to a relatively low level e.g. 10 mv peak.

Thus, whatever the direction and magnitude of the change in Vin (above a threshold magnitude), the circuit will detect such changes as being the result of the heart beating and will react accordingly to prevent the timer 4 from timing out.

The monitoring electronics can be housed in any suitable manner. One convenient arrangement is for the monitoring electronics to be housed in a small handheld plastics box. Such a monitor may be powered by batteries, for example four 1.5 volt dry batteries disposed in the box, and is therefore inherently safe. A low voltage indicator can be incorporated to warn when batteries need changing.

Referring next to Figure 4, a circuit is shown which serves to count and display the heart rate of a patient. In normal operation, the circuit has two rate limits arranged such that: Low Rate < Heart Rate < High Rate Limit When the low rate count has been exceeded (in less than 30 secs), a first monostable 31 is triggered which sets a first latch 32. Latch 32 being set prevents a first Timer 33 from timing out, so that the Timer 33 output is held high and a second, alarm latch 37 is held reset.

Also for normal operation the high rate count will not be exceeded so that a second Timer 34 times out before the 'high rate limit in counter 35 goes high.

This ensures that the output of a NAND gate 36 stays high and again the alarm latch 37 is not set.

Timer 34 times out after 30 secs. In timing out, it: 1. Latches the current count into display drivers 38 and 39; 2. Triggers a second monostable 40 which resets the counter 35 to zero; and 3. Reset itself via reset circuitry 41.

The whole process then repeats.

Low Rate Alarm Condition In this case the low rate count is not exceeded within the 30 second time period.

Timer 33 and Timer 34 both time out together.

When Timer 33 times out it: 1. Sets latch 37 which raises the alarm; and 2. Latch 37 in turn sets a third latch 42 which stops the heart beat pulses being fed to the counter.

When Timer 34 times out it: 1. Latches the current count into the display drivers 38 and 39.

This count will then be held displayed until the alarm has been accepted and the reset button pushed.

High Rate Alarm Condition In this case Timer 38 is reset early in the 30 second period, and this has the same effects as described above in relation to normal heart beat operation. However, the 'high rate output' from the counter 35 goes high before Timer 34 times out. This makes the output of NAND gate 36 go low which sets latch 37 and raises the alarm. However, the counter 35 is allowed to continue to count till the end of the 30 second period so that the true high heart rate will be latched into the display.

Timer 34 output will remain high to the end of the 30 second period. This prevents latch 42 from being set (via OR gate 43) so that the counter 35 continues to count. At the end of the 30 second period the count will be latched into the display, and the counter stopped.

Referring now to Fig. 5, the first stage amplifier is a triple op-amp instrumentation amplifier (this being a common and well-established technique). This arrangement ensures that any 50 Hz (or 60 Hz in the U.S.A.) signal which is picked up as a common mode signal by the body electrodes is reduced.

It is usual to follow this first stage amplifier by a notch rejection filter to further reduce the 50 Hz (60 Hz) pick-up, before further amplification of the heart rate signal takes place. Notch filters are difficult to design requiring tight tolerance components and fine tuning during manufacture.

An alternative method is presented in accordance with this invention which method requires no tuning and no specially selected components.

The signal leaving the first stage amplifier (see Fig. 6) comprises the heart beat signal buried in 50 Hz or 60 Hz pick-up signal which may be several magnitudes larger than the desired signal. The signal passes through an averager (described below with reference to Fig. 7) which has as its output a dc signal the magnitude of which depends directly on the magnitude of the 50 Hz or 60 Hz pick-up signal.

The heart beat signal then appears as a disturbance to this d.c. level so that in effect the rolls of the signals have been reversed.

The detection of the heart beat signals (for counting purposes) is then accomplished by the detection circuitry as described hereinabove with reference to Figs. 1 - 3 and 4.

Referring next to Fig. 7, an averager circuit is shown the purpose of which is to replace the conventional notch filter in a heart rate monitor.

Amplifiers 44 and 45 form a full wave rectifier, such that the voltage V7 at the output of amplifier 45 is a full wave rectified version of Vin. This output voltage V7 is smoothed by the resistor capacitor combination R2C2, and then further amplified by amplifier 46. The output voltage V14 of amplifier 46 will now be a dc voltage with a ripple frequency twice that of the pick-up signal i.e. 100 Hz (UK) or 120 Hz (USA).

Although the ripple at this point may still be comparable in magnitude to the heart beat signal we are trying to detect, if now the voltage V14 is applied as the input into another identical stage i.e. it becomes Vin into a second averager, then the output of this second averager will have a ripple frequency of 200 Hz or 240 Hz. It is thus preferred to employ two circuits as shown in Fig. 7, these connected in series. Further circuits can be added if desired so as to give even better discrimination.

This progressive doubling of the frequency of the interfering signal makes the filtering of the heart beat signal from the interfering pick-up progressively easier to achieve.

No tuning is required and no special selection of components is necessary.

The final output signal is then a dc voltage, the magnitude of which varies directly with the magnitude of the interfering pick-up. Superimposed upon this dc voltage is the heart beat signal. The detection of the heart beat signal is then achieved by pulse detection circuitry which is as shown in, and as, described above with reference to, Fig. 2.

Preferably, medical apparatus in accordance with this invention incorporates at least one heart rate condition alarm. Three such alarm circuits will now be described with reference to Figs 8 -10. These circuits provide the facility to alarm in the event of: 1. The heart rate exceeding a pre-determined upper limit.

2. The heart rate falling below a pre-determined lower limit.

3. The heart rate suffering a 20% (approximately) reduction over a 30 second period.

High Heart Rate Detection The high rate limit is set by the operator (doctor or nurse) by means of a 15 position switch on the unit.

This switch is a hexadecimal switch which has a-BCD output (Binary Coded Decimal) so that any number between 1 and 15 may be generated by the switch. The maximum heart rate that this embodiment of the unit will register is pre-selected to be 300 beats/min. 300 b/m = 5 beats/sec; counted over a 3 second period the count would be 15. (This corresponds to the maximum number which can be set on the BCD HEX switch).

Count over a 3 sec x Scale factor = Rate beats/min period 15 x 20 = 300 14 x 20 = 280 13 x 20 = 260 5 x 20 = 100 The value of the high alarm rate is selected by the clinician and is set via the BCD Hex switch - e.g.

300(15), 280(14) etc. Every 3 seconds a clock pulse loads this number into counter 47. The counter 47 then subtracts each heart beat in turn from this preset number. If within the period of 3 seconds the number of heart beats exceeds or is equal to the number set on the BCD switch then the terminal count output is set and the alarm is triggered.

If the number of heart beats does not exceed the number set on the BCD switch within the 3 second period then the terminal count output will not be triggered, the number set at the PO to P3 inputs will be loaded once more and the process repeats.

Low Heart Rate Detection A range of lower limits is needed according to the age of the patient. Thus for a maximum lower limit of 150 beats/min = 150/60 beats/sec, then over a 6 second period, the count = 150/60 x 6 = 15.

Hence, as described above for the high rate alarm, Count over a 6 second x Scale factor = Rate beats/min period 15 x 10 = 150 14 x 10 = 140 3 x 10 = 30 The lower limit is selectable between 30 and 150 beats/min in increments of 10. In this case, if the number of heart beats which occur in 6 sec DOES NOT exceed that number set on the switch we need to alarm.

The terminal count output from counter 48 (Fig.

9 ) is normally high; it goes low when the terminal count is reached. If the Terminal Count output is still high when the clock pulse arrives the output of NAND gate 49 goes low and sets the alarm. If the Terminal Count output is low when the clock pulse arrives (i.e. the heart rate is above the lower limit setting) then as with the high rate counter, the number set on the switches is loaded into the counter once more and the process repeats.

Decelerating Heart Rate To detect a 20% deceleration over a 30 sec period, the monitor 1. Establish the heart rate (averaged over a 4 second period) 2. Wait 30 secs.

3. Establish a new heart rate and compare with that in 1. If it has dropped by 20% alarm.

If for example the initial count over 4 seconds was 12 i.e. 3 pulses/sec.

If at the end of 30 secs the rate has dropped by 20% i.e. the rate will now be 2.4 pulses/sec, and if we now count at this rate for 5 secs, the count would be 2.4 x 5 = 12 i.e. the same as what we started with.

If the rate had not dropped then the count at the end of 5 secs would be 3 x 5 = 15 i.e. the count would be greater than our initial count.

Therefore for a 20% reduction or more we alarm if the count taken over a 5 sec span is less than or equal to the count taken over a 4 sec span (but measured 30 secs. earlier).

The circuiting adopted in one embodiment to measure deceleration of heart rate will now be described with reference to Fig. 10.

Heart beats are counted in a 6 sec time slot by counter 50, i.e. after 6 sec the counter is reset to zero and the count re-started. The counter contents are continuously available (in binary form) at the outputs 0O, 01, 02, 03.

After 4 secs (from the start of a 6 sec slot) the count current in the counter 50 is loaded into the FIFO register 51, (First In First Out), where it is held for 30 secs before being made available at the FIFO output port 52 and presented to the 'B' inputs 53 of a magnitude comparator 54. Subsequent 4 second counts are loaded into the FIFO 51 for each 6 second time slot, where they in turn are held for 30 seconds before being dumped out.

The magnitude comparator 54 compares the magnitude of two binary numbers presented at its 'A' and 'B' inputs. The comparison is made 5 secs after the start of a 6 sec time slot by an "initialise comparison" pulse. The magnitude comparator 54 has the current counter contents applied to its 'A' input terminals at 55. After 5 seconds into a cycle, the 'initialise comparison' pulse arrives so that the current count taken over 5 secs is compared with the count taken over 4 secs (30 secs earlier). An output pulse (alarm trigger) is generated from the comparator 54 if the magnitude of the binary number at the A terminals is less then or equal to the number at the B terminals.

Claims

CLAIMS:

1. Medical monitoring apparatus comprising means for detecting and displaying data relating to a patient's heart rate, wherein said heart rate monitoring means comprises: (a) a plurality of inputs for electrodes which, in use, are positioned on the patient's abdomen; (bj an operational amplifier for amplifying the signal fed to said inputs by the electrodes; (c) a full wave rectification circuit arranged to act upon the output of the operational amplifier so as to reduce the effect of unwanted signal pick up from the electricity supply frequency and to deliver a DC signal whose magnitude is dependent on the unwanted signal element and on which there is superimposed the wanted signal indicative of the patient's heart rate; and (d) counting and display circuits and display means arranged to display parameters associated with the heart rate of the patient.

2. Apparatus as claimed in claim l, which further comprises means for generating an alarm signal.

3. Apparatus as claimed in claim 1 or 2, wherein said operational amplifier comprises a first stage triple op-amp circuit and an averager circuit, the AC output of said first amplification stage being fed to the averager which is arranged to generate a DC output signal and which incorporates said full wave rectification circuit

4. Apparatus as claimed in claim 3, wherein said full wave rectification circuit comprises two operational amplifiers.

5. Apparatus as claimed in claim 1, 2, X or 4, wherein said amplification and rectification circuitry is arranged to give frequency multiplication of the unwanted AC signal deriving from the mains supply frequency.

6. Apparatus as claimed in any preceding claim, wherein detection of a heart beat signal is achieved by pulse detection circuitry which includes a level detector adapted to detect changes in the prevailing level of signal fed to the detector, irrespective of the magnitude of the prevailing level.

7. Apparatus as claimed in claim 6, wherein said level detector comprises a comparator, the reference level of which is provided by a square wave signal supplied by an oscillator.

8. Apparatus as claimed in claim 7, when appendant to claim 3, wherein said level detector includes two series connected comparators, the first comparator receiving at its one input the signal from the averager and at its other input (a) the integrated output of the averager and (b) said square wave signal, the output of the first comparator being coupled to the input of the second comparator by way of a diode pumping circuit and a parallel capacitor, the other input of the second comparator being provided with a fixed reference level, whereby when the averager output remains constant an oscillating output is obtained from the first comparator which charges said parallel compacitor and holds the second comparator in one switching state, but when a change in averager output occurs a steady signal is temporarily obtained from the first comparator which causes the voltage on the parallel capacitor to decay and the second comparator to change switching states, thereby indicating that heart function has occurred.

9. Apparatus as claimed in any preceding claim, which is arranged to count and to display the heart rate of a patient.

10. Apparatus as claimed in claim 9, wherein there is provided a display of heart beats per minute which display is updated every 30 seconds.

11. Apparatus as claimed in claim 2, or in any one of claims 3 - 10 when appendant to claim 2, wherein said apparatus includes at least one heart rate condition alarm which is activated in the event of: (a) the heart rate exceeding a pre-determined upper limit; (b) the heart rate falling below a pre-determined lower limit; or (c) the heart rate suffering a 20% reduction over a 30 second period.

12. Medical monitoring apparatus substantially as hereinbefore described with reference to, ~ and as illustrated in, Figure 4 of the accompanying drawings.

13. Medical monitoring apparatus substantially as hereinbefore described with reference to, and as illustrated in, Figures 5, 6 and 7 of the accompanying drawings.

14. Medical monitoring apparatus substantially as hereinbefore described with reference to, and as illustrated in, Figures 8, 9 and 10 of the accompanying drawings.

15. Medical monitoring apparatus substantially as hereinbefore described with reference to, and as illustrated in, Figures 1 - 10 of the accompanying drawings.