GB2215565A

GB2215565A - Signal suppression circuits

Info

Publication number: GB2215565A
Application number: GB8805907A
Authority: GB
Inventors: John Richard Cobden Snow
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-03-12
Filing date: 1988-03-12
Publication date: 1989-09-20
Anticipated expiration: 2008-03-12
Also published as: GB2215565B; GB8805907D0

Abstract

An intermediate frequency stage signal suppression circuit for a radio frequency receiver is provided for the suppression of one or more relatively large signals of different frequencies occurring within a wideband input to the arrangement including a number of relatively small signals of still further different frequencies. The arrangement comprises mixer means 1, 2, 3 and associated controlled synthesiser means 4, 5 and 6 which mix down the signals within the wideband input to within a predetermined intermediate frequency band. Detector means 10 are provided for detecting and measuring the frequency or frequencies of any relatively large signals in the wideband signal and identifying them to control means 1 for the synthesiser means 4, 5, 6. The frequency output(s) from the synthesiser means will be varied in order to cause the output from the mixer means 1, 2, 3 to be notched down or filtered out by notch filter means 8, 9. The circuit reduces large signals to a level which does not produce spurious signals in a signal analysis arrangement or removes unwanted signals eg jamming signals. <IMAGE>

Description

IMPROVEMENTS RELATING TO SIGNAL SUPPRESSION CIRCUIT ARRANGEMEN TS This invention relates to circuit arrangements for suppressing (i.e. reducing or removing) unduly large signals within a signal frequency band to be monitored and/or analysed. Such arrangements may be utilised for example in wideband radar system receivers for analysing a band of received target echo signals.

Wideband signal receivers are often limited in multiple signal dynamic range due to limitations in the currently available analogueto-digital converters and signal analysis systems. Difficulties arise in such receivers when one or more relatively large signals occur within the particular frequency band required to be monitored and analysed and produce spurious outputs which obscure relatively small signals of interest within the particular frequency band. The relatively large signals referred to may be of interest and required to be monitored together with relatively small received signals within the band of interest or, they may be unwanted signals (e.g. jamming signals), in which case their removal from the band of interest is required.

Techniques to overcome the difficulties referred to above include the use of frequency selective limiters and coarse low frequency filters. However, such techniques do not provide signal resolution in keeping with that achievable with Chirp Z Transform (CZT) and Fast Fourier Transform (FFT) analysers employed for signals analysis purposes.

According to the present invention there is provided an intermediate frequency stage signal suppression circuit arrangement for a radio frequency receiver, in which for the suppression of one or more relatively large signals of different frequencies occurring within a wideband input to the arrangement including a number of relatively small signals of still further different frequencies said circuit arrangement comprises mixer means and associated controlled synthesizer means which mix down all the required signals within said wideband input to within a predetermined intermediate frequency band, in which means are provided foi detecting and measuring the frequency or frequencies of any relatively large signals occurring in the wideband input frequency band during operation of the circuit arrangement and in which the frequency or frequencies of any such relatively large signals are identified to processor control means for the synthesizer means whereby the frequency output(s) from the synthesizer means will be varied in order to cause the output or outputs from the mixer means to be notched down or filtered out by notch filter means whilst maintaining the same intermediate frequency band output from the circuit arrangement to the radio receiver.

When the relatively large signals are notched down the circuit arrangement serves as a spectral equaliser.

In the absence of any relatively large signals in the input frequency band the output frequency or frequencies from the synthesizer means will be such that the notch frequency or frequencies of the notch filter means will be outside the band or bands of output frequencies from the mixer means.

By way of example, one embodiment of the present invention will now be described with reference to the accompanying drawings in which: Figure 1 shows a block schematic diagram of an intermediate frequency stage circuit arrangement for a wideband radio frequency receiver; and, Figure 2 shows a typical input wideband signal to the circuit arrangement of Figure 1.

Referring to the drawings, the circuit arrangement of Figure 1 comprises an intermediate frequency stage of a wideband radio frequency receiver which in operation receives a wideband input signal (e.g. 5MHz) typically of the form shown in Figure 2. It will be seen from Figure 2 that the typical wideband input signals of 100 105MHz comprises two relatively large signals SL1 and SL2 of different frequencies (i.e. 101 and 104MHz) and a number of relatively small signals SS of different frequencies (i.e. 100.5, 102, 103 etc.) all of which signals within the input band are required in the present example to be monitored and analysed by means of an analyser (e.g. FFT analyser) in the receiver.As previously mentioned, the relatively large signals SLl and SL2 may cause spurious outputs from the signal analysis arrangement which tends to obscure the relatively small signals SS.

In order to overcome this problem in the analysis of wideband signals the amplitude of the relatively large signals SL1 and SL2 at 101 and 104 MHz, respectively, in the typical example under consideration are reduced by the signals being notched down to a relatively low level of amplitude at which the aforesaid spurious signals are avoided.

For the purpose of achieving this notching down of the relatively large signals SLI and SL2 of the wideband input to the circuit arrangement, the arrangement comprises three mixers, 1, 2 and 3 which are fed, respectively, with the outputs from three synthesizers 4, 5 and 6 which are under the control of a processor controller 7. Two crystal notch filters 8 and 9 providing a very sharp resolution are introduced, respectively, between the mixers 1 and 2 and the mixers 2 and 3. For the purpose of describing the operation of the circuit arrangement it may be conveniently assumed that the notch filter 8 has a notch frequency of 30 MHz and the other filter 9 has a notch filter of 15MHz, as indicated in Figure 1. The synthesizers 4, 5 and 6 may have output frequency ranges of 70 75MHz, 40 - 50MHz and 12.5 -17.5MHz, respectively.

With an input signal band of 100 - 105MHz applied to the circuit arrangement as indicated and in the absence of any relatively large signals, such as the signals SL1 and SL2, within the input band of interest the processor controller 7 may set the output frequencies of the respective synthesizers 4, 5 and 6 so that the input band of 100 - 105MHz is progressively mixed down by the mixers 1, 2 and 3 to an intermediate frequency band of 0 to f 2.5MHz. Moreover, the mixing down of the input band will serve to position the notch frequencies (i.e. 30MHz and 15MHz) outside the mixed down band of interest so that the filters will have no effect on the signals passing through the arrangement.

Under these conditions, the relatively small signals SS within the mixed down band of interest will be monitored and analysed by a suitable analyser (e.g. Fast Fourier Transform analyser) within the radio receiver shown in dotted outline at 10. Upon the occurrence of relatively large signals, such as signals SLl and SL2, within the band of interest of 100 - 105MHz these signals will be detected and their frequencies measured by means of the frequency analyser located within the receiver 10.The measured frequencies (i.e. 101 and 104MHz) of the relatively large signals will be identified to the processor controller 7 over line 11, whereupon the processor controller will vary the output frequencies of the three synthesizers 4, 5 and 6 to bring the notch frequencies of the notch filters 8 and 9 within the mixed down band of interest so that the amplitudes of the signals SL1 and SL2 at 101 and 104MHz, respectively are appropriately reduced whilst the intermediate frequency band output from the circuit arrangement remains unchanged. The reduction in level of the relatively large signals SLI and SL2 may be up to 60dB. More specifically, with the particular examples of frequencies under consideration, the output frequency of the synthesizer 4 would be changed by the processor controller 7 to 71MHz. This signal of 71MHz will be mixed by the mixer 1 with the input signal (see Figure 2) to the arrangement. The mixer 1 will mix down the relatively large input signal of 101MHz to 30MHz so that this mixed down signal coincides with the notch of the filter 8 and will therefore be substantially reduced in amplitude by the filter to a level corresponding generally to that of the relatively small signals SS of the band of interest. All of the mixed down signals within the band of interest including the relatively large signal SL2 will pass substantially unattenuated through the filter 8. For example, considering the relatively small signal SS at 103MHz, this will be mixed down to 32MHz whilst the relatively large signal SL2 will be mixed down to 33MHz.Both of these signals will pass unattenuated through the notch filter 8 and will be applied to the mixer 2.

However, with the synthesizer 5 set at 48MHz by the processor controller 7 the mixed down outputs from the mixer 2 in respect of the mixed down input signals of 32MHz and 33MHz will be 16MHz and 15MHz, respectively. Consequently, the 15MHz signal which corresponds to the relatively large signal SL2 of 104MHz in Figure 2 will be notched down by the notch filter 9 since it coincides with the notch frequency of that filter, whereas the other mixed down signal of 16MHz corresponding to the relatively small signal SS of 103MHz will pass through the filter without attenuation. Thus it will be appreciated that both the signals SLI and SL2 will now have been mixed down and attenuated to a level corresponding to that of the relatively small signals SS.

The third frequency synthesizer may be set to 16.5MHz by the processor controller 7 so that the original 5MHz band (100-105MHz) is finally converted to a band of 0+2.5MHz, for analysis. This may be performed using a quadrature splitting producing I and Q channels from a quadrature mixer 3. In order to avoid spurious signals passing down through the circuit arrangement, band pass filters (10MHz) may be placed in series with the notch filters 8 and 9.

From the foregoing description it will be appreciated that the mixing down process the frequencies of the detected relatively large signals within the band of interest are caused by the processor controller 7 controlling the synthesisers to coincide with notch frequencies of the respective notch filters. - It will of course be appreciated that the-circuit arrangement of the present invention could include just one notch filter when a single relatively large signal is required to be suppressed or, it may include more than two notch filters if further relatively large signals at different frequencies are to be suppressed.

Although in the specific example described the relatively large signals SL1 and SL2 are just reduced in amplitude, it will be understood that the signals could be completely removed from the band of interest in the case of unwanted signals (e.g. jamming signals).

It should also be appreciated that the outputs from the notch filter 9 instead of being fed into the single mixer 3 may be divided over two paths and fed to separate mixers, fed with the quadrature outputs from a synthesizer corresponding to the synthesiser 6. Thus the mixers will provide intermediate frequency band signals which are in quadrature relative to one another and these will then be fed to the radio receiver such as indicated at 10 in Figure 1.

The synthesizers 4, 5 and 6 may of compact chip form to acheive response times of a few tens of milliseconds in a very small power unit.

Claims

CLAIMS:

1. An intermediate frequency stage signal suppression circuit arrangement for a radio frequency receiver, in which for the suppression of one or more relatively large signals of different frequencies occurring within a wideband input to the arrangement including a number of relatively small signals of still further different frequencies said circuit arrangement comprises mixer means and associated controlled synthesiser means which mix down all the required signals within said wideband input to within a predetermined intermediate frequency band, in which means are provided for detecting and measuring the frequency or frequencies of any relatively large signals occurring in the wideband input frequency band during operation of the circuit arrangement and in which the frequency or frequencies of any such relatively large signals are identified to processor control means for the synthesiser means whereby the frequency output(s) from the synthesiser means will be varied in order to cause the output or outputs from the mixer means to be notched down or filtered out by notch filter means whilst maintaining the same intermediate frequency band output from the circuit arrangement to the radio receiver.

2. A circuit arrangement as claimed in Claim 1, wherein the mixer means comprises first, second and third mixers, the first and second mixers being connected by way of a first notch filter, and the second and third mixer being connected by way of a second notch filter.

3. A circuit arrangement as claimed in Claim 2, wherein the means for detecting and measuring the frequency or frequencies is a fast fourier transform analyser.

4. A circuit arrangement as claimed in Claim 3, wherein the third mixer is a quadrature mixer providing quadrature splitting producing in-phase and out-of-phase channels.

5. A circuit arrangement as claimed in Claims 2,3 or 4, wherein the output frequencies from the synthesiser means will be such that the notch filter frequencies will be outside the band of output frequencies of the mixers when the relatively large signals are absent from the input frequency band.

6. A circuit arrangement as claimed in any preceding claim, wherein the arrangement serves as a spectral equaliser when the relatively large signals are notched down by the notch filters.

7. A circuit arrangement substantially as hereinbefore described.

8. A circuit arrangement substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.