GB2214319A - Testing electronic circuits - Google Patents

Abstract

Apparatus for automatically testing electronic circuits (16) includes an AC measurement system (32, 22) and a time measuring circuit (18) for counting clock pulses provided between stop and start event edges presented to it. Two independent input selectors (54, 56) each selectively connect one of a plurality of its inputs to the time measuring circuit, and a plurality of local timing comparators (26, 28) generate an event edge upon receiving a signal crossing a threshold value. Also disclosed are making time measurements of signals at digital and analog pins using local comparators connected to input selectors over deskewed transmission paths and connecting a local comparator (68, 70) to the filter output of an AC measurement instrument (62, 63); and a differential input selector (Fig 2 not shown) for selectively connecting one of a plurality of differential inputs (118) to a differential output (122). <IMAGE>

Description

AUTOMATIC TEST EQUIPMENT.

The invention relates in one aspect to apparatus for automatically testing electronic circuits. In another aspect it relates to differential input selectors which can usefully be incorporated in such apparatus.

In apparatus for testing electronic circuits, input test signals are generated and provided to a fixture engaging the circuit under test ("CUT"), and resulting output signals are compared with expected results. The test signals and the resulting outputs can be digital, analog (e.g., audio or video) or a combination of digital and analog (e.g., for a codec or modem).

Such test apparatus typically includes time measuring circuits to measure such things as rise time, pulse width, propagation delay, frequency, duty cycle and ratios of repetitive events with respect to signals at the nodes of the CUT.

Typically a single time measuring circuit, including comparators that receive the signal or signals being timed and provide event edges to a timer/counter, is employed and is selectively connected to receive an analog signal or signals to be timed. A timer/counter typically counts clock pulses between start and stop events (i.e., the signal of interest crossing a designated threshold at which the comparator provides an event edge), and two counters can be used so that one can count clock pulses while the other counts events. when timing digital signals at digital nodes of the CUT, the comparators of the digital detectors provide the event edges that are selectively routed by switchi##g to he time measuring circuit.

In a prior art circuit tester available from Teradyne Inc. under the trade designation M606, a general time measuring circuit was provided in the mainframe, and a pair of timing comparators were located in an adjacent test table and connected to input/output plugs to which the user electrically connected his fixture for the CUT and any local pin electronics, e.g., switching and special instruments. Connecting the two timing comparators to more than two pins required switching by the user in his local pin electronics. Digital detectors were in subsystems for two testing stations that also were separate from the mainframe. The time measuring circuit could be connected through an input switch in the mainframe to either the two comparators dedicated to timing or to two comparators of the digital detectors in one of the two testing station subsystems.

We describe below apparatus which makes accurate time measurements of signals in automatic circuit testing apparatus by providing local timing comparators that are located near sources of signals to be timed, are dedicated to timing, and are connected to two independent input selectors of a time measuring circuit by transmission paths. The local comparators each provide an event edge that is independent of the signal to be timed and has the same characteristic as edges from other comparators upon sensing that the signal to be timed crosses a programmable threshold, adjusted to the event of the particular signal to be timed.One input selector can provide a start counting event, and the other can provide a stop counting event; by using two independent input selectors, greater flexibility and capabilities are provided, as one can select which of a plurality of timing comparators located near sources is to detect a start event and which is to detect a stop event. Also, the switching provided by the input selectors is of event edges, and not the actual analog signal being timed, and thus does not affect the signal being timed or the detection of its threshold.

We disclose connecting a local timing comparator to the output of a filter in an analog signal processing instrument including an analog to digital converter, thereby reducing noise in the signal to the local timing comparator, and reducing the number of measurements needed to be averaged. In preferred embodiments there are high and low frequency analog signal processing instruments and separate timing comparators connected to the filter outputs in each.

Accordingly, the present invention provides in one aspect thereof, apparatus for automatically testing electronic circuits and performing time measurements, said apparatus comprising: a fixture including node contacts adapted to contact nodes of a circuit under test; means adapted for operatively generating input test signals and for providing them to said node contacts; means adapted for detecting and processing.

output signals from said node contacts; a clock adapted for providing clock pulses; a time measuring circuit adapted for operatively counting clock pulses provided between start and stop event edges presented to lots a first alternating current measurement instrument including å first filter connected operatively to receive an analog source signal from a circuit under test and a first analog to digital converter connected operatively to receive the output of said first filter; a first local timing comparator connected to said first filter operatively to receive a filtered analog source signal and adapted operatively to generate an event edge when the filtered signal crosses a threshold value; and a first transmission path connecting said first local timing comparator to said time manuring circuit.

The invention is hereinafter more particularly described by way of example only with.reference to the accompanying drawings, in which:- Fig. 1 is a block diagram of elements of an electronic circuit testing apparatus relating to time measurement functions and constructed according to the present invention; Fig. 1A is a diagrammatic partial elevation showing a connection of channel cards to a fixture for a circuit under test by the Fig. 1 appar,atus; Fig. 2 is an electrical schematic of an input selector of the Fig. 1 apparatus; Fig. 2A is a diagram of wiring of integrated circuit chips of the Fig. 2 input selector; and Fig. 3 is a time diagram describing a frequency measurement using the Fig. 1 apparatus.

In Fig. 1 the elements of electronic circuit tester 1O relating to time measurements are shown. They include mainframe cabinet electronics 12 and test head electronics 14. The test head electronics are located in a test head that' includes, a plurality of daughter channel cards carrying portions of digital and analog instruments which are electrically connected over short distance, controlled impedance paths to fixture 15 connected to circuit under test ("CUT") 16.

Included in mainframe cabinet electronics 12 is the time measuring subsystem 18, which is used to measure time between events and to count events within a specified period of time, for example, to measure such things as rise time, pulse width, propagation delay, frequency, duty cycle, and ratios of repetitive events with respect to signals at the nodes of CUT 16. Also included in main frame electronics 12 is formatter cage 20, for providing input digital test signals to and for receiving and processing the output digital signals from CUT 16, and conversion cage 22, for providing input analog test signals to and for processing output analog signals from CUT 16.

Test head electronics 14 includes two analog time channel cards 24 each carrying local timing comparators 26, 28 (687 type, differential ECL) dedicated to making time measurements. Test head electronics 14 also includes analog direct current source and measure channel cards 30 and analog alternating current source and measure channel cards 32 (also referred to as conversion cards for both low frequency and high frequency), for providing and capturing analog signals, e.g., direct current, high accuracy direct current, low frequency alternating current, and high frequency alternating current.Each analog channel card 24, 30 or 32 is connectable to two nodes of CUT 16 over controlled impedance paths 34, 36, 38, which include (see rig. lA) connections through oo pins on interface board 39 (which is perpendicular to the channel cards), device card 41 (which is parallel to and connected to the interface board by pogo pins), and test fixture 15, supported on device card 41.

Each path 34, 36, or 38 can be directly connected to the components on its respective channel card (providing the shortest, primarily uninterrupted path for transmission of a signal for best accuracy) or can be connected via two-line, controlled impedance switching matrix 40 to components on any other analog channel card.

Time channel card 24 includes high impedance buffers 42, which also have high fidelity, and high speed, and minimize the loading of the nodes of CUT 16. Each buffer 42 is connectable via switches 44 to one or both (e.g., for a single channel measurement) of local timing comparators 26, 28. The other inputs of comparators 26, 28 are connected to respective programmable threshold voltage generators 46, 48. The outputs of comparators 26, 28 are connected via shielded, twisted pair lines 50, 52 to A, B input selectors 54, 56. A third E input selector 57 is connected to receive inputs from formatter cage 20 and conversion cage 22, also over shielded, twisted pair, differential ECL lines.Conversion cards 32 include differential amplifiers 58 connected by coaxial cables 60, 61 to high frequency and low frequency analog signal processors 62, 63 (including antialiasing and band-limiting filters). The outputs of signal processing 62, 63 are connected via lines 64, 65 to A/D converters 66, 67.

Conversion cage 22 also includes high and low reguency local timing comparators 68, 70 i# threshold inputs connected to ground to detect zero crossings. The outputs of comparators 68, 70 are selectively connectable to the inputs of selectors 54, 56, 57 via alternating current differential ECL channel selector 72.

Test head electronics 14 also includes a plurality of digital channel cards 74, for providing the high-speed digital test signals to digital pins of CUT 16 and detecting the output digital signals.

Digital channel card 74 includes high impedance buffer 75 and dual threshold digital comparator 76, having programmable voltage threshold generators 78 and differential ECL output lines 80, 82 connected over bus 83 to both the high-speed digital comparison circuitry 84 (to process output digital signals andsto compare them with expected results) and differential ECL high speed digital channel selector 86. Card 74 also includes high speed digital driver 87.

A, B, E input selectors 54, 56, 57 are each 16 to 1 differential ECL multiplexers described in more detail in Fig. 2 and the associated text below. Of the 16 inputs on each selector 54 or 56, six are for timing comparators 26, 28 (two per test head, up to three test heads), four are for high speed digital comparators 76, one is for one of frequency timing comparators 68 or 70, one is for checking purposes, and four are for additonal comparators that could be added in the future.

The outputs of the A and B input selectors 54, 56 are connected via switches 88, 90 to slope selectors 92, 94, to provide the desired slope to edges passing through them. The inputs of slope selectors 92. 94 are ccnnectabie to eaca steer cy single threshold connector 96, used, to make single-threshold, single-channel measurements, for example, frequency. The outputs of slope selectors 92, 94 are connected to switching and time gate circuitry 98, which provides gated clock pulses and event pulses to counters 100, 102 (24-bit counters). The outputs of counters 100, 102 are provided to RSM and computer readback circuitry 104 for storing desired timing information. Registers 106, 108 are used to preload counters 100, 102, respectively, to perform postcount functions with stop enable logic 110.Start enable timer/counter 112 is connected to receive inputs from E input selector 57 or A or B input selectors 54, 56 to provide a start enable pulse after a designated event or time or combination of the two. Switching and time gate circuitry 98 also provides pulses to interpolator counter circuitry 114, used to determine the time between an event that is asynchronous with a clock edge and a clock edge, to provide measurement resolution better than that of the reference clock. The output of interpolation counter circuitry 114 is provided to RAM in computer readback 116 and used with the output from counters 100, 102.

Referring to Fig. 2, there is shown a partial schematic for one half (eight inputs) of input selector 54. Input selectors 56, 57 are identical. Eight differential ECL inputs 118 are connected in parallel to pairs of differential amplifier elements 120 (10216) on the same integrated circuit chips, the outputs of which are connected to differential output bus 122. Each pair of amplifier elements 120 ma:ies u# a a-=erent#a amplifier 123 with increased power. Inputs 118 are connected to terminating resistors R1 (75 ohms), R2 (75 ohms), and R3 (470 ohms). Bus 122 includes termination resistors R4 and 25 (68 ohms).Each pair of differential amplifier elements 120 are powered on and off by transistor 124 (VMOS FET, available from Supertex under designation VN0106).

Capacitor C1 (0.1 uF) is used to bypass the differential amplifier's power supply. As can be seen in Fig. 2#, the output pins (2, 3, 15, 14) of the pairs of differential amplifiers 120 are in two rows, and adjacent integrated circuits 126, 128, 130 are aligned so that output bus 122, provided by conductors on a circuit board, is straight. This permits a high-quality transmission line output and high density of integrated circuits. ETs 124 are driven by a very low power control signal.

In general, in a typical time measurement, when signals to be timed cross thresholds, start and stop event edges are provided by local timing comparators and presented through input selectors 54, 56 to switching and time gate circuitry 98, and time counter 100 counts clock pulses between the two event edges. Event counter 102 optionally counts events during the time between the start and stop event edges, if desired.

The nodes of the CUT 16 having signals to be timed are either connected directly over paths 34 to comparators 26, 28 or over paths 36, 38 and two-line switching matrix 40. The path from the node of CUT 16 to the local timing comparator is of controlled impedance (to avoid reflections), and the path length is snort (to provide redb c--tac'tance and load), thereby providing minimal distortion to the signal presented to the local comparators, and thus accurate triggering on the threshold events.

when the signal presented to a local timing comparator 26 or 28 crosses a threshold, an ECL differential edge travels down the respective shielded, twisted pair 50 or 52 to the respective input selector 54 or 56. Because transmission paths 50, 52 are differential, they are immune to signal transmission distortions related to single-ended paths, for example noise and temperature. The shielding of these paths gives them controlled impedance, also helping in reducing distortion.

Referring to the schematic for the input selectors on Fig. 2, a differential input 118 is connected to the differential output bus 122 when a pair of differential amplifier elements 120 is powered on by the associated transistor 124.

Termination resistors R1 through R3 match the impedance in the input lines to that of transmission paths 50, 52. Termination resistors R4, R5 match the impedance of the output bus on the printed circuit board. Use of two differential amplifier circuit .elements 120 in parallel provides increased power for termination resistors R4, R5. Referring again to Fig. 1, slope selectors 92, 94 select the desired start and stop slopes.

when timing periodic signal inputs, start enable timer counter 112 is used to select which of a plurality of these events is used to start the counting. Likewise stop enable logic 110 is used to determine which event of a plurality is used as a stop event.

When the timing measurement involves one or more digital signals detected by comparators 76 on the digital channel cards, high-speed digital channel selector 86 presents one or two of the event edges on lines 80, 82 (each digital pin has an associated digital comparator 76 and two lines 80, 82) to one or two of input selectors 54, 56, 57.

when doing analog signal frequency or period measurements, the output from differential amplifier 58 is filtered by the respective analog signal processing 62 or 63, and the output from the filtering is used as the input to the respective comparator 68 or 70. Selector 72 selectively provides the edge to one of the input selectors 54, 56, 57.

Different transmission paths through the various comparators to the switching and gate circuitry are deskewed by providing the same input through an equal-delay branched network and comparing the times that the signals arrive at the time measuring circuit. The compared values are then automatically used in the software to adjust for differences in delay. This deskewing permits an event edge from any local comparator 26, 28, 68, 70, or 76,to used with an event edge from any other local comparator.

By having four local timing comparators in the test head near the circuit under test, precision timing measurements, employing a limited number of relays in the critical path between the node of the circuit under test and the comparator, of four pins can be made. In effect switching to select different signals for timing is done at differential ECL input selectors 54, 56, and this differential ECL signal distr#bution as a c esr#r be performance than an analog distribution system could achieve. Where switching is necessary to connect local comparators 26, 28 to different pins of circuit under test 16 (i.e., those not connected to lines 34), it is done through controlled impedance two-line matrix 40.

Fig. 3 is a timing diagram for an example of a timing measurement when the CUT is a phase locked loop integrated circuit, and it is desired to test the phase difference between the input and output alternating current signals, after the CUT has signalled its ready condition, indicating that the loop has locked. The analog input of CUT 16 is connected to the low frequency source card, and the analog output signal is connected to the low frequency measure card. The two-line matrix eo would have its switches closed so as to present the input signal to one of the local timing comparators 26, 28 and the output signal to the other. Input selectors 54, 56 are switched to present the event edges from comparators 26, 28 through slope selectors 92, 94 to switching and time gate circuitry 98.A digital ready pin of CUT 16 is connected through a digital comparator 76, and the desired output line 80 or 82 is routed through high-speed digital input selector 86 to E input selector 57, to provide the start enable signal to switching and time gate circuitry 98. When a digital ready output is detected by digital comparator 76, a start enable signal is presented to switching and time gate circuitry 98. when the analog input signal next crosses its respective threshold in the desired direction, the start event edge is provided to the counters, and counter 100 begins counting clock pulses. When the next threshold of the output waveform is crossed in the desired direction, the stop event edge is provided, and counter 100 stops counting. The clock pulses counted between these two events gives the difference in phase.

Other embodiments are feasible. For example, additional analog channel cards with additional local timing comparators can be provided and connected to the circuit under test, and their outputs can be connected by differential ECL transmission to input selectors 54, 56, 57.

Claims (3)

1. Apparatus for automatically testing electronic circuits and performing time measurements, said apparatus comprising: a fixture including node contacts adapted to contact nodes of a circuit under test; means adapted for operatively generating input test signals and for providing them to said node contacts; means adapted for detecting and processing output signals from said node contacts; a clock adapted for providing clock pulses; a time measuring circuit adapted for operatively counting clock pulses provided between start and stop event edges presented to it; a first alternating current measurement instrument including a first filter connected operatively to receive an analog source signal from a circuit under test and a first analog to digital converter connected operatively to receive the output of said first filter; a first local timing comparator connected to said first filter operatively to receive a filtered analog source signal and adapted operatively to generate an event edge when the filtered signal crosses a threshold value; and a first transmission path connecting said first local timing comparator to said time measuring circuit.

2. Apparatus according to Claim 1, wherein- said first alternating current measurement instrument is high frequency; and further comprising a second low frequency alternating current measurement instrument including a second filter and a second analog to digital converter, a second local timing comparator connected to the output of said second filter operatively to receive a filtered analog source signal and adapted operatively to generate an event edge when the filtered signal crosses a threshold value, and a second transmission path connecting said second local timing comparator to said time measuring circuit,

3. For automatically testing electronic circuits and performing time measurements, apparatus according to Claim 1 as hereinbefore described with reference to and as shown in the accompanying drawings.