GB2213683A - Channel tester - Google Patents

Abstract

A channel tester for testing the communications link or channel from a central processing unit to a plurality of peripheral devices comprises an input/output module (14 Fig 1) for connection to the channel in place of the central processing unit which may continue to operate during the tests. Included in the device are a memory unit (94-100, Fig 3) a plurality of manual controls 48-60, a plurality of display means 32-46 and a processing unit (78 Fig 3). The processing unit (78) monitors the manual controls 48-60 and retrieves information from the memory unit (94-100) in accordance therewith. Test signals are transmitted into the channel by processing of the said information and the display means 32-46 are controlled to indicate the results of transmission of the test signals. Tests, which may be performed at fast or slow rates are intended to determine communications circuit faults, including for example duplicated peripheral addresses. DMA is used for the test routines. <IMAGE>

Description

Title:- Channel tester The present invention relates to a channel tester.

That is, a device for testing the communications link or channel from a central processing unit to a plurality of peripheral devices.

The maintenance of computer systems has become a significant industry which has an identity separate from that of the computer manufacturing companies. Much of the maintenance work undertaken by the maintenance companies can be carried out using the central processing unit of the computer system itself. However, this often means that the whole system has to be given over to the maintenance company and is effectively out of use until it is repaired. If the fault on the channel is not readily identifiable, it is frequently necessary for the maintenance company to refer the problem to the manufacturer of the computer. This results in various disadvantages to the parties involved, not least of which is the delay which may be incurred in resolving the malfunction.Simple forms of test equipment have been proposed in an attempt to enable independent maintenance companies to tackle these specific forms of malfunction. However, the previously proposed test equipment has been of a particularly basic nature and it is generally considered that more sophisticated test equipment is not feasible.

Nonetheless, the present invention seeks to provide an improved channel tester which will mitigate the above described disadvantages.

According to the present invention there is provided a device for testing the communications link or channel from a central processing unit to a plurality of peripheral devices, comprising: an input/output module having an input connector for receiving the channel and an output connector for driving the channel, both in place of connections to the said central processing unit, a memory unit for storing information relating to signals to be transmitted via said output connector so as to initiate various tests, a plurality of manual control means for selecting the tests to be undertaken, a plurality of display means for indicating the results of tests, and a processing unit which operatively; monitors the manual control means and retrieves information from the memory means in accordance with operation of the manual control means, processes the said information such that the signals are transmitted, and regulates operation of the display means in accordance with the result of said transmission such that the display means indicate the test results.

It is to be noted that there is no operative connection of the tester to the central processing unit. Consequently, the computer system can be used, apart from the channel under test, while the fault is located and repaired.

An embodiment of the invention will now be described in detail by way of example only and with reference to the accompanying drawings, in which: Figure 1 is a schematic perspective view of the external appearance of a channel tester embodying the present invention, Figure 2 is a plan view of a portion of the channel tester shown in figure 1, and Figure 3 is a block circuit diagram of the components of the channel tester shown in Figure 1.

As indicated in figure 1, the channel tester 10 comprises two units which, for ease of reference, will be referred to as the controller 12 and the input/output (or I/O) module 14. The controller 12 is housed in a brief case type housing 16 and as a recess 18 for receiving the I/O module 14 and a mains connection lead 20. Thus, the entire channel tester can be stored in case 16 and is very readily transportable.

The I/O module 14 is cube shaped and is provided with two standard connectors, 22 and 24, on its top surface. Two multi-strand ribbon cables, 26 and 28 are connected to the internal circuitry of the I/O module 14 and pass through one of its vertical faces. Both of the ribbon cables 26, 28 are terminated with connectors which are received in corresponding connectors (not shown) provided within recess 18 in the controller 12.

Electrical power at 240 volts and/or 110 volts (at 50 or 60 Hz) is supplied to the controller 12 via lead 20. Apart from recess 18, the surface area inside housing 16 is taken up by a control panel 30. Mounted on control panel 30 along the rear end of the case are four LCD displays 32-38 in front of these is an elongate LCD display 40 in front of which are two rows of six LEDs 42 with two additional LEDs 44 and 46 being spaced apart from, but in line with, respective LED rows.

Along the front edge of the control panel are provided; a hex switch 48, five manual switches 50-58 and a COMMAND knob 60. The operation and function of components 32 to 60 will become apparent from the description given below.

The specific embodiment of the invention described herein with reference to the drawings constitutes a channel tester for testing IBM equipment and the IBM 360/370 computer systems in particular. Attention is directed to IBM Publication GA.22-6974-08 (file No.

S360/S370-19) entitled IBM System/360 and System/370 I/O Interface Channel to Control Unit: Original Equipment Manufacturers' Informationll. That publication is specifically incorporated herein by reference thereto. As indicated by the title of the publication, it contains information which is referred to by Original Equipment Manufacturers. The publication and its contents are very well known to those people providing maintenance services for the IBM 360/370 systems. The precise requirements of the various signals transmitted by the channel tester of the present invention and interpretation of the response to such transmitted signals will be readily apparent from the aforesaid IBM publication.Consequently, a detailed discussion of the precise form of the transmitted signals and the precise method of interpreting responses to such signals will not be described herein. A person skilled in the art will readily derive this information from the aforesaid IBM publication.

The whole of the circuitry of the channel tester is arranged so as to meet the specific requirements and standards as set out in the above mentioned IBM publication. In particular, the circuitry is arranged so as to ensure that there is no possibility of any signals being transmitted into the IBM channel which could damage either the IBM CPU or the IBM control unit/peripheral devices. In particular, these fail safe features include initial checking of the channel connections to connectors 22 and 24 prior to the supply of power to the main operative circuits 62 and 68, of the 1/0 module 14. This is achieved by a power supply relay which is only energised once the initial check has confirmed correct connection of the I/O module 14 to the IBM channel.

It is to be appreciated that ribbon cables 26 and 28 do not necessarily provide connections for all of the BUS and TAG signals available on the IBM channel. This is because the specific tests to be carried out by the channel tester need only be concerned with those malfunctions of peripheral devices and their control units which are not readily detectable using the main IBM system CPU. One reason why a malfunction may not be readily identifiable using the IBM system CPU is if that malfunction prevents the IBM system CPU itself from operating correctly. That is, if the original malfunction brings the whole IBM system down.

For example, the channel tester will not monitor the TAGS used for write operations since such an operation could be catostrophic to a customer's storage media (discs, tapes ete).

It is to be noted that the purpose of the channel tester is to test the integrity of the channel itself.

The channel tester is not required to detect faults within individual peripheral devices, as such, other than communication circuitry faults. The purpose of the channel tester is to identify the location of a malfunction which is preventing use of the entire channel, with a view to enabling the device causing the malfunction to be omitted from the system configuration. This will enable the channel to be brought back into operation while the malfunctioning device is taken off-line for repair. This is particularly significant when one considers that up to eight sets of two hundred and fifty six peripheral devices can be connected per channel in the IBM 370 system.

The basic circuit arrangement of a channel tester which embodies the present invention will now be described with reference to figure 3 of the accompanying drawings.

The IBM channel is connected to the I/O module 14 via connector 22 which is connected to a BUS and TAG receiving circuit 62, the so-called BUS and TAG being the constituent parts of the IBM channel. Output from circuit 62 is transmitted over the ribbon cable 26 via a buffer 64. Similarly, output from the controller 12 via ribbon cable 28 is received into a buffer 66 provided in the I/O module 14. Buffer 66 is connected to a BUS and TAG drive circuit 68, the output of which is connected to connector 24, for onward transmission to the control unit/peripheral devices to be tested. As indicated in figure 2, power supply and control signals for the I/O module 14 are provided by the controller 12 via the ribbon cables 26 and 28. The ribbon cables 26 and 28 are connected to respective buffers 70 and 72 provided in the controller 12.

The circuit components of controller 12 are organised around an address bus 74- and a data bus 76, both are connected to a central processing unit (CPU) 78. Buffer 70 which receives incoming signals from the I/O module 14 is connected to data bus 76 via a BUS and TAG input circuit 80. Similarly, data bus 76 is connected to the output buffer 72 via a BUS and TAG output circuit 82. Signals transmitted between buffer 70 and BUS and TAG input circuit 80 are also supplied to a parity check and BUS in/status display 84. Signals transferred between BUS and TAG output circuit 82 and buffer 72 are also supplied to a hex display and parity generator 86.

An LCD interface 88, hex switch 90 and additional function switches 92 are connected to the data bus 76.

A number of memory units are connected between the bus 76 and the address bus 74. These memory units include: an EPROM 94 which controls tester code; a scratch pad RAM 96; main RAM 98 and an EPROM 100. EPROM 100 stores data and the channel tester system code. Also connected to the address bus 74 is a control bus 102 via which control signals are supplied from the CPU 78 to other components of the tester (as indicated in figure 2 by the signal lines designated CONT.

Figure 3 indicates additional components which are provided so as to facilitate the initial testing and encoding of the various test routines which are to be undertaken by the channel tester. This can be considered as an optional facility and these features are not used during normal operation of the channel tester. Specifically, these additional components constitute a DMA system which is arranged as follows.

Respective buffers 104 and 106 are connected to the address bus 74 and data bus 76. The output from these buffers are respectively connected to a DMA address bus 108 and a DMA data bus 110. Both of buses 108 and 110 are connected to a DMA RZffl 112 and the DMA address bus 108 is also connected to an additional sequence logic circuit 114. Additional sequence logic circuit 114 receives input from a connector 116 via which the DMA system is connected to a separate computing system for initial testing and loading of test sequences. RAM 112 is provided with a battery backup 118 and connection of the DMA system to the address bus 74 and data bus 76 is controlled by an on/off switch 120.

The DMA system, as described above, is provided so as to facilitate the development of the test routines to be carried out by the channel tester. When the test routines have been established as functioning correctly, the information necessary for generating the test signals is stored in EPROM 94. If the DMA system is not provided, the test routines are initially encoded in EPROM 94 which must be removed and re-encoded if it is found that any of the test routines are not operating satisfactory. The DMA system also allows downloading of test software in the event of a fault within the tester.

The control panel 30 shown in figure 1 is shown in more detail and in plan view in figure 2 Specifically, figure 2 includes the legends associated with the individual components of the control panel.

As indicated by the legends on the control panel, as shown in figure 2, the LCD display 32 is associated with the BUS OUT function, LCD 34 is associated with the BUS IN function, LCD 36 is a status indicator and LCD 38 is associated with a BAT (Basic Assurance Test) function.

The BUS OUT display 32 displays the data on BUS OUT in hex format. Similarly, the BUS IN display 34 displays the data on BUS IN in hex format. Status display 36 displays the status byte in hex format. The Basic Assurance Test function includes power up and rest of the diagnostic indicators. Display 38 also displays the number of bytes transferred as a result of a data transfer.

The LEDs 42 of tester 12 can provide various indications of the signal being received from the peripheral devices connected to the channel under test.

Specifically, the address of individual peripheral devices can be set using hex switch 48. The manual control switches 50-60 can be set such that the status of the individual peripheral device whose address is set by hex switch 48 is indicated by illumination of various ones of the LEDs 42. In general, one row of LEDs 42 is controlled by the TAG IN function and the other row is controlled by the TAG OUT function. That is, the LED's show the state of the respective TAG lines indicated by the legend associated with each LED. The LED is illuminated when the associated TAG line is raised. The TAG OUT LEDs are illuminated in accordance with the particular test which is being undertaken.In contrast, the TAG IN LEDs are illuminated under the control of the IBM channel and the only function which can be undertaken by the channel tester in respect of these TAG IN LEDs is to de-illuminate them by using a correct response on a TAG OUT. The TAG IN LEDs are purely passive monitors, but they do provide useful indications as to operation of the channel.

The two rows of six LEDs 42 each contain four LEDs which are associated with the same function for both the TAG OUT and TAG IN functions. These four LEDs/TAGs are; ADD (ADDRESS), OPER (OPERATIONAL), SVC (SERVICE IN), and SEL (SELECT IN). The two remaining TAG OUT LEDs are associated with the HOLD TAG and the CMD (COMMAND) TAG.

The two remaining TAG IN LEDs are associated with an REQ (REQUEST IN) function and a STA (STATUS IN) function respectively. Manual control switch 50 can be set either at MAN (MANUAL) or SCAN positions.

In the MAN setting, test signals are sent to the particular peripheral device whose address is set by hex switch 48. In the SCAN position, the channel tester scans through the addresses of all peripheral devices attached to the channel and sequentially applies the same test to each of the peripheral devices in turn.

Manual control switch 52 has RESET and EXEC (EXECUTE) settings. To initiate a test, control switch 52 is placed in the EXEC setting. Switch 52 is placed in the RESET position in order to initialise a test routine.

Manual control switch 53 also has two settings. These are ERR LOOP and PASS LOOP. The setting of switch 54 determines whether the test routine loops on encoutering an error (ERR LOOP) or loops on pass (PASS LOOP). That is, loop on error enables a test to be automatically re-run when the test fails and loop on pass enables a test to be automatically re-run when the test has successfully been completed.

Manual control switch 56 had two settings, ABORT and CONT (CONTINUE). This control switch enables a test to be aborted or continued at certain stages during any particular test, or abort at any time if held for 3 seconds or more. Manual control switch 58 enables a test to be executed one step at a time in either the forward (STEP +) or reverse (STEP -) directions. The step +/step - enables the operator to step through bytes in memory which have resulted from a data transfer.

COMMAND/knob 60 can be placed in any one of six settings. These settings are associated with the three basic IBM diagnostic commands; TEST I/O, BASIC SENSE, and SENSE I/D. These three IBM commands are emulated by the channel tester without making use of a substantial portion of any software developed by IBM, That is, from the above identified IBM publication, it is within the capabilities of a person skilled in the art to generate software to emulate the IBM commands without making use of software developed by IBM. The illustrated embodiment of the present invention provides for all tests to be undertaken at either a fast speed or a slow speed. In the fast speed setting, the channel tester operates at approximately 2 MHz.In the slow speed setting, the channel tester operates at a speed dictated by the specific test being performed and this speed setting generally enables an operator to view the entire sequence of illumination of LEDs 42, which may not be possible in the fast mode setting. The slow speed setting of COMMAND knob 60 is achieved by introducing a delay in transmission of the acknowledge signal. Hence, of the six positions associated with COMMAND knob 60, settings 1 to 3 are slow speed settings and settings.4 to 6 are fast speed settings. Further, positions 1 and 4 are associated with the command (TEST I/O), positions 2 and 5 are associated with the command BASIC SENSE, and positions 3 and 6 are associated with the command SENSE IJD.

The three IBM commands referred to above are emulated by the channel tester and details of the transmitted signals involved, expected responses and the like are as described in the above mentioned IBM publication and are therefore not described herein in detail. The following observations should, however, be noted. The command BASIC SENSE is not generally recognised as a command which can be used to check the integrity of a channel. Normally, this command would be used under the control of the CPU of the IBM system so as to indicate to the operator warnings such as "DO NOT ATTEMPT TO WRITE TO THIS DISK, BECAUSE IT IS WRITE PROTECTED.". The information returned in response to transmission of the BASIC SENSE command is, however, comprehensive and can give a much more detailed indication of the status of the channel and individual devices in particular.Such information can be interpreted by highly skilled specialists but such interpretation is not within the skills of the average systems maintenance engineer. The highly skilled engineer would make use of a so-called @programming card" which is essentially a look-up table which denotes the significance of the various fault codes which can be returned in response to the BASIC SENSE command. This look-up table is effectively encoded in the memory of the channel tester and responses to transmission of the BASIC SENSE command are interpreted automatically by the channel tester so that the result from the look-up table is displayed on the LCD display 40.

The SENSE I/D command generates a response which identifies inter alia the type, model, address etc. of the individual peripheral device to which the command is transmitted. Using tis command, the tester undertakes a test to check the actual address of each peripheral device connected to the channel. The occurrence of a duplicate address, perhaps caused by a change in systerm configuration or by a fault in the device, is one of the more common problems which result in a channel malfunction of the type in question. The LCDs 32-38 give an interpretation of the response to the SENSE I/D command. In particular, the status of each device can be display on LCD 36.

The raising and lowering of the TAG levels indicates the sequence of data flowing on the channel. In particular, the channel tester readily indicates when a particular peripheral device is not responding, when such a device has a wrongly set address and when such a device is not actually on-line.

The address of a particular peripheral device can be set using the hex switch 48 and, with switch 50 set to MAN, switches 54, 56 and 58 can be used to carry out a more detailed test of that one particular device.

The parity added (by parity generator 86) to outgoing signals and checking of that parity (by unit 84) on incoming signals is purely a function of the channel tester and is not associated with any parity checking used by the IBM system. This parity check introduced by the channel tester is transparent to the channel except when an error occurs on parity checking, in which case the test routine is interrupted. Should a parity error occur, the test routine is interrupted and the PARITY LED 44 is illuminated. The channel tester does not treat these parity errors as being fatal.

The HALT LED 46 is illuminated if the controller software enters a loop awaiting user intervention.

LCD display 40 provides the test engineer with messages at various points of testing, such as the above mentioned responses to the BASIC SENSE command.

The fact the units 62 and 68 are contained in I/O module 14 enables the arrangement to conform readily with the IBM specification concerning the maximum distance from the connector to the printed circuit board containing such circuits. The provision of a separate I/O module is also more convenient for an engineer to use since connection of the bulky channel cables is facilitated.

The channel tester is simple to operate and enables previously highly specialised testing to be carried out by general maintenance invention.

One embodiment of the invention has been described in detail with reference to the accompanying drawings.

It will be readily apparent to those skilled in the art that various modifications can be made without departing from the scope of the invention.

Claims (24)

1. A device for testing the communications link or channel from a central processing unit to a plurality of peripheral devices, comprising: an input/output module having an input connector for receiving the channel and an output connector for driving the channel, both in place of connections to the said central processing unit, memory unit for storing information relating to signals to be transmitted via said output connector so as to initiate various tests, a plurality of manual control means for selecting the tests to be undertaken, a plurality of display means for indicating the results of tests, and a processing unit which operatively: monitors the manual control means and retrieves information from the memory means in accordance with operation of the manual control means, processes the said information such that the signals are transmitted, and regulates operation of the display means in accordance with the result of said transmission such that the display means indicate the test results.

2. A device as claimed in claim 1, comprising a main power supply relay and connection testing means, the arrangement being such that the relay can only be energised after successful verification by the connection testing means that the device is correctly connected to the channel.

3. A device as claimed in claim 1 or claim 2, wherein the manual control means include a hex switch arranged for selection of the address of individual peripheral devices to be tested.

4. A device as claimed in any preceding claim, wherein the memory unit comprises an EPROM which stores information relating to signals to be transmitted.

5. A device as claimed in any preceding claim, wherein the memory unit includes an EPROM which stores information for controlling the processing unit.

6. A device as claimed in any preceding claim, wherein the memory unit includes a RAM.

7. A device as claimed in any preceding claim, further comprising a direct memory access (DMA) system arranged to enable development of test routines.

8. A device as claimed in any preceding claim, wherein the plurality of display means includes respective displays associated with BUS OUT, BUS IN, STATUS and BASIC ASSURANCE TEST all as hereinbefore defined.

9. A device as claimed in claim 8, wherein the said displays are Liquid Crystal Displays.

10. A device as claimed in any preceding claim, wherein the plurality of display means includes one group of displays associated with TAG IN as hereinbefore defined and a second group of displays associated with TAG OUT as hereinbefore defined.

11. A device as claimed in claim 10, wherein each of the two groups have respective displays associated with ADDRESS, OPERATIONAL, SERVICE IN and SELECT IN all as hereinbefore defined.

12. A device as claimed in claim 10 or 11, wherein the TAG IN group includes respective displays associated with REQUEST IN and STATUS IN as hereinbefore defined.

13. A device as claimed in any of claims 10 to 12, wherein the TAG OUT group includes respective displays associated with TAG HOLD and TAG COMMAND as hereinbefore described.

14. A device as claimed in any of claims lo to 13, wherein the displays associated with TAG IN and TAG OUT are Light emitting diodes.

15. A device as claimed in any preceding claim, wherein the plurality of manual control means include a two position switch one position of which is associated with MANUAL as hereinbefore defined and the other position of which is associated with SCAN as hereinbefore defined.

16. A device as claimed in any preceding claim, wherein the plurality of manual control means include a two position switch one position of which is associated with REREST as hereinbefore defined and the other position of which is associated with EXECUTE as hereinbefore defined.

17. A device as claimed in any preceding claim, wherein the plurality of manual control means include a two position switch one position of which is associated with ERROR LOOP as hereinbefore defined and the other position of which is associated with PASS LOOP as hereinbefore defined.

18. A device as claimed in any preceding claim, wherein the plurality of manual control means include a two position switch one position of which is associated with ABORT as hereinbefore defined and the other position of which is associated with CONTINUE as hereinbefore defined.

19. A device as claimed in any preceding claim, wherein the plurality of manual control means include a two position switch one position of which is associated with STEP + as hereinbefore defined and the other position of which is associated with STEP - as hereinbefore defined.

20. A device as claimed in any preceding claim, wherein the plurality of manual control means includes a multi-position switch having respective positions associated with TEST I/O, BASIC SENSE and SENSE ID all as hereinbefore defined.

21. A device as claimed in claim 20, wherein the multi-position switch has six positions, three for undertaking the specified functions at a constant cycle frequency and three for undertaking the specified functions with a delay in transmission of the acknowledge signal.

22. A device as claimed in any preceding claim, further comprising a parity signal generating means and a parity signal checking means.

23. A device as claimed in any preceding claim, wherein the device is housed in a hand portable case with the input/output module being separate from but receivable in said case.

24. A device for testing the communications link or channel from a central processing unit to a plurality of peripheral devices, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.