GB2213338A - Tapped delay line using multiplexer - Google Patents
Tapped delay line using multiplexer Download PDFInfo
- Publication number
- GB2213338A GB2213338A GB8820367A GB8820367A GB2213338A GB 2213338 A GB2213338 A GB 2213338A GB 8820367 A GB8820367 A GB 8820367A GB 8820367 A GB8820367 A GB 8820367A GB 2213338 A GB2213338 A GB 2213338A
- Authority
- GB
- United Kingdom
- Prior art keywords
- multiplexer
- delay line
- delay
- resistors
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Networks Using Active Elements (AREA)
- Pulse Circuits (AREA)
Abstract
A variable digital delay line comprises a CMOS multiplexer, and a chain of resistors with tapping points connected to the multiplexer inputs. The input impedances of the multiplexer are almost purely capacitative, and these capacitances, together with the resistors, form a delay line. <IMAGE>
Description
VARIABLE DIGITAL DELAY.
This invention relates to variable digital delay lines.
It is known to construct such a delay line by means of an inductance - capacitance network, using a multiplexer to select the output from different tapping points of the network. However, it has been found that, for very small delay increments, of the order of one nanosecond or less, such a delay line is difficult to construct, since the required capacitance values may be smaller than the input capacitance of the multiplexer.
The object of the present invention is to overcome this problem.
According to the invention there is provided a variable digital delay line comprising: (a) a multiplexer having a plurality of inputs
whose impedances are substantially purely
capacitative, and (b) a chain of resistors connected in series, the
chain having a plurality of tapping points
connected to the inputs of the multiplexer,
whereby the resistors together with the input
impedances provide a delay network, and the
multiplexer is operable to select one of a
plurality of different delay values.
One delay line in accordance with the invention will now be described by way of example with reference to the accompanying drawing, which is a circuit diagram of the delay line.
Referring to the drawing, the delay line comprises an 8-input mulitplexer 1. In this example, the multiplexer is a Fairchild 74 AC 151 CMOS integrated circuit device. Such CMOS devices differ from earlier
TTL devices in having inputs which are almost purely capacitative. In the present example, the inputs of the multiplexer 1 have capacitances of approximately 5 picoFarads.
The delay line also includes a chain of seven resistors R1-R7, connected in series with'an input terminal 2. The tapping points between adjacent pairs of resistors are connected to respective inputs of the multiplexer 1, as shown.
The output of the multiplexer 1 is connected to an output terminal 3.
The multiplexer is controlled by a three-bit control signal S0-S2 which selects one of the eight inputs and hence determines the overall delay between the input and output terminals 2, 3.
The values of the resistors R1-R7 depend on the required delay per stage of the delay line and can be calculated using a known transient analysis program. The following table shows the values required for delays of 250 picoseconds and 500 picoseconds per stage.
Delay per stage Resistance (ohms) (picoseconds) R1 R2 R3 R4 R5 R6 R7
250 16.07 14.57 12.13 11.75 14.80 22.50 47.10
500 44.30 22.30 19.27 22.07 28.94 44.63 94.01
The above figures assume that the input capacitances are exactly 5 picoFarads. A set of temperature compensated trimming capacitors may be connected between the tapping points and earth, the values of these capacitors being chosen so as to make the effective input capacitances exactly equal to 5 picoFarads. Alternatively, these trimming capacitors may be omitted, with consequent adjustment of the values of the resistors.
Claims (3)
1. A variable digital delay line comprising: (a) a multiplexer having a plurality of inputs
whose impedances are substantially purely
capacitative, and (b) a chain of resistors connected in series, the
chain having a plurality of tapping points
connected to the inputs of the multiplexer,
whereby the resistors together with the input
impedances provide a delay network, and the
multiplexer is operable to select one of a
plurality of different delay values.
2. A delay according to Claim 1 wherein said multiplexer is a CMOS device.
3. A delay line substantially as hereinbefore described with reference to the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB878728495A GB8728495D0 (en) | 1987-12-05 | 1987-12-05 | Variable digital delay |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8820367D0 GB8820367D0 (en) | 1988-09-28 |
| GB2213338A true GB2213338A (en) | 1989-08-09 |
| GB2213338B GB2213338B (en) | 1991-07-31 |
Family
ID=10628060
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB878728495A Pending GB8728495D0 (en) | 1987-12-05 | 1987-12-05 | Variable digital delay |
| GB8820367A Expired - Fee Related GB2213338B (en) | 1987-12-05 | 1988-08-26 | Variable digital delay |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB878728495A Pending GB8728495D0 (en) | 1987-12-05 | 1987-12-05 | Variable digital delay |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8728495D0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2661059A1 (en) * | 1990-04-16 | 1991-10-18 | Tektronix Inc | DIGITAL TIMER CIRCUIT THAT CAN BE SELECTIVELY ACTIVE. |
| EP0539831A2 (en) * | 1991-11-01 | 1993-05-05 | Hewlett-Packard Company | Pseudo-NMOS programmable capacitance delay element |
| US7453302B2 (en) | 2003-12-23 | 2008-11-18 | Infineon Technologies Ag | Temperature compensated delay signals |
-
1987
- 1987-12-05 GB GB878728495A patent/GB8728495D0/en active Pending
-
1988
- 1988-08-26 GB GB8820367A patent/GB2213338B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2661059A1 (en) * | 1990-04-16 | 1991-10-18 | Tektronix Inc | DIGITAL TIMER CIRCUIT THAT CAN BE SELECTIVELY ACTIVE. |
| EP0539831A2 (en) * | 1991-11-01 | 1993-05-05 | Hewlett-Packard Company | Pseudo-NMOS programmable capacitance delay element |
| EP0539831A3 (en) * | 1991-11-01 | 1995-04-26 | Hewlett Packard Co | |
| US7453302B2 (en) | 2003-12-23 | 2008-11-18 | Infineon Technologies Ag | Temperature compensated delay signals |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8820367D0 (en) | 1988-09-28 |
| GB2213338B (en) | 1991-07-31 |
| GB8728495D0 (en) | 1988-01-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |