GB2210744A - D C offset voltage nulling circuit - Google Patents

Abstract

A first feedback loop of the circuit includes a sample/hold circuit C1A2 connected by a switch S2 across an amplifier A1 to which the signal to be nulled is applied as an input. The input signal is periodically disconnected and the offset voltage at the amplifier is sampled, by opening S1 and closing S2 and S3 and applied as a correction voltage, and held when the signal is reconnected. Thus, offsets due to the signal line or lines, the amplifier and the sample/hold are all nulled. A second feedback loop, R3, provides no D C feedback during the sampling interval because S1 is open. R3 may be replaced by a permanently connected capacitor (Fig 2). <IMAGE>

Description

Offset Voltage Nulling Circuit This invention relates to a circuit for nulling offset voltages.

It is frequently required to measure a specific DC voltage amplitude in electronic circuits. To enable this to be done accurately it is preferable that electronic devices have low offset voltage characteristics so that a true value for the amplitude may be obtained, otherwise, the offset voltage would add to the wanted signal to give a false amplitude reading. However, there are still occasions when high offset voltages remain in a circuit and tend to degrade the performance. Typical circumstances are; when a large gain is involved in a circuit, which may compound the poor offset performance of a device; variations in operating temperature, which can affect offset voltages; and, when a signal path is taken through a large number of DC-coupled devices, the signal will tend to accrue a large offset voltage.Also, a device may itself be one whose offset voltage can not be minimised, such as a biassed detector diode.

In such circumstances some form of nulling of the offset voltages is required to obtain accurate results.

This may be performed manually by periodically disconnecting a signal and directly observing any offset voltages in a system and altering the values of components in the system to eliminate or null the observed offsets.

For instance, variable resistors may be used. Such a system suffers in that the presence of an operator is continually required to observe the system, and also in that the system must be disconnected for relatively long periods in order that nulling is achieved, during which periods useful measurements can not be made.

According to the present invention in a first aspect there is provided an auto-nulling circuit comprising; an amplifier having one or more inputs; a sample/hold circuit connected as a first feedback loop between the amplifier output and a chosen input, the connection at the amplifier output being via switch means; a second feedback loop connected across the amplifier, the arrangement being such that whenever the first feedback loop is connected across the amplifier there is no D.C. feedback via the second loop; and control means for periodically actuating the switch means for a chosen period of time; whereby the sample/hold is arranged, when connected to the amplifier output, to sample the output voltage from the amplifier and also to apply at least a portion of this voltage to the chosen input as a correction voltage and, when disconnected from the amplifier output, to hold the correction voltage for a period of time.

In some embodiments of the invention the second feedback loop is resistive and is selectably connected by the switch means between a first position across the amplifier when a D.C. feedback loop is provided and a second position between the chosen amplifier input and ground such that a D.C. feedback loop is not provided.

Alternatively, the second feedback loop is one which introduces substantially no D.C. feedback across the amplifier, and may be permanently connected.

Preferably, the amplifier is a differential amplifier configured in differential mode or single ended inverting or non-invertng mode. The sample/hold circuit may include a holding capacitor.

In a second aspect the invention provides a method for use of the auto-nulling circuit as described above comprising; using as the or each input to the amplifier one or more lines through which a particular desired signal is being passed; using the control means to disconnect this signal in synchronism with actuating the switch means to connect the sample/hold loop, leaving only offset voltages on the line; sampling this offset voltage, and applying a correction voltage, and; holding this voltage and applying it as a correction voltage for a period of time when the desired signal is reconnected.

Thus, a signal is interrupted for only brief periods during which the offset is calculated, and then reconnected and its offset nulled.

When the amplifier is in differential mode the amplifier input to which the signal is not connected may be grounded if the offset on only one channel is to be measured. Alternatively, two channels may be connected, one to each input.

The method and circuit described are particularly useful in measuring instruments, for example power meters, where DC offsets can give false readings. By using sampling and holding techniques on the amplitude level display, an amplitude reading immediately before interruption of the circuit can be held on the display during the sampling portion of the nulling sequence, and a real time display restored upon reconnection of the signal.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which; Figure 1 shows an auto-nulling circuit according to the present invention and disposed in a differential amplifier configuration, Figure 2 shows an auto-nulling circuit disposed as an integrating amplifier, and Figure 3 shows a particular application of an autonulling circuit.

Referring to Figure 1 there is shown a circuit to null DC voltages. The circuit comprises two inputs to which respective voltages V1 and V2 may be applied, via respective resistors R1 and R2 to the inverting and noninverting inputs of a respective differential amplifier A1. The amplifier accordingly acts as a differential amplifier. The output of amplifier A1 is taken through a switch S2 to a first feedback loop comprising a sample and hold circuit including an amplifier A2 and a resistor R4.

The output of the sample/hold circuit is fed back in the first feedback loop to sum at the inverting input of the amplifier with a proportion of the input voltage V1. The sample/hold circuit further includes a hold capacitor C connected to ground as shown. A second output is taken from the amplifier A1 in a second feedback loop through a switch S1 and a feedback resistor R3 to its inverting input. A further resistor 2 ensures that the differential gain of the amplifier can be balanced and the amplifier acts as a differential amplifier.

In use, if the offsets on inputs V1 and/or V2 are to be nulled then any desired signals on inputs V1 and V2 are momentarily disconnected in order that only the residual DC offsets remain. These are then applied respectively to the inverting and non-inverting inputs of the amplifier A1 which produces an output signal dependent upon the difference between them. Switch S1 is opened for the period during which the input voltages are disconnected, and switches S2 and S3 closed. S3 is a switch connecting the output line of the system to earth and when closed ensures that resistor R3 is grounded.The output signal from amplifier A1 is accordingly routed through sample/hold amplifier A2 and also a charge is built up on capacitor C1 which is equal to the required correction voltage This correction voltage is added, via resistor R4 to the voltage- V1 and thus, by equalising all dc offsets brings the output from amplifier A1 to zero, i.e.

nulls the system. It is immediately seen that the system not only nulls DC offsets present on the inputs V1 and V2 but also any offsets present due to the effects of the amplifiers A1 and A2; hence the circuit may be used with low cost devices which may themselves have a significant offset voltage, without affecting the auto-nulling properties of the circuit. When the signals on lines V1 and V2 are reconnected then switches S2 and S3 are opened and switch S1 is closed. The voltage held on capacitor C1 is then applied to the inverting input of amplifier A1 to allow and compensate for the DC offsets.

By grounding inputs V2 or V1 then the circuit can be configured as respectively an inverting or a non-inverting amplifying arrangement.

The particular requirements of the sample/hold circuit are not particularly strenuous and basically it is only required to have acquisition and settling times such that the main- circuit function is not interrupted for too long. In some applications this is not critical and the sample/hold circuit can take as long as perhaps 0.5 to 1 second to sample. However, a sample time of a few milliseconds is generally simple to achieve in which case interruption of the main circuit is very brief. The sample period should always be long enough to allow the nulling loop to settle to a steady state.

As described above, the offset voltage introduced by the sample/hold circuit itself is not critical since this is always nulled by the loop. The hold period is slightly more critical since it should not be so long that the charge held on the hold capacitor C1 drops noticeably.

Too long a hold period between successive samples allows the capacitor charge to decay significantly and allows offset errors in the output to appear. However, the exact hold time selected will depend on many factors such as the size and dielectric material of the capacitor, the gain of the sample/hold feedback loop, the integrity of the leakage protection around the capacitor and the reverse leakage characteristic of the switch. In practice, a best value would be easily obtainable by a skilled operator.

Figure 2 shows a similar circuit to Figure 1 but in this case it is configured as an inverting integrator. In this case, a second capacitor C2 replaces the first feedback resistor R3. Additionally, there is no need for switches S1 and 53 since any DC components from the output will be blocked by the capacitor. Hence the capacitive feedback loop can be left in the system when sampling is done and accuracy is not significantly affected although the settling time of the nulling loop will be impaired.

The sample/hold feedback loop operates in the same way for Figure 2 as in the differential amplifier configuration of Figure 1. Switch S1 may however be included to speed up the nulling loop settling time if the time constant of the integrator causes the nulling period to be unacceptably long.

One particular application of the present invention is illustrated in Figure 3. The circuit is configured as a differential-input integrating amplifier as may be used in a control loop application. Two schematic devices 1 and 2 are shown which may for example be diode detectors.

The inverting and non-inverting inputs of the integrator are preceded by devices 1 and 2 respectively which have significant DC offsets (shown schematically as Vosl and Vos2). Hence the difference signal to be measured is added to these offsets. To measure accurately, the nulling system cancels the effect of the offsets in devices 1 and 2 and also those of the integrator and sample/hold amplifiers, leaving just the difference of the two input signals to be integrated.

A switch arrangement S4, controlled in synchronism with switch S1 is used to isolate the incoming signals from devices 1 and 2 whilst the nulling takes place.

The sample/hold feedback loop operates in an identical manner in the apparatus of Figure 3 and Figure 1.

Claims (10)

1. An auto-nulling circuit comprising; an amplifier having one or more inputs; a sample/hold circuit connected as a first feedback loop between the amplifier output and a chosen input, the connection at the amplifier output being via switch means; a second feedback loop connected across the amplifier, the arrangement being such that whenever the first feedback loop is connected across the amplifier there is no D.C. feedback via the second loop; and control means for periodically actuating the switch means for a chosen period of time; whereby the sample/hold is arranged, when connected to the amplifier output, to sample the output voltage from the amplifier and also to apply at least a portion of this voltage to the chosen input as a correction voltage and, when disconnected from the amplifier output, to hold the correction voltage for a period of time.

2. An auto-nulling circuit as claimed in claim 1 wherein the second feedback loop is resistive and is selectably connected by the switch means between a first position across the amplifier when a D.C. feedback loop is provided and a second position between the chosen amplifier input and ground such that a D.C. feedback loop is not provided.

3. An auto-nulling circuit as claimed in claim 1 wherein the second feedback loop is one which introduces substantially no D.C. feedback across the amplifier, and is permanently connected.

4. An auto-nulling circuit as claimed in any of the preceding claims wherein the amplifier is a differential amplifier configured in differential mode.

5. An auto-nulling circuit as claimed in any of claims 1 to 3 wherein the amplifier is a differential amplifier configured in single-ended inverting or non-inverting mode.

6. An auto-nulling circuit as claimed in any of the preceding claims, wherein the sample/hold circuit includes a holding capacitor.

7. A measuring instrument including an auto-nulling circuit as claimed in any of claims 1 to 6.

8. A method for use of an auto-nulling circuit as claimed in any of the preceding claims comprising; using as the or each input to the amplifier, one or more lines through which a particular desired signal is being passed; using the control means to disconnect this signal in synchronism with actuating the switch means to connect the sample/hold loop, leaving only offset voltages on the line; sampling this offset voltage, and applying a correction voltage, and; holding this voltage and applying it as a correction voltage for a period of time when the desired signal is reconnected.

9. An electrical circuit substantially as hereinbefore described with reference to, and as illustrated by, any one of Figures 1, 2 and 3 of the accompanying drawings.

10. A method for use of an auto nulling circuit substantially as hereinbefore described with reference to the accompanying drawings.