GB2210539A - Narrow band digital communications method and system - Google Patents

Abstract

Digital data radio communication between a transmitter and a receiver in which a receiver utilises a real time spectrum analyser 14 to search for and identify a digital binary data transmission. Each binary bit of said transmission comprises a sequence of frequency shifts in accordance with a predetermined code and timing (Figs 1, 2). A search for valid transmission is continuously performed at the receiver by testing a plurality of outputs from the real time spectrum analyser 14 to find (a) that which exhibits an amplitude variation with time that matches the erect predetermined code and (b) that which exhibits an amplitude variation with time which matches the inverse of the predetermined code. The erect and inverse signals are located and matches therebetween are identified in accordance with requirements that the frequency separation received is similar to a frequency shift employed at the transmitter, and that the timing of the received sequences is similar to that employed at the transmitter. <IMAGE>

Description

Narrow Band Digital Communications Method And Svstem This invention relates to the narrow bandwidth transmission of digital data by radio.

There are many instances where the data presented to a transmission system changes slowly. An example of this is data relating to the natural environment such as atmospheric temperature and pressure. In such cases very low data rates, and hence a narrow transmission bandwidth can be used. This invention provides a means of exploiting this situation so that a very low received signal power is sufficient to provide reliable communication. Thus, either a very high radio path loss can be accepted, as in tropospheric scatter propagation, or the transmitted signal power can be much reduced below that which is conventionally used.

When operating with a very narrow transmission bandwidth, it is necessary for the receiver to know accurately the transmitter frequency so that narrow bandwidth filtering may be used to recover the signal from the background noise. At v.h.f. and higher frequencies the frequency stability of conventional oscillators is insufficient to ensure that transmitter and receiver are tuned to the same frequency such that a transmission bandwidth of the order of 1Hz can be used.

In accordance with one aspect of the invention, there is provided a method of digital data radio communication between a transmitter and a receiver in which a receiver utilises a real time spectrum analyser to search for and identify a digital binary data transmission, each binary bit of said transmission comprising a sequence of frequency shifts in accordance with a predetermined code and timing in which a search for valid transmission is continuously performed at the receiver by testing a plurality of outputs from the real time spectrum analyser to find (a) that which exhibits an amplitude variation with time that matches the erect predetermined code and (b) that which exhibits an amplitude variation with time which matches the inverse of the predetermined code; comparing the erect and inverse signals located and identifying matches therebetween in accordance with requirements that the frequency separation received is similar to a frequency shift employed at the transmitter, and the timing of the received sequences is similar to that employed at the transmitter.

In accordance with another aspect of the invention, there is provided a digital data radio communication system between a transmitter and a receiver wherein the receiver utilises a real time spectrum analyser to search for and identify a digital binary data transmission, each binary bit of said transmission comprising a sequence of frequency shifts in accordance with a predetermined code and timing, including means at the receiver for continuously performing a search for the transmission by testing a plurality of outputs from the real time spectrum analyser to find (a) that which exhibits an amplitude variation with time that matches the erect predetermined code and (b) that which exhibits an amplitude varying with time which matches the inverse of said predetermined code; and including means at the receiver for comparing the erect and inverse signals located and identifying matches therebetween in accordance with requirements that the frequency separation received is similar to a frequency shift employed at the transmitter, and the timing of the received sequences is similar to that employed at the transmitter.

At the transmitter of a typical embodiment of the invention, each data bit to be transmitted is converted into a binary sequence. For a data bit polarity of "one" a particular sequence is chosen and for a data bit polarity of "zero" the logical inverse of that sequence is used. The radio transmitter carrier frequency is then caused to be narrow frequency-shift modulated by the successive sequences generated from the input data.

At the receiver the band of frequencies in which the signal is expected to lie, allowing for the anticipated inaccuracies of the transmitter and receiver oscillators, is applied to a real-time spectrum analyser with a resolution sufficient to separately filter the upper and lower shift frequencies of the signal. Typically this analyser would be implemented by means of the Fast Fourier Transform. Successive magnitude outputs from the spectrum analyser are stored in a memory for a period at least equal to the period of one binary sequence. This memory is then searched at close increments of frequency and time for an on-off signal sequence matching either the normal or inverted binary sequence expected.Initial confirmation of receipt of the signal is achieved when a match is obtained against normal polarity on one frequency, and against inverted polarity on a frequency either above or below the first, differing by an amount equal to the transmitted frequency shift. Further confirmation of valid reception is made by ensuring that a second match is obtained on the same pair of frequencies at a later instant in time separated by the duration of one binary sequence. Confirmation may be reinforced by similar checking of further sequences, if necessary.

Having established the correct frequency and timing of the signal, the receiver now recovers the sequence of data bits transmitted according to the polarity of each frequency-shift sequence received. Because the frequency and timing of the transmitter and receiver may drift, the matching process described previously is continued and, within permitted rates of change, the receiver tracks these changes. If the signal should fade out temporarily, then the receiver remains at its last settings of time and frequency until the signal reappears. If the duration of the signal loss exceeds a pre-determined period, the receiver reverts back to searching for a match anywhere in the expected band.

To overcome the effects of fading and interference which may cause errors in data bit detection, the data bits applied to the radio transmitter may be constructed from the information to be sent using an error correcting code. At the receiver, the sequence-matching process gives an indication of bit quality and, should the quality of a particular bit fall below a pre-determined threshold, this may be.signalled to the error correcting decoder as an erasure. Identification of erasures can greatly enhance the error correcting properties of the code used.

The invention will now be described by way of an example with reference to the accompanying drawings of which: Figure 1 is a graph showing the frequency shift sequence transmitted for a data bit polarity of "zero1,; Figure 2 is a graph showing the frequency shift sequence transmitted for a data bit polarity of "one"; Figure 3 is a block diagram representation of the transmitter sub-system; and Figure 4 is a block diagram representation of the receiver sub-system.

Figure 1 shows the frequency shift sequence radiated by the transmitted for a data bit polarity of "zero". It should be noted that the frequency shift is plus and minus 2.5Hz about the norminal carrier frequency fc, and that the duration of the sequence is seven seconds.

Figure 2 shows the sequence transmitted when the data bit polarity is "one". This sequence has the same shift and timing as that for "zero" polarity, but the sequence is inverted.

Figure 3 shows the transmitter sub-system in block diagram form. The information to be transmitted is formed into five bit blocks and these are fed into the Reed Muller encoder 1. The encoder generates a sixteen bit code word from each five bit information block and this is passed serially at a rate of one bit every seven seconds to the sequence generator 3 via line a. To facilitate block synchronisation at the receiver, transmission of the first bit of each code word is arranged to start at an instant which is an integer multiple of 112 seconds since a predefined instant of time (e.g. the start of the year).

It should be noted that 112 seconds is the time needed to transmit one sixteen bit code word. A real-time clock 4 is provided to give reference to absolute time. If no new information is presented for transmission to the Reed Muller encoder 1, then optionally, either the previous code word may be repeated, or an all zero code word generated. The objective is to ensure that at all times a code word of some form is being fed to the sequence generator 3. This ensures a continuous transmission onto which the receiver can maintain synchronisation.

The sequence generator 3 produces a binary serial output which is fed into the transmitter 6 via line 5 to produce a frequency shift modulated output of the form shown in Figure 1 or Figure 2 depending on whether the '1 11 11 current code bit polarity is respectively "zero" or one The transmitter 6 operates in the VHF band and generates the required power to feed the antenna 7.

All timing and frequency generation in the transmitter sub-system is under the control of a reference oscillator 8 which uses a temperature compensated crystal oscillator circuit.

Figure 4 shows in block diagram form the receiver sub-system. The radio receiver 10 selects and amplifies signals within the band of interest from the antenna 9.

The output of the receiver 11 contains signals in a frequency band of plus and minus 250Hz centred on 750Hz, and is a down-converted version of the radio frequency band expected to contain the wanted signal. The 512 Point Fast Fourier Transform (FFT) 14 operates on a sampled and digitised version of the receiver output on line 13 from the analogue to digital converter 12. The rate of input of complex samples to the FFT computation is 512 per second, giving an FFT output frequency resolution of about 1Hz. The FFT is computed four times per second to give overlap between successive outputs. The 512 signal magnitude output lines 15 are fed into the buffer memory 16. This is capable of storing twenty-eight successive sets of FFT outputs and can, therefore, be regarded as having a width of 512 words and a depth of twenty-eight.

It holds at any instant all FFT outputs for the previous seven seconds. As each new FFT output is fed into the buffer memory 16, the oldest set of seven seconds ago is discarded. Following each transfer of an FFT output data set into the buffer memory 16, the sequence identifier 18 accesses the memory via the interface lines 17 and performs a search over the FFT output for the past seven seconds, looking for a signal pattern which corresponds to either that shown in Figure 1 or Figure 2. This is done by regarding the frequency shift modulated signal as two complementary on/off sequences separated by 5HZ. A correlation is performed on each FFT output line over the previous twenty-eight outputs. Considering any one output line, the most recent sample is represented by XO, the next most recent by X1 and so on to X27 which is the oldest.The following two summations are then carried out: Y1 r (X0 + X1 + X2 + X3) + (X4 + X5 + X6 + X7) + (X8 + X9 + X10 + X11) + (X20 + X21 + X22 + X23) Y2 = (X12 + X13 + X14 + X15) + (X16 + X17 + X18 + X19) + (X24 + X25 + X26 + X27) Y1 is the summation of the FFT output samples corresponding to the times at which the signal would be on the upper frequency if a "zero" data bit had been received. Y2 is likewise the summation of the FFT output samples corresponding to the times at which the signal would be on the lower frequency if a "zero" data bit had been received.Two ratios R1 and R2 are then computed as below: R1 = Y1 R2 = Y2 Y2 Y1 R1 and R2 are computed and stored for each FFT output line. Now the values of R1 and R2 for each line are inspected, firstly to determine those which have a magnitude exceeding a predefined threshold. Then a search is made for those pairs of ratios which exceed the threshold and are separated by five FFT output lines (corresponding to the 5Hz frequency shift expected). For a pair to be acceptable they must also be complementary, that is, either R1 is on the higher frequency and R2 on the lower frequency, or vice-versa. If more than one pair of ratios is found which match the above criteria, then the pair with the highest value of R1 multiplied by R2 is chosen.The pair of ratios so chosen (if any) is then stored together with their frequencies, which are represented by the FFT output lines on which they occurred.

The whole correlation process on all FFT lines is repeated as described above for twenty-eight successive FFT computations. At the end of this period the following information is output from the sequence identifier functional block 18 on lines 19, 20, 21 and 22 Line 19 carries information which represents the timing phase of the received sequence relative to the sequence identifier 18 timing. This is derived from a count value indicating at which FFT output time the selected value of R1 multiplied by R2 was a maximum.

Line 20 carries the polarity of the data bit indicated by the selected pair R1 and R2. The polarity is "zero" if R1 is on the higher frequency and "one" if R1 is one the lower frequency.

Line 21 carries information indicating the quality of the received data bit. This is the maximum value of R1 multiplied by R2 at the timing phase indicated on line 19.

If no valid bit has been received then the quality level is set to zero.

Line 22 carries information indicating the received frequency of the binary sequence from which the information on lines 19, 20 and 21 is derived. It is the number of the FFT output line (a value between zero and 511) on which the higher frequency of the selected pair R1 and R2 was found.

Output line 19, 20, 21 and 22 from the sequence identifier 18 are coupled to the data verification and drift tracking functional block 23. This functional block operates in either an acquisition mode or a tracking mode.

Initially it operates in the acquisition mode. Once a valid signal has been identified and verified, it switches to the tracking mode and provides output data derived from the received message code bits.

In acquisition mode the data verification and drift tracking functional block 23 tests the information transmitted to it from the sequence identifier 18 for the presence of a valid signal. This is done by observing whether successive outputs from the sequence identifier 18 show repetitive reception of valid data bits with approximately the same frequency and timing phase. When a predetermined number of bits are consecutively received which meet these criteria, the data verification and drift tracking functional block 23 switches to the tracking mode.

In the tracking mode the polarity and quality of data bits which are received with a frequency and timing phase closely matching those of data bits received in the recent past are fed to the Reed-Muller decoder a6 via lines 24 and 25. In effect, the receiver tracks slow variations in frequency and timing of the signal caused by drift in the reference oscillators used in the transmitter and receiver. If the rate of reception of valid data bits falls below a pre-determined threshold, then it is presumed that the signal has been lost and the data verification and drift tracking functional block 23 reverts to the acquisition mode.

The Reed-Muller decoder 26 assembles the received data bits into sixteen bit blocks and decodes them into five bit information words, applying any necessary error correction in the process. The decoder is capable of correcting both hard errors and erasures in the received data code word. A hard error occurs when a code bit polarity is incorrectly decoded. An erasure occurs when the quality of a code bit falls below an acceptable level.

With the Reed-Muller code used, correct decoding is achieved providing the following relationship holds:8 > (2 x A) + B where:- A - number of hard errors, and B - number of erasures The five bit message word from the Reed-Muller decoder 26 is presented on the output line 27. Along with each message word a quality value is provided on line 28 which is computed from the number of hard errors and erasures corrected in the received code word.

The Reed-Muller decoder 26 achieves frame synchronisation to the received data code words by noting the absolute time of reception of each code bit. The first bit of a code word is that which is received at a time nearest to an integer multiple of 112 seconds since a pre-defined instant in time (for example, the start of the year). This allows for an error of plus or minus 3.5 seconds between the absolute time references at the transmitter and receiver. Absolute time information is provided in the receiver sub-system by the real-time clock 30, from which information is fed into the Reed-Muller decoder 26 via line 29.

All oscillator and timing signals used by the receiver sub-system are controlled by the temperature compensated crystal oscillator 31.

In a typical implementation of the receiver subsystem given in the example above, the functions provided by blocks 14, 16, 18, 23, 26 and 30 as shown in Figure 4, would be performed by a digital signal processor.

Claims (12)

Claims:

1. A method of a digital data radio communication between a transmitter and a receiver in which a receiver utilises a real time spectrum analyser to search for and identify a digital binary data transmission, each binary bit of said transmission comprising a sequence of frequency shifts in accordance with a predetermined code and timing in which a search for valid transmission is continuously performed at the receiver by testing a plurality of outputs from the real time spectrum analyser to find (a) that which exhibits an amplitude variation with time that matches the erect predetermined code and (b) that which exhibits an amplitude variation with time which matches the inverse of the predetermined code; comparing the erect and inverse signals located and identifying matches therebetween in accordance with requirements that the frequency separation received is similar to a frequency shift employed at the transmitter, and the timing of the received sequences is similar to that employed at the transmitter.

2. A method as claimed in Claim 1 wherein after identifying valid transmission, the transmitted data bits are recovered at the receiver according to the frequency order in which the erect and inverted matches against the predetermined code are obtained.

3. A method as claimed in Claim 1 or a wherein upon recognition of a valid transmission, the receiver is arranged to track slow variations in frequency and timing of the received code sequences.

4. A method as claimed in Claims 1, 2 or 3 wherein the transmitter is arranged to despatch the message encoded according to an error correcting code, and the receiver includes a decoder capable of correcting errors and erasures in the received data up to the capability of the code used.

5. A method as claimed in Claim 4 wherein the receiver is arranged to identify and detect an erasure by means of inadequate correlation of the received signal against the expected sequence, or by the received sequence having timing or a frequency outside that currently being transmitted.

6. A method of a digital data radio communication substantially as shown in and as herein before described with reference to the accompanying drawings.

7. A digital data radio communication system between a transmitter and a receiver wherein the receiver utilises a real time spectrum analyser to search for and identify a digital binary data transmission, each binary bit of said transmission comprising a sequence of frequency shifts in accordance with a predetermined code and timing, including means at the receiver for continuously performing a search for the transmission by testing a plurality of outputs from the real time spectrum analyser to find (a) that which exhibits an amplitude variation with time that matches the erect predetermined code and (b) that which exhibits an amplitude varying with time which matches the inverse of said predetermined code; and including means at the receiver for comparing the erect and inverse signals located and identifying matches therebetween in accordance with requirements that the frequency separation received is similar to a frequency shift employed at the transmitter, and the timing of the received sequences is similar to that employed at the transmitter.

8. A system as claimed in Claim 7 including at the receiver means which, upon recognition of a valid transmission, is arranged to track slow variations in frequency and timing of the received code sequences.

9. A system as claimed in Claims 7 or 8 wherein the transmitter is arranged to despatch the message encoded according to an error correcting code, and the receiver includes a decoder capable of correcting errors and erasures in the received data up to the capability of the code used.

10. A system as claimed in Claim 9 wherein the receiver includes means capable of identifying and detecting an erasure by means of inadequate correlation of the received signal against the expected sequence, or by the received sequence having timing or a frequency outside that currently being transmitted.

11. A digital'data radio communication transmitter substantially as shown in and as hereinbefore described with reference to Figure 3 of the accompanying drawings.

12. A digital data radio communication receiver substantially as shown in and as herein before described with reference to Figure 4 of the accompanying drawings.