GB2208967A - Junction field effect transistor - Google Patents
Junction field effect transistor Download PDFInfo
- Publication number
- GB2208967A GB2208967A GB8819748A GB8819748A GB2208967A GB 2208967 A GB2208967 A GB 2208967A GB 8819748 A GB8819748 A GB 8819748A GB 8819748 A GB8819748 A GB 8819748A GB 2208967 A GB2208967 A GB 2208967A
- Authority
- GB
- United Kingdom
- Prior art keywords
- polysilicon
- drain
- source
- gate
- jfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000002019 doping agent Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of making a low-noise, junction field-effect transistor is provided, in which locations for a gate, source and drain are defined by simultaneously defining corresponding locations in an oxide layer (16) covering a silicon wafer, etching the oxide from the locations to leave gaps, and filling the gaps with polysilicon (30, 32, 34). The polysilicon then has suitable dopants deposited in it, such as phosphorus and boron, and a subsequent heat treatment causes the dopants to diffuse into the silicon to form the source (22), gate (20) and drain (24). Electrical connection to the polysilicon over the source and drain may be made by metal contacts. The topology of the JFET is desirably such that metal contacts do not cross over any p/n junctions and are @ from active surface regions of the device. <IMAGE>
Description
Transistor
This invention relates to transistors and in particular to junction field-effect transistors (JFETs) and to their method of manufacture.
A junction field-effect transistor (JFET), otherwise known as a junction-gate field-effect transistor, includes a doped semiconductor region with highly doped zones referred to as the source and the drain, and an intervening doped zone referred to as the gate doped so that there are rectifying (p-n) junctions between it and both the source and the drain. The voltage applied to the gate may be used to control the current flow between the source and the drain. JFETs may be used in amplifiers, and are especially useful in low-noise amplifiers, for example in alarm systems such as fire alarms. However, in some cases, it has been found that noise signals may be generated by a
JFET, in particular random telegraph signal (RTS) noise in which a signal switches at random intervals between two well-defined levels which may exceed the noise level due to other causes by ten or twenty times.Even though the interval between successive RTS noise signals may be more than a day, this is not satisfactory, as it can lead to the generation of false alarms.
According to the present invention there is provided a method of making a JFET on a silicon substrate including the operations of simultaneously defining the locations of the source, drain and gate zones, by defining regions of an oxide layer covering the substrate; removing the regions of the oxide layer so defined, to leave gaps, and filling the gaps with polysilicon; depositing dopant materials into the polysilicon in the filled gaps; and heat treating so that the dopant materials diffuse into the silicon substrate to create the source, drain and gate.
The locations may be defined using a common mask, or by an electron beam writing process. Preferably the polysilicon overlaps the oxide layer adjacent to the filled gaps. The dopant materials are preferably phosphorus for the source and the drain zones and boron for the gate zone, as boron diffuses more slowly in silicon than does phosphorus, creating a shallower gate zone. The dopant materials may be deposited by an ion beam implantation technique. The heat treatment may be performed at between about 80000 and 12000C, and may be performed in two stages, the first stage being performed before the second dopant material is deposited.
Desirably the arrangement of the doped zones and of subsequently-applied metal conductors is such that there are no metal conductors crossing over junctions, and no metal conductors near active surface regions of the transistor. In this specification the term active surface region means a region adjacent the surface of the doped semiconductor and between any two zones, such as between the gate and the source, where the distance between the zones is less than about 25 micrometres.
The metal conductors may be of aluminium or of titanium; desirably titanium is used to make electrical contact to the polysilicon regions.
The invention also provides a JFET made by the method defined above. Such a JFET can be expected to produce far less PTS noise than a conventional JFET; furthermore it may have a lower value of the product of thermal noise and input capacitance of the gate.
The invention will now be described by way of example only and with reference to the accompanying drawings, in which:
Figures la to ld show diagrammatic sectional views of
a JFET at successive stages in the
process of manufacture;
Figure 2 shows a diagrammatic plan view of a
JFET; and
Figure 3 shows a sectional view along the
line III-III of Figure 2.
Referring to Figure la, an n-channel JFET is formed on a silicon wafer 10 comprising a p+ substrate 12 and an epitaxial n-type layer 14, covered by a layer of oxide 16.
The region in which the JFET is to be defined is surrounded by a p+ isolating wall 18 which extends between the substrate 12 and the oxide layer 16. By means of a single mask (not shown), portions of the oxide layer 16 are defined corresponding to the subsequent locations of the gate 20, source 22, drain 24 and the edge 26 of the JFET (see Figure lid), and these portions are etched away to leave gaps 28.
A layer of undoped polysilicon is then deposited over the entire exposed surface of the wafer 10; this is then etched away to leave strips 30,32,34 and 36 of polysilicon filling the former gaps 28 and slightly overlapping the oxide layer 16, as shown in Figure lb.
The exposed surface is then oxidised, and then a layer 38 of oxide deposited by chemical vapour deposition, typically about a half or a third a micrometre thick. Gaps 40 are etched in the layer 38 above the strips 32 and 34; and phosphorus is implanted by an ion beam process into the exposed surface, in particular into the strips 32 and 34 of polysilicon. The wafer 10 is then as shown in Figure lc.
Another layer of oxide is then deposited over the exposed surface, and gaps etched above the strips 30 and 36. Boron is then implanted into the exposed surface and in particular the strips 30 and 36 of polysilicon. A further layer of oxide is then deposited, the layer 38 and all the subsequent layers creating the layer 42, and the wafer 10 is heat treated at about 10000C. The dopants, phosphorus and boron, diffuse through the polysilicon strips 30,32,34 and 36 into the epitaxial layer 14 where they define the gate 20, source 22, drain 24 and the edge 26 zones of the JFET. The wafer 10 is then as shown in
Figure ld. Because phosphorus diffuses faster in silicon than does boron, the source 22 and drain 24 zones are deeper than the edge zone 26 and the gate zone 20. The edge 26 is p+, as is the isolating wall 18, so that these merge together.The dopants deposited within the oxide layer 42 remain trapped, and do not diffuse into the underlying material.
Electrical contact to the gate 20, the source 22 and the drain 24 may be made by etching gaps in the oxide layer 42 above the polysilicon strips 30,32 and 34 at locations where contact is to be made, and depositing a metal such as titanium in the gaps (the metal will in practice be deposited all over the exposed surface, heat-treated, and then etched away everywhere except where electrical contacts are desired).
It will be appreciated that the process described above may be used to make JFETs of any desired topology.
One such JFET is shown in Figures 2 and 3, to which reference is now made, defined on a silicon wafer 50 most of whose surface is covered by an insulating layer 52 of silicon dioxide which is not shown in Figure 2 for clarity.
The JFET comprises a rectangular region 54 of epitaxial n-type silicon below which is a p+ substrate 55 and around which is an isolating wall 56 of p+ extending up from the substrate 55. Within the rectangular region 54 are also defined further p+ isolating pillars 57, 58, 59, extending up from the substrate 55: two pillars 57 extend inwardly from the wall 56 directly opposite each other, a third pillar 58 is midway between the pillars 57, and two other pillars 59 are spaced apart on a line parallel to but spaced away from the line between the pillars 57.
A p+ gate strip 60 is defined near the surface of the region 54 extending along a zig-zag line connecting all the pillars 57, 58, 59 in succession. A source 62 is defined by an n+ zone near the surface of the region 54,
U-shaped in plan, whose limbs extend between portions of the gate 60 towards the pillars 59. A drain 64 is defined by another n+ zone, E-shaped in plan, whose outer limbs extend between portions of the gate 60 and the wall 56 towards the pillars 57, and whose central limb extends between portions of the gate 60 towards the pillar 58. A p+ edge strip 66 is defined around the inside edge of the isolating wall 56, and merges with the gate 60 on top of the isolating pillars 57.
The gate 60, the source 62, the drain 64 and the edge strip 66 are formed in the way described above in relation to Figure la to d; consequently a corresponding strip 70, 72, 74 and 76 of polysilicon (not shown in Figure 2) extends along the upper surface of each, and is enclosed within the oxide layer 52. The layer 52 covers the entire region shown in Figure 2 apart from two narrow slots 78 and 79 which provide for electrical connection to the polysilicon above the portions of the source 62 and the drain 64 remote from their limbs. Two square titanium contacts 82 and 84 overlie the oxide layer 52 above the region 54 and the said portions of the source 62 and the drain 64, filling the slots 78 and 79.
The JFET of Figure 2 and 3 operates in a conventional manner, external electrical connections being made to the contacts 82 and 84 (for connection to the source 62 and drain 64) and to the substrate 55 (for connection to the gate 60 via the pillars 57, 58, 59). The active surface regions of the device are the portions of region 54 near the surface, between the source or drain zones, 62 or 64, and the gate 60 - for example the portion marked A. The portions of region 54 between the non-limb part of the source or drain zone, 62 or 64, and the edge strip 66 are not active regions because the separations involved are too large - typically more than 20 micrometres - for example the portion marked B. The edge strip 66 ensures that the gate 60, source 62, and drain 64 zones of the device are at a well-defined separation from the isolating wall 56.
It will be observed that the metal contacts 82 and 84 do not cross over any p/n junctions, and are not near the active surface regions of the device.
In a modification (not shown) of the JFET of Figures 2 and 3, titanium strips are deposited in slots in the oxide layer 52 above the polysilicon strips 70,72 and 74 along the whole length of each (including the slots 78 and 79).
Aluminium contacts similar to the contacts 82 and 84 overlie the oxide layer 52 and are in contact with the titanium in the slots 78 and 79, and hence with the source 62 and drain 64.
Claims (7)
1. A method of making a JFET on a silicon substrate including the operations of simultaneously defining the locations of the source, drain and gate zones, by defining regions of an oxide layer covering the substrate; removing the regions of the oxide layer so defined, to leave gaps, and filling the gaps with polysilicon; depositing dopant materials into the polysilicon in the filled gaps; and heat treating so that the dopant materials diffuse into the silicon substrate to create the source, drain and gate.
2. A method as claimed in Claim 1 wherein the polysilicon is deposited so as to overlap the oxide layer adjacent to the filled gaps.
3. A method as claimed in Claim 1 or Claim 2 wherein the heat treatment is performed in two stages, the first stage being performed before a second dopant material is deposited.
4. A method as claimed in any one of the preceding
Claims wherein the arrangement of the doped zones and of subsequently-applied metal conductors is such that there are no metal conductors crossing over junctions, and no metal conductors near active surface regions of the transistor.
5. A method as claimed in any one of the preceding Claims wherein titanium conductors are provided to make electrical contact to the polysilicon.
6. A method of making a JFET on a silicon substrate substantially as hereinbefore described with reference to and as shown in the accompanying drawings.
7. A JFET made by a method as claimed in any one of the preceding Claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB878719842A GB8719842D0 (en) | 1987-08-21 | 1987-08-21 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8819748D0 GB8819748D0 (en) | 1988-09-21 |
| GB2208967A true GB2208967A (en) | 1989-04-19 |
Family
ID=10622645
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB878719842A Pending GB8719842D0 (en) | 1987-08-21 | 1987-08-21 | Transistor |
| GB8819748A Withdrawn GB2208967A (en) | 1987-08-21 | 1988-08-19 | Junction field effect transistor |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB878719842A Pending GB8719842D0 (en) | 1987-08-21 | 1987-08-21 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8719842D0 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008024655A3 (en) * | 2006-08-22 | 2008-05-22 | Dsm Solutions Inc | Complementary silicon-on- insulator (sod junction field effect transistor and method of manufacturing |
| WO2008134225A2 (en) * | 2007-04-27 | 2008-11-06 | Dsm Solutions, Inc. | Integrated circuit switching device, structure and method of manufacture |
| EP2038934A2 (en) * | 2006-06-12 | 2009-03-25 | Dsm Solutions, Inc. | Scalable process and structure for jfet for small and decreasing line widths |
| US7629812B2 (en) | 2007-08-03 | 2009-12-08 | Dsm Solutions, Inc. | Switching circuits and methods for programmable logic devices |
| US7646233B2 (en) | 2006-05-11 | 2010-01-12 | Dsm Solutions, Inc. | Level shifting circuit having junction field effect transistors |
| US7692220B2 (en) | 2007-05-01 | 2010-04-06 | Suvolta, Inc. | Semiconductor device storage cell structure, method of operation, and method of manufacture |
| US7710148B2 (en) | 2008-06-02 | 2010-05-04 | Suvolta, Inc. | Programmable switch circuit and method, method of manufacture, and devices and systems including the same |
| US7727821B2 (en) | 2007-05-01 | 2010-06-01 | Suvolta, Inc. | Image sensing cell, device, method of operation, and method of manufacture |
| US7764137B2 (en) | 2006-09-28 | 2010-07-27 | Suvolta, Inc. | Circuit and method for generating electrical solutions with junction field effect transistors |
| US7943971B1 (en) | 2008-12-17 | 2011-05-17 | Suvolta, Inc. | Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture |
| US7968393B2 (en) | 2006-10-31 | 2011-06-28 | Suvolta, Inc. | Semiconductor device, design method and structure |
| US8035139B2 (en) | 2007-09-02 | 2011-10-11 | Suvolta, Inc. | Dynamic random access memory having junction field effect transistor cell access device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3837935A (en) * | 1971-05-28 | 1974-09-24 | Fujitsu Ltd | Semiconductor devices and method of manufacturing the same |
| GB2057760A (en) * | 1979-08-30 | 1981-04-01 | Seiko Instr & Electronics | Integrated circuit device and method of making the same |
-
1987
- 1987-08-21 GB GB878719842A patent/GB8719842D0/en active Pending
-
1988
- 1988-08-19 GB GB8819748A patent/GB2208967A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3837935A (en) * | 1971-05-28 | 1974-09-24 | Fujitsu Ltd | Semiconductor devices and method of manufacturing the same |
| GB2057760A (en) * | 1979-08-30 | 1981-04-01 | Seiko Instr & Electronics | Integrated circuit device and method of making the same |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7646233B2 (en) | 2006-05-11 | 2010-01-12 | Dsm Solutions, Inc. | Level shifting circuit having junction field effect transistors |
| EP2038934A2 (en) * | 2006-06-12 | 2009-03-25 | Dsm Solutions, Inc. | Scalable process and structure for jfet for small and decreasing line widths |
| EP2038934A4 (en) * | 2006-06-12 | 2010-10-13 | Dsm Solutions Inc | Scalable process and structure for jfet for small and decreasing line widths |
| WO2008024655A3 (en) * | 2006-08-22 | 2008-05-22 | Dsm Solutions Inc | Complementary silicon-on- insulator (sod junction field effect transistor and method of manufacturing |
| US7764137B2 (en) | 2006-09-28 | 2010-07-27 | Suvolta, Inc. | Circuit and method for generating electrical solutions with junction field effect transistors |
| US7968393B2 (en) | 2006-10-31 | 2011-06-28 | Suvolta, Inc. | Semiconductor device, design method and structure |
| WO2008134225A3 (en) * | 2007-04-27 | 2009-05-22 | Dsm Solutions Inc | Integrated circuit switching device, structure and method of manufacture |
| WO2008134225A2 (en) * | 2007-04-27 | 2008-11-06 | Dsm Solutions, Inc. | Integrated circuit switching device, structure and method of manufacture |
| US7727821B2 (en) | 2007-05-01 | 2010-06-01 | Suvolta, Inc. | Image sensing cell, device, method of operation, and method of manufacture |
| US7692220B2 (en) | 2007-05-01 | 2010-04-06 | Suvolta, Inc. | Semiconductor device storage cell structure, method of operation, and method of manufacture |
| US7629812B2 (en) | 2007-08-03 | 2009-12-08 | Dsm Solutions, Inc. | Switching circuits and methods for programmable logic devices |
| US8035139B2 (en) | 2007-09-02 | 2011-10-11 | Suvolta, Inc. | Dynamic random access memory having junction field effect transistor cell access device |
| US7710148B2 (en) | 2008-06-02 | 2010-05-04 | Suvolta, Inc. | Programmable switch circuit and method, method of manufacture, and devices and systems including the same |
| US7943971B1 (en) | 2008-12-17 | 2011-05-17 | Suvolta, Inc. | Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8719842D0 (en) | 1987-09-30 |
| GB8819748D0 (en) | 1988-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4314857A (en) | Method of making integrated CMOS and CTD by selective implantation | |
| US4819045A (en) | MOS transistor for withstanding a high voltage | |
| US4103415A (en) | Insulated-gate field-effect transistor with self-aligned contact hole to source or drain | |
| EP0130736A2 (en) | Processes for making integrated circuit single FET and storage capacitor memory cells | |
| US4659428A (en) | Method of manufacturing a semiconductor device and semiconductor device manufactured by means of the method | |
| US3958323A (en) | Three mask self aligned IGFET fabrication process | |
| EP0227085A2 (en) | A method of manufacturing IGFETs having minimal junction depth using epitaxial recrystallization | |
| KR970054231A (en) | Nonvolatile Memory Cells and Manufacturing Method Thereof | |
| GB2208967A (en) | Junction field effect transistor | |
| US5773330A (en) | Semiconductor device and method for fabricating the same | |
| GB2381122A (en) | Trench isolation | |
| US4276099A (en) | Fabrication of infra-red charge coupled devices | |
| US4181537A (en) | Method of fabricating an insulated gate field effect device | |
| CA1124408A (en) | Method of producing a metal-semiconductor field-effect transistor | |
| GB2347014A (en) | Vertical power MOS / IGBT devices | |
| US4455742A (en) | Method of making self-aligned memory MNOS-transistor | |
| JPH06260506A (en) | Semiconductor element insulated dielectrically and its preparation | |
| KR920001750A (en) | Semiconductor device and manufacturing method thereof | |
| US5726082A (en) | Semiconductor device and method for fabricating the same | |
| KR0146864B1 (en) | Method for manufacturing semiconductor device | |
| EP0233791A2 (en) | Insulated gate field effect transistor and method of manufacture thereof | |
| US4345365A (en) | Method for fabricating an integrated circuit | |
| KR970008575A (en) | Manufacturing method of complementary MOS transistor | |
| US4517728A (en) | Manufacturing method for MIS-type semiconductor device | |
| GB2208966A (en) | Junction field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |