GB2208728A

GB2208728A - Digital processing system with multi data buses

Info

Publication number: GB2208728A
Application number: GB8819083A
Authority: GB
Inventors: Harvey Lee Kasdan; John Liberty
Original assignee: International Remote Imaging Systems Inc
Current assignee: Iris International Inc
Priority date: 1987-08-14
Filing date: 1988-08-11
Publication date: 1989-04-12
Also published as: FR2619462A1; GB8819083D0; DE3827313A1; AU2096388A; JPH0194470A

Description

1 A 2208720 PATENT A DIGITAL PROCESSING SYSTEM WITH MULTI-DATA BUSES

Technical'Field

The present invention relates to a digital processing system with multi-data buses, and more particularly. to a video image processor for processing a video image wherein said video image processor has a plurality of processor modules and a plurality of memory modules and a plurality of data buses interconnecting the plurality of memory and processor modules.

Backaround of the Invention

Digital processors are well-known in the art. They can be used for a variety of purposes. One purpose is to process a video image. Typically, a video image is supplied from an analog source, such as a video camera. The analog video signal from the video source is digitized. The digitized video image is then stored in a digital memory and is processed by a digital processor.

Because a video image comprises a large number of pixels or video image points, the amount of data which must be processed by a video processor is large. Heretofore, no video processor has addressed the 7 is problem of handling the large volume of data involved in image processing.

The following U.S. patents describe digital processors generally: U.S. Patent No. 4,542,455; 4,503,511; 4,594,655; 4,327,355; 4,346,438; and 4, 467,409. Although U.S. Patent No. 4,467,409 describes a flexible computer architecture, it does not address the particular problems of handling a large volume of data efficiently, and particularly in a video image processing environment.

Summarv of the Invention In the present invention, a digital processing system is disclosed. The system comprises a plurality of digital electronic modules. Each of the modules has a communication means. The modules process and store data. A plurality of data buses interconnect the plurality of modules. Each data bus has a plurality of communication paths. A master controller means is connected to a control bus, which has a plurality of communication paths. The control bus interconnects the master controller means to each one of the modules. The master controller means controls the operation of the plurality of modules by passing control signals along the control bus. In each module there is also provided means responsive to the control signals from 3 the control bus for connecting the communication means of that module to one or more of the data buses.

Brief Description of the Drawings

Figure 1 is a schematic block diagram of an imaging system using the video image processor of the present invention.

Figure 2 is a block diagram of the video image processor of the present invention, shown with a plurality of modules, and a plurality of data buses.

Figure 3 is a schematic block diagram of the portion of each module of the video image processor of the present invention with communication means, and logic control means to interconnect one or more of the data buses to the module.

Figure 4 is a detail circuit diagram of one implementation of the logic unit shown in Figure 3.

Figures 5(a-c) are schematic block diagrams of various possible configurations connecting the modules to the data buses.

Figure 6 is a schematic block diagram of another embodiment of a video image processor of the present invention shown with a plurality of data buses which can be electronically switched.

Figure 7 is a schematic block diagram of the portion of the video image processor shown in Figure 6 1 1 is showing the logic unit and address decode unit and the switching means to electronically switch the data buses of the video image processor shown in Figure 6.

Figure 8(a-c) show various possible embodiments as a result of switching the data buses of the video image processor shown in Figure 6.

Figure 9 is a detail circuit diagram of a portion of the switch and logic unit of the video image processor shown in Figure 6.

Figure 10 is a schematic block diagram of the video processor module of the video image processor shown in Figures 2 or 6.

Figure 11 is a schematic block diagram of an image memory module of the video image processor shown in Figures 2 or 6.

Figure 12 is a schematic block diagram of a morphological processor module of the video image processor shown in Figures 2 or 6.

Figure 13 is a graphic controller module of the video image processor shown in Figures 2 or 6.

Figure 14 is a block schematic diagram of the master controller of the video image processor shown in Figures 2 or 6.

Figure 15 is a circuit diagram of another implementation of a logic unit.

1 1 petailed Description of Drawings

Referring to Figure 1 there is shown an imaging system 8 using the video image processor 10 of the present invention. The imaging system 8 comprises the video image processor 10, which receives analog video signals from a color camera 12. The color camera 12 is optically attached to a fluorescent illuminator 14 which is focused through a microscope 16 and is directed at a stage 18. A source of illumination 20 provides the necessary electromagnetic radiation. The video imaging processor 10 communicates with a host computer 22. In addition, the host computer 22 has software 24 stored therein to operate it. Finally, a full color monitor display device 26 receives the output of the video image processor 10.

There are many uses for the video image processor 10. In the embodiment shown in Figure 1, the imaging system 8 is used to analyze biological specimen, such as constituents of blood. The biological specimen is mounted on a slide and is placed on the stage 18. The video image of the slide as taken by the color camera 12 through the microscope 16 isprocessed by the video image processor 10 of the present invention.

In preferred embodiment, the host computer 22 is a Motorola 68000 microprocessor and communicates with the video image processor 10 of the present invention via a is 1 r k_ is Q-bus. The Q-bus is a standard communication protocol developed by Digital Equipment Corporation.

As shown in Figure 2, the video image processor 10 comprises a master controller 30 and a plurality of electronic digital modules. Shown in Figure 2 are a plurality of processor modules: the video processor 34, graphic controller processor 36. morphological processor 40, and a plurality of image memory modules: image memory modules 38a, 38b and 38c. The image. memory modules store data which is representative of the video images. The processor nodules process the data or the video images. The master controller 30 communicates with each one of the plurality of digital modules (34, 36, 38 and 40) via a control bus 32. In addition, the plurality of digital modules (34, 36, 38 and 40) communicate with one another via a plurality of data buses 42.

In the video image processor 10 of the present invention, the master controller 30 controls the operation of each one of the plurality of digital modules (34, 36, 38 and 40) by passing control signals along the control bus 32. The bus 32 comprises a plurality of lines. The bus 32 comprises 8 bit lines for address, 16 bit lines for data, 4 bit lines of control, one line for vertical sync and one line for horizontal sync. In addition, there are numerous power and ground lines. The 4 bits of control include a signal for clock, ADAV, CMD, and WRT (the function of these control signals will be described later).

The plurality of data buses 42, which interconnect the modules (34, 36, 38 and 40) with one another, comprise nine a bit wide data buses 42. The nine data buses 42 are designated as 42A, 42B, 42C, 42D, 42E, 42F, 42G, 42H, and 421, respectively.

Within each module (34, 36, 38 and 40) is a communication means 54. Further, within each module a logic unit means 52 which is responsive to the control signals on the control bus 32 for connecting the communication means 54 of each module to one or more of the data buses 42.

Referring to Figure 3 there is shown a schematic block diagram of the portion of each of the modules which is responsive to the control signals on the control bus 32 for interconnecting one or more of the data buses 42 to the communication means 54 within each of the modules. Shown in Figure 3 is an address decode circuit 50. The address decode circuit 50 is connected to the eight address lines of the control bus 32. The address decode circuit 50 also outputs a signal 56 which activates its associated logic unit 52. Since each logic unit 52 has a unique address, if the address lines present on the address decode 50 matches the is address for that particular logic unit 52, the address decode 50 would send a signal 56 to activate that logic unit 52. Within each module, there can be a plurality of logic units 52 each with an associated address decoder 50. Each of the plurality of logic units 52 can perform different tasks.

The logic unit 52 receives the 16 bits of data from the 16 bits of data portion of the control bus 32. In addition, the logic unit 52 can also be connected to the four control lines: clock, ADAV, CMD, WRT, as previously described, of the control bus 32 and vertical sync and horizontal sync. The logic unit 52 will then control the operation of a plurality of tristate transceivers 54A, 54B, 54C, 54D, 54E, 54F, 54G and 541. This being understood that there are eight individual tri-state transceivers 54 for the group of tri-state transceivers 54A, and eight individual tristate transceivers for the group of tri-state transceivers 54B, etc. The function of the tri-state transceivers 54 is to connect one or more of the data buses 42A to functions within the module of which the logic unit 52 and address decode circuit 50 is a part thereof. In addition, within the module, a crosspoint switch 58 may be connected to all of the outputs of the tri-state transceivers 54 and multiplex the 1 1 -g- plurality of tri-state transceivers 54 into a single 8 bit wide bus 60.

Referring to Figure 4 there is shown a simplistic example of the address decoder 50, the logic unit 52, and one of the group of transceivers 54A interconnecting with the bus 42A. As previously stated, the eight address signal lines of the control bus 32 are supplied to the address decoder 50. If the address supplied on the address lines of the control bus 32 correctly decodes to the address of the logic unit 52, the address decoder 50 sends a signal 56 going high which is supplied to the logic unit 52. The address decode circuit 50 can be of conventional design.

Logic unit 52 comprises two AND gates 62A and 62B whose outputs are connected to J-K flipflop 64a and 64B respectively. The AND gates 62A and 62B receive at one of the inputs thereof the control signal 56 from the address decoder 50. The other input to the AND gates 62A and 62B are from the data lines of the control bus 32. If the address decoder 50 determines that the logic unit 52 is to be activated, as determined by the correct address on the address lines of the control bus 32, the control signal 56 going high gates in to the flipflop 64A and 64B the data present on the data lines of the control bus 32. The output of the J-K flipflop is 64A and 64B are used to control the eight tri-state transceivers 54A0... 54A7. Each of the eight tri-state transceivers has as one terminal thereof connected to one of the eight bit communication paths of the bus 42A. The other terminal of each of the tri-state transceivers 54A is connected to electronic elements within the module.

The tri-state transceivers 54A, as the name suggests, has three states. The transceivers 54A can provide communication to the data bus 42A. The tristate transceivers 54A can provide data communication from the data bus 42A. In addition, the tri-state transceivers 54A can be in the open position in which case no communication occurs to or from the data bus 42A. As an example, the tri-state transceivers 54A are components manufactured by Texas Instruments designated as 74AS620. These tri-state transceivers 54A receive two inputs. If the inputs have the combination of 0 and 1, they denote communication in one direction. If the tri-state transceivers receive the inputs of 1 and 0, they denote communication in the opposite direction. If the tri-state transceivers 54A receive 0 0 on both input lines, then the tri-state transceivers 54A are in the open position. Since the tri-state transceivers 54A0... 54A7 are all switched in the same manner, i.e. either all eight lines are connected to the data bus 1 42A, or they are not, the output of the flipflop 64A and 64B are,used to control all eight transceivers to interconnect one of the data buses. The logic unit 52 can also comprise other flipflops and control gates to control other tri-state transceivers which are grouped in groups of eight to gang the switching of the selection of connection to one or more of the other data buses 42.

Because the interconnection of one or more of the data buses 42 to one or more of the plurality of modules (34, 36, 38 and 40), is under the control of the control bus 32, the data paths for the connection of the data buses 42 (A-I) can be dynamically reco nfigured.

Referring to Figure 5a, there is shown one possible configuration with the dynamically reconfigurable data buses 42. Since each data bus 42 is 8 bits wide, the plurality of modules (34, 36, 38 and 40) can be connected to receive data from two data buses (e.g. 42A and 42B), simultaneously. This is data processing in the parallel node in which 16 bits of data are simultaneously processed along the data bus.

Thus, the data buses 42 can be ganged together to increase the bandwidth of data transmission.

Referring to Figure 5b, there is another possible configuration for the data buses 42. In this node of operation, module 34 can transmit data on data bus 42A to module 36. Module 36 can communicate data with module 38 along the data bus 42B. Finally, module 38 can communicate with module 40 along the data bus 42C. In this mode, which is termed pipeline processing, data can flow from one module to another sequentially or simultaneously since data is flowing on separate and unique data buses.

Referring to Figure 5c, there is shown yet another possible configuration for the data bus 42. In this mode the operation is known as macro interleaving. If, for example, the module 34 is able to process or transmit data faster than the modules 36 or 38 can receive them, module 34 can send every odd data byte to module 36 along data bus 42A and every even data byte along bus 42B to the module 38. In this manner, data can be stored or processed at the rate of the fastest module. This is unlike the prior art where a plurality of modules must be operated at the speed of the slowest module.

Thus, as can be seen by examples shown in Figures 4a-4c, with a dynamically reconfigurable data bus structure, a variety of data transmission paths, including but not limited to those shown in Figures 4(a-c), can be dynamically and electronically reconfigured.

i Referring to Figure 6, there is shown yet another embodiment of a video image processor 110 of the present invention. The video image processor 110, similar to the video image processor 10 comprises a master controller 130 and a plurality of digital modules 134, 136 (not shown), 138 (A-B) and 140. These modules, similar to the modules 34, 36, 38 and 40, perform the respective tasks of image processing and image storing. The master controller 130 communicates with each one of the modules via a control bus 132. Each one of the modules 134-140 is also connected to one another by a plurality of data buses 42A-42I. Similar to the video image processor 10, there are nine data buses, each bus being 8 bits wide.

The only difference between the video image processor 110 and the video image processor 10 is that along each of the data buses 42 is interposed a switch means 154 controlled by a logic unit 152 which is activated by an address decode circuit 150. This is shown in greater detail in Figures 7 and 9. As can be seen in Figure 6, the switch means 154A...154I are interposed between the image memory module 138A and image memory module 138B. That is, the switch means 154A...154I, divide the data buses 42A... 42I into two sections: the first section comprising of the video processor module 134 and the image memory module 138A; IC the second part comprising the morphological processor 140 and the,second image memory module 138B. The switch means 154 provide the capability of either connecting one part of the data bus 42A to the other part or leaving the data bus open, i.e. the data bus severed.

Referring to Figures 8a-8c, there is shown various configurations of the possible data bus structure that results from using the switch means 154A1541.

Figure 8a shows nine data buses 42A-42I, wherein the switch means 154A, 154B and 154C connect the data buses 42A, 42B and 42C into one continuous data bus. However, the switch means 154D... 1541 are left in the open position thereby severing the data buses 42D... 421 into two portions. In this mode of operation, parallel processing can occur simultaneously using the data buses 42D... 421 by the modules 134, and 138 and by the modules 138 and 140. In addition, serial or pipeline processing can occur along the data buses 42A... 42C. As before, with the switch means 154A... 1541, dynamically selectable, total parallel processing as shown in Figure Zb or total pipeline processing as shown in Figure Ic are also possible. In addition, of course other configurations including but not limited to the macro interleave configuration of Figure 5c, are also possible.

Referring to Figure 7, there is shown a schematic block diagram of the electronic circuits used to control the data 42A... 421 of the video image processor 110. As previously stated, a switch means 154 is interposed between two halves of each data bus 42. shown in Figure 7, is the switch means 154A interposed in the data bus 42A and the switch means 1541 interposed in the data bus 421. Each one of the switch means 154 is controlled by the logic unit 152 which is activated by the address decode circuit 150. Similar to the address decode circuit 50, the address decode 150 is connected to the eight address lines of the control bus 132. If the correct address is detected, the control signal 156 is sent to the logic unit 152. The control signal 156 activates the logic unit 152 which in turn activates one or more of the switch means 154.

Referring to Figure 9, there is shown a detailed simplistic schematic circuit diagram of the logic unit 152 and the switch means 154A. As can be seen, the logic 152 is identical to the logic unit 52. The switch means 154 (a tri-state transceiver). interconnects one half of one of the bus lines to the other half of the bus line 42. In all other respects, the operation of the switch means 154, logic unit 152, and the address decode circuit 150 is identical to that shown and described for the address decode circuit 50, logic unit 52, and switch means 54.

As previously stated, the reconfigurable data buses 42, interconnect the plurality of modules (34, 36, 38 and 40) to one another. The modules comprise a plurality of processor modules and a plurality of memory modules. With the exception of the communication means, logic unit and address decode circuit, the rest of the electronic circuits of each module for processing or storing data can be of conventional design. One of the processor modules 34 is the video processor module.

The video processor module 34 is shown in block diagram form in Figure 10. The video processor 34 receives three analog video signals from the color camera 12. The three analog video signals comprising signals representative of the red, green, and blue images, are processed by a DC restoration analog circuit 60. Each of the resultant signals is then digitized by a digitizer 62. Each of the three digitized video signals is the analog video signal from the color camera 12, segmented to form a plurality of image pixels and with each image pixel digitized to form a greyscale value of 8 bits. The digitized video signals are supplied to a 6x6 cross-point matrix switch 64 which outputs the three digitized video signals onto three of the six data buses (42A-42F).

From the data buses 42A-42F, the digitized video signals can be stored in one or more of the image memory modules 3SA-38C. The selection of a particular image memory module 3SA-38C to store the digitized video signals is accomplished by the address decode circuit 50 connected to the logic unit 52 which activates the particular tri-state transceivers 54, all as previously described. The data selection of which data bus 42 the digitized video images would be sent to is based upon registers in the logic unit 52 which are set by the control bus 32.

Each of the memory modules 38 contains three megabytes of memory. The three megabytes of memory is further divided into three memory planes: an upper plane, a middle plane, and a lower plane. Each plane of memory comprises 512 x 2048 bytes of memory. Thus, there is approximately one megabyte of memory per memory plane.

Since each digitized video image is stored in a memory space of 256 x 256 bytesi each memory plane has room for 16 video images. In total, a memory module has room for the storage of 48 video images. The address of the selection of the particular video image from the particular memory plane within each memory is -is- module is supplied along the control bus 32. As the data is supplied to or received from each memory module 38, via the data buses 42, it is supplied to or from the locations specified by the address set on the control bus 32. The three digitized video images from the video processor 34 are stored, in general, in the same address location within each one of the memory planes of each memory module.

Thus, the digital video signal representative of the red video image may be stored in the starting address location of x=256, Y=0 of the upper memory plane; the digitized signal representative of the blue video image may be stored in x=256, y=0 of the middle memory plane; and the digital video signal representative of the green video image may be stored in x=256, y=0 of the lower memory plane.

once the digital video signals representative of the digitized video images are stored in the memory planes of one or more memory modules 38, the digitized video images are operated upon by the morphological processor 40.

The morphological processor 40 receives data from the data buses 42A-42D and outputs data to the data buses 42E-42G. Further, the morphological processor 40 can receive input or output data to and from the data buses 42H and 421. Referring to Figure 12, there is shown a schematic block diagram of the morphological processor 40. 'the morphological processor 40 receives data from data buses 42A and 42B which are supplied to a multiplexer/logarithmic unit 70. The output of the multiplexer/logarithmic unit 70 (16 bits) is either data from the data buses 42A and 42B or is the logarithm thereof. The output of the multiplexer/logarithmic unit 70 is supplied as the input to the ALU 72, on the input port designated as b. The ALU 72 has two input ports: a and b.

The morphological processor 40 also comprises a multiplier accumulator 74. The multiplier accumulator 74 receives data from the data buses 42C and 42D and from the data buses 42H and 421 respectively, and performs the operation of multiply and accumulate thereon. The multiplier accumulator 74 can perform the functions of 1) multiplying the data from (data bus 42C or data bus 42D) by the data from (data bus 42H or data bus 421); or 2) multiplying the data from (data bus 42C or data bus 42D) by a constant as supplied from the master controller. The result of that calculation is outputted onto the data buses 421, 42H and 42G. The result of the multiply accumulate unit 74 is that it calculates a Green's function kernel in realtime. The Green's function kernel is a summation of all the pixel values from the start of the horizontal sync to the is then current pixel. This would be used subsequently in calculation of other properties of the image.

A portion of the result of the multiplier accumulator 72 (16 bits) is also inputted into the ALU 72, on the input port designated as a. The multiplier accumulator 74 can perform calculations of multiply and accumulate that are 32 bits in precision. The result of the multiplier accumulator 74 can be switched by the multiplier accumulator 74 to be the most significant 16 bits or the least significant 16 bits, and is supplied to the a input of the ALU 72.

The output of the ALU 72 is supplied to a barrel shifter 76 which is then supplied to a look-up table 78 and is placed back on the data buses 42E and 42F. The output of the ALU 72 is also supplied to a prime generator 80 which can also be placed back onto the data buses 42E and 42F. The function of the prime generator 80 is to determine the boundary pixels, as described in U.S. Patent No. 4,538,299.

The ALU 72 can also perform the function of subtracting data on the input port a from data on the input port b. The result of the subtraction is an overflow or underflow condition, which determines a>b or a<b. Thus, the pixel-by-pixel maximum and minimum for two images can be calculated.

Finally, the ALU 72 can perform histogram calculations. There are two types of histogram calculation. In the first type, the value of A pixel (a pixel value is 8 bits or is between 0-255), selects the address of the memory 73. The memory location at the selected address is incremented by 1. In the second type, two pixel values are provided: a first pixel value of the current pixel location and a second pixel value at the pixel location of a previous line to the immediate left or to the immediate right (i.e. diagonal neighbor). The pairs of pixel values are used to address a 64K memory (256 x 256) and the memory location of the selected pixel is incremented. Thus, this histogram is texture related.

In summary, the morphological processor 40 can perform the functions of addition, multiplication, multiplication with a constant, summation of a line, finding the pixel-by-pixel minimum and maximum for two images, prime generation, and also histogram calculation. The results of the morphological processor 40 are sent along the data buses 42 and stored in the image hemory modules 38. The ALU 72 can be a standard 181 type, e.g. Texas Instruments part ALS181. The multiplier accumulator 74 can be of conventional design, such as Weitech WTL2245.

is Referring to Figure 13, there is shown the graphic controller processor 36, in schematic block diagram form. The function of the graphic controller 36 is to receive processed digitized video images from the memory modules 38, graphic data, and alphanumeric data and combine them for output. The data from the control bus 32 is supplied to an Advanced CRT controller 84. The CRT controller is-a part made by Hitachi, part number HD 63484. The output of the advance CRT controller 84 controls a frame buffer 80. Stored within the frame buffer 80 are the graphics and alphanumeric data. The video images from the data buses 42A-42F are also supplied to the graphics controller processor 36. One of the data buses 42 is selected and that combined with the output of the frame buffer 80 is supplied to a look-up table 82. The output of look-up table 82 is then supplied as the output to one of the data buses 42G, 42H or 421. The function of the graphics control processor 36 is to overlay video alpha and graphics information and then through a D to A to converter 86 is supplied to the monitor 26. In addition, the digital overlayed image can also be stored in one of the image memory modules 38.

The image which is received by the graphics control processor 36 from one of the image memory 1 C modules 38 is through one of the data buses 42A-42F. The control,signals along the control bus 32 specifies to the image memory module 36 the starting address, the x and y offset with regard to vertical sync as to when the data from the image memory within that memory module 38 is to be outputted onto the data buses 42A42F. Thus, split screen images can be displayed on the display monitor 26. The master controller 30, as previously stated, communicates with the host

computer 22 via a Q-bus. The master controller 30 receives address and data information from the host computer 22 and produces a 64 bit microcode. The 64 bit microcode can be from the writable control store location of the host computer 22 and is stored in WCS 90 or it can be from the proxy prom 92. The control program within the proxy prom 92 is used upon power up as WCS 90 contains volatile RAM. The 64 bit microcode is processed by the 29116 ALU 94 of the master controller 30. The master controller 30 is of the Harvard architecture in that separate memory exists for instruction as well as for data. Thus, the processor 94 can get instruction and data simultaneously. In addition, the master controller 30 comprises a background sequencer 96 and a foreground sequencer 98 to sequence series of program instruction stored in the writable control storage 90 or the proxy t C prom 92. The Q-bus memory map from which the master controller 30 receives its writable control store and its program memory is shown as below:

ADDRESS (HEXADECIMAL) use BS7 (Block 7 conventional Digital Egipment Corp. nonemclature) Scratch Pad 3FFFFF 3FEOOO 3FDFFF) 3FAO.00) 387FFF) 380000) 37FFFF) 280000) Writable Control Store Image Memory Window 1FFFFF) Host Computer 0 Program Memory In addition, the control signals ADAV, CMD and WRT have the following uses.

CONTROL SIGNALS ADAV CMD 0 x 1 1 1 1 1 0 WRT X 0 1 0 Use Quiescent Bus Read Register Write Register Read Image Memory 1 0 1 Write Image Memory The master controller 30 operates synchronously with each one of the modules 34, 36, 38 and 40 and asynchronously with the host computer 22. The clock signal is generated by the master controller 30 and i sent to every one of the modules 34, 36, 38 and 40. In addition, the master controller 30 starts the operation of the entire sequence of video image processing and video image storing upon the start of vertical sync.

Thus, one of the signals to each of the logic units 52 is a vertical sync signal. In addition, horizontal sync signals may be supplied to each one of the logic units.

The logic units may also contain logic memory elements that switch their respective tri-state transceivers at prescribed times with respect to the horizontal sync and the vertical sync signals.

Referring to Figure 15, there is shown a schematic diagram of another embodiment of a logic unit 252. The logic unit 252 is connected to a first address decode circuit 250 and a second address decode circuit 251.

The logic unit 252 comprises a first AND gate 254, a second AND gate 256, a counter 258 and a vertical sync register 260.

Prior to the operation of the logic unit 252, first address decode circuit 250 is activated loading the data from the date lines of the control bus 32 into the counter 258.

Thereafter, when the second address decode circuit 251 is activated, and vertical sync signal is received, the counter 258 counts down from each clock pulse received. When the counter 258 reaches zero, the tristate registers 64a and 64b are activated.

It should be emphasized that the master controller 30, each one of the processing modules 34, 361 38 and 40 and each one of the image memory modules 38 can be of conventional design. The master controller 30 controls the operation of each one of the modules along a separate control bus 32. Further, each of the modules communicates with one another by a plurality of data buses 42. The interconnection of each one of the modules (34-40) with one or more of the data buses 42 is accomplished by means within the module (34-40) which is controlled by the control signals along the control bus 32. The interconnection of the data buses 42 to the electronic function within each of the modules is as previously described. However, the electronic function within each of the modules, such as memory storage or processing can be of conventional architecture and design.

There are many advantages to the video image processor 10 and 110 of the present invention. First and foremost is that because the interconnection is dynamically reconfigurable, the architecture can be dynamically changed. In particular, in the same program execution, data can be flowing in pipeline fashion or parallel fashion or a combination of both.

1 % Further, since address is not supplied on the data buses 42 but is instead supplied on a separate control bus, greater transfer rate can be achieved. Finally, since a plurality of processing modules and a plurality of memory modules can be attached to the plurality of buses and with the bus interconnection dynamically reconfigurable, simultaneous processing functions can occur.

is CEATIVS 1. A digital processing system comprising:

a lurality of digital electronic modules, each module having a communication means, said modules for processing and storing data; a plurality of data buses interconnecting said plurality of modules, each data bus having a plurality of communication paths; master controller means; control bus having a plurality of communication paths interconnecting said master controller means to each one of said modules; said master controller means for controlling the operation of said plurality of modules by passing control signals along said control bus; and means in each module responsive to said control signals from said control bus for connecting said communication means to one or more of said data buses.

2. The system of claim 1 wherein said plurality of modules further comprises a plurality of processor modules.

1 1 3. The system of claim 2 wherein said plurality of modules further comprises a plurality of memory modules.

4. The system of claim 1 further comprising: a plurality of switch means, each interposed in one of the communication paths of said plurality of data buses for interconnecting said communication path; and means responsive to said control signals to activate one or more of said switch means to connect said communication path.

A video image processor for processing an analog video image comprising: a plurality of digital electronic modules, each module having a communication means; said modules further comprising a plurality of processor modules for receiving said analog video image, for digitizing said analog video image to form a digitized video image, for processing said digitized video image to form a processed digitized image and for outputting said digitized video image; a plurality of memory modules for storing said 1 digitized video image and said processed digitized image; a plurality of data buses interconnecting said plurality of modules, each data bus having a plurality of communication paths; a master controller means; a control bus having a plurality of communication paths interconnecting said master controller means to each one of said modules;. said master controller means for controlling the operation of said plurality of modules by transmitting control signals along said control bus; and means in each module responsive to said control signals from said control bus for connecting said communication means to one or more of said data buses.

The process of claim 5 further comprising: a plurality of switch means, each interposed in one of the communication paths of said plurality of data buses; and means responsive to said control signals to activate one or more of said switch means.

Z k 1 7. The processor of claim 5 wherein said plurality of processor modules further comprisingz a first processor module having means for receiving an analog video image and means for digitizing said analog video image to form a digitized video image; a second processor module having means for processing said digitized video image to form a processed digitized image; and a third processor module having means for outputting said digitized video image.

8. The processor of claim 7 wherein said first processor module further comprising: means for receiving three analog video images simultaneously, said three analog video images representing the color components of a single video image; means for digitizing simultaneously said three analog video images to form three digitized video images.

9. The processor of claim 5 wherein one of said control signals is a clock signal.

10. The processor of claim 9 wherein each one of said modules operates synchronously with said clock signal.

11. The processor of claim 10 wherein said analog video image is characterized by a vertical sync signal.

12. The processor of claim 11 wherein said vertical sync signal is transmitted to said modules along one of the communication paths of said control bus.

13. The processor of claim 7 wherein said third processor module further comprising: digital to analog conversion means for converting said digitized video image to an analog video image.

14. The processor of claim 13 wherein said third processor module furthercomprising: means for displaying graphic data, alphanumeric data and said digitized video image simultaneously.

15. The process of claim 6 wherein said responsive means further comprises: memory means for storing timing data.

2 means for activating said memory means; and means for receiving the output of said memory means to activate one or more of said switch means.

16. A digital processing system having dynamically reconfigurable data paths comprising: a plurality of digital modules, each module having a communication means, said modules for storing and processing data; a plurality of data buses interconnecting said plurality of modules, each data bus having a plurality of communication paths; a master controller means for generating control signals to dynamically reconfigure the connection between each module and one or more of said data buses; means in each module responsive said control signals to connect said communication means to one or more of said data buses.

Published 1988 at The Patent Office. State House. 6671 High Holborn. London WC1R 4TP. Ftrther copies may be obtained from The Patent Office, w. tnRA:%RD. Printed b-v Multiplex tecliniques ltd, St Mary Cray. Kent. Con 1187