GB2207573A - Data transmission circuits - Google Patents

Abstract

An improved data transmission circuit for CMOS dynamic random access memory devices having a data input buffer (10) for converting TTL input data signals to CMOS logic level true and complement data signals, a pair of transmission gates (100, 200) for transferring the true and complement data signals in a write cycle, a pair of inverting means connected between respective ones of the transmission gates and true and complement I/O bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalising means (500) for precharging and equalising true and complement I/O bus lines in a precharge cycle. It is characterised in that each of the inverting means can operate under the control of a block selecting clock signal regardless of precharging voltages of true and complement I/O bus lines. <IMAGE>

Description

DATA TRANSMISSION CIRCUITS The present invention relates to data transmission circuits for use in semiconductor memory devices, and more particularly relates to data transmission circuits for transmitting data signals from a data input buffer to a pair of input/output (hereinafter referred to as "I/O") bus lines in a CMOS dynamic random access memory (hereinafter referred to as "DRAM") device.

Conventionally, a CMOS DRAM device includes a data input buffer which is activated in a write cycle and converts TTL (Transistor - Transistor Logic) level input data signals to CMOS logic level data signals. The data input buffer supplies true and complement output data signals on a pair of data bus lines, respectively, and signals on the pair of data bus lines are respectively sent to a pair of I/O bus lines. Thereafter, the true and complement signals on the I/O bus lines are respectively transmitted on a pair of corresponding bit lines via a pair of transfer gates (respectively coupled to the I/O bus lines and turned on by a column address signal) and via a sense amplifier. One of the data signals on the bit line pair is written into one memory cell selected by a row address signal provided by a row address decoder.

However, since in high density DRAM devices, for example, in such devices as 1 megabit DRAM, both the data bus line pair and the I/O bus line pair extend a long distance from the data input buffer to the bit line pair in view of the circuit arrangement, the data input buffer must bear the burden of driving one of the data bus line pairs having parasitic capacitance of approximately 1.5 Pf per line and the corresponding 1/0 bus line having about 3 Pf to 4 Pf per line as a load.

To assist in understanding the disadvantages which plague prior art devices, a data transmission circuit is shown in a block diagram form in Figure 1 of the accompanying drawings. Referring to Figure 1, a data signal read into the circuit through a data input buffer 10 is outputted as a pair of true and complement MOS logic level data signals DIN and DIN, and the signals DIN and DIN are respectively coupled to a pair of data bus lines 11 and 12. The signals DIN and DIN are respectively sent on the I/O bus lines 13 and 14 through a pair of transmission transistors 1 and 2 which are turned on by a transfer gate control clock signal on a gate line 16, generated from the combination of a write enable signal and column address signals.The data signals transmitted on the I/O bus lines 13 and 14 are respectively sent on a pair of bit lines 61 and 60 through a pair of transmission transistors 44 and 43 (constituting a transfer gate 40 turned on by the column address signal on a gate line 41) and through a sense amplifier 50. Thereafter, one of the true and complement data signals on the bit lines 61 and 60 is written into a memory cell 63 or 62 by a row address signal on a row address line 65 or 64.

An I/O sense amplifier 30 enabled only in a read cycle amplifies one of the true and complement data signals on the I/O bus lines 13 and 14 read out from the memory cells. An equaliser circuit 20 begins an operation for equalising the I/O bus lines 13 and 14 at a precharge time of read and write cycles.

Therefore, the data transmission circuit shown in Figure 1 must drive the large parasitic capacitance of each selected data bus line and its corresponding I/O bus line as a load, in order to write data information into a memory cell 62 or 63.

Therefore, the data input buffer 10 must include a relatively large size current drive transistor at the output stage thereof in order to charge the relatively large parasitic capacitance and as a result, a relatively low rate transfer speed and a relatively large power consumption are effected.

One way of decreasing the parasitic capacitance of the I/O bus lines, which provides the largest capacitance, is to divide on chip all memory cells into several blocks each including a certain number of memory cells, according to the integration and density of memory cells. Such an increase of the number of divided blocks causes an increase of I/O bus lines pairs and that of their corresponding transmission transistors.

In a write cycle for reading the data information into the memory cell array, however, many are the I/O bus line pairs due to the number of such divided blocks, there is no problem because only one of the I/O bus line pairs is selected and then one of the data signals on the selected I/O bus line pair is stored in an addressed memory cell. However, the larger the integration density of memory cells, the more serious is the problem of testing the memory cells when the memory device is manufactured. That is, the test time for writing data information into all memory cells and for reading the stored information out from each memory cell increases greatly according to the increased density of memory cells. Therefore, to achieve a high speed test of memory cells, a plurality of data bits must be written into addressed memory cells and read out from those memory cells.In this case, since the I/O bus line pairs must be coupled to the data input buffer in the same numbers as the number of data bits written into memory cells, the load burden of the data input buffer will be increased by the number of such data bits. Finally, the size of the transistors for driving the I/O bus pairs at the output stage of the data input buffer will be increased to accommodate the increased parasitic capacitance and as a result the chip size will be increased.

A data transmission circuit for solving the above described problems is shown in Figure 5 of the accompanying drawings, and is disclosed in U.S. Patent application serial No. 067,016 entitled "Data Transmission Circuit", which is now allowed to SEO SEUNG MO and assigned to the present applicant. Referring to Figure 5 (in which like reference numerals denote like or corresponding parts to those of Figure 1), inverting buffer circuits 70 and 80 for isolating data bus lines 11 and 12 and I/O bus lines 13 and 14 are respectively coupled between transmission gates 1 and 2 and data bus lines 13 and 14.In a precharge cycle, all of transmission gates 1 and 2 and inverting buffer circuits 70 and 80 will remain at off-states in response to a write data clock ~WDT, and both of I/O bus lines 13 and 14 will be precharged to a potential VDD through the operation of a precharged and equalising circuit 500. In a write cycle, after data DIN and DIN from the data input buffer 10 respectively supplied to data bus lines 11 and 12, in response to the clock ~WDT, transmission gates 1 and 2 and inverting buffer circuits 70 and 80 are all operated to transmit inverted data DIN and DIN on I/O bus lines 13 and 14 respectively. Therefore, a decreased load burden of the data input buffer will be accomplished because of the treatment of only data bus lines 11 and 12 as loads.This data transmission circuit has no problem where the precharge scheme is such that I/O bus lines 13 and 14 are precharged to full power supply potential VDD.

However, where I/O bus lines 13 and 14 are precharged to half potential 1/2VDD, the transmission circuit has a drawback of operation. That is, in a precharge cycle, Pchannel MOS transistors 72 and 82 are both turned on due to a 1/2VDD precharge of I/O bus lines 13 and 14. Also, in response to the clock #WDT, both N-channel MOS transistors 71 and 81 are turned on. Therefore, assuming that the transistors 71 and 81 happen to become less conductive than the transistors 72 and 82, the potential of lines 31 and 32 can be higher than each threshold voltage of N-channel MOS transistors 75 and 85 and consequently, due to the conduction of N-channel MOS transistors 75 and 85, the precharge of I/O bus lines 13 and 14 cannot be accomplished. Also, the conduction of transistors 71, 72 and 81 and 82 results in power consumption.

Preferred embodiments of the present invention aim to provide improved data transmission circuits, which can effect a decreased load burden on a data input buffer in a write cycle, and be sure to operate at any precharge potential of I/O bus lines.

More generally, according to one aspect of the present invention, there is provided an integrated CMOS data transmission circuit including true and complement data bus lines (11, 12) for receiving input data signals from respective ones of true and complement output terminals of a data input buffer, first and second transmission gating means for respectively transferring the data signal on said true and complement data buses to first and second lines in response to a first clock signal during a write cycle, first and second input/output bus line pull-up and pull-down means connected respectively between said first line and a true input/output bus line, and between said second line and a complement input/output bus line for pulling one of said input/output bus lines up and pulling the other of said input/output bus lines down in response to the data signals on said first and second lines in said write cycle, and equalising means connected between the true and complement input/output bus lines for precharging and equalising both the said input/output bus lines to a power supply voltage (VDD) or fraction thereof in response to second and third clock signals during a precharge cycle, wherein said first pull-up and pull-down means comprises a first inverting means connected to said first line for inverting data signals on said first line in response to a fourth clock signal to provide said inverted data signals to a third line, a second inverting means for inverting data signals on said third line, and a first clocked inverting means connected between said second inverting means and said true input/output bus line for inverting data signals from said second inverting means in response to data signals on a fourth line to provide said inverted data signals to said true input/output bus line, and said second pull-up and pulldown means comprises a third inverting means connected to said second line for inverting data signals on said second line in response to said fourth clock signal to provide said inverted data signals to said fourth line, a fourth inverting means for inverting said data signals on said fourth line, and a second clocked inverting means connected between said fourth inverting means and said complement input/output bus line for inverting data signals from said fourth inverting means in response to data signals on said third line to provide said inverted data signals to said complement input/output bus line.

Preferably, each of said first and second pull-up and pull-down means further comprises a pull-down transistor having a gate coupled to receive said first clock signal and a drain-source path connected between one of said first and second lines and a reference potential.

Each of said first and third inverting means may be a two-input CMOS NAND gate inputting data signals on one of said first and second lines and said fourth clock signal.

Said fourth clock signal is preferably an address decoding signal for selecting one or more memory cell array block and said first clock signal is preferably a write enable signal.

Preferably, each of said first and second transmission gating means comprises a P-channel MOS transistor having a gate coupled to receive said first clock signal and whose source-drain path is connected between one of said data bus lines and a corresponding one of said first and second lines, and an N-channel MOS transistor having a gate coupled to receive an inversion clock signal of said first clock signal and whose drainsource path is connected in parallel with said sourcedrain path of said P-channel MOS transistor.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2, 3 and 4 of the accompanying diagrammatic drawings, in which: Figure 2 is a block diagram of a preferred embodiment of the invention; Figure 3 is a circuit diagram showing a portion of the block diagram of Figure 2; and Figure 4 is a timing diagram illustrative of the operation of the circuit of Figure 3.

In all of Figures 1 to 5, like reference numerals denote like or corresponding parts.

The embodiment of Figure 2 comprises a first transmission gate 100 which is coupled to the data bus line 11 connected to a complement output line of the data input buffer 10, and is turned on or off under the control of the write data transmission clock ~WDT and its complement clock signal ~WDT for transmitting data information signal on the data bus line 11 to an output line 31. A second transmission gate 200 is coupled to the other data bus line 12 carrying the true signal from the data input buffer 10 (the complement of the data signal on the data bus line 11) and is turned on or off under the control of said clock signals ~WDT and ~WDT for transmitting a data information signal on the line 12 to an output line 32.

A first I/O bus line pull-up for pull-down circuit 300 is coupled between the line 31 and an I/O bus line 13 and, in a write cycle, effects pull-up or pulldown of the I/O bus line 13 in response to the data signal on the line 31, under the control of said clock signal ~WDT, a block selecting clock signal 0DOTS decoded by the combination of a selected one or more address signals for selecting a write-in block of the data information signal, and a feedback signal on a line 92.

In a precharge cycle, the circuit 300 isolates between lines 31 and 13 under the control of said clock signals ~WDT and ~DTB. A second I/O bus line pull-up or pulldown circuit 400 is coupled between the line 32 and the other I/O bus line 14 and, in the write cycle effects pull-up or pull-down of the I/O bus line 14 under the control of said clock signals ~WDT and ~DTB together with a feedback signal on a line 91 and, in a precharge cycle, isolates between lines 32 and 14 under the control of said clock signals ~WDT and ~DTB. An I/O bus line equalising circuit 500 is coupled between the lines 13 and 14 for precharging and equalising said lines 13 and 14 in response to an equalising clock signal ~IOEQ and an I/O bus line precharging clock signal ~IOP in the precharge cycle.

The block selecting clock signal ~DTB and the I/O bus line precharging clock signal ~IOP will now be described in detail.

For example, in 1 megabit DRAM, the array of its memory cells can be divided into four main blocks, each of which can be again divided into two sub-blocks. Then, the data transmission circuit is coupled to each subblock. In such a case, two main blocks of four main blocks will be selected by one address signal and one sub-block of four sub-blocks in two main blocks selected by the address signal can be selected by two other address signals. Therefore, the clock signal e)DTB will be a sub-block selecting signal decoded by those address signals in a write cycle and the generation of such a clock signal ~DTB is well known in the art.On the other hand, the I/O bus line precharging clock signal ~IOP can be produced by the logical sum of the clock signal ~DTB and the clock signal ~WDT. The clock ~WDT can be a conventional write enable signal from an external pin or pad.

In a precharge cycle, prior to the output of data from the data input buffer 10, the first and second I/O bus line pull-up or pull-down circuits 300 and 400 make lines 31 and 32 pull-down to low state in response to the clock signal ~WDT and at the same time the I/O bus line equalising circuit 500 causes I/O bus lines 13 and 14 to precharge (or pull-up) to a high state (VDD or 1/2VDD) in response to clock signals ~IOEQ and ~IOP.

Now, if the data signals from the data input buffer 10 are supplied on the data bus lines 11 and 12, both first and second transmission gates 100 and 200 are activated by clock signals ~WDT and BWDT and then deliver data signals on the data bus lines to lines 31 and 32, respectively. Data signals on the lines 31 and 32 are inverted by the first and second I/O bus line pull-up or pull-down circuits 300 and 400 under the control of clock signals ~WDT, ~DTB and are delivered to lines 41 and 42, respectively (see Figure 3). Therefore, the first I/O bus line pull-up or pull-down circuit 300, if the inverted signal of that on the line 91 and the signal on the line 92 have the same logical value, delivers to the I/O bus line 13 the same logical value as that on the line 91.The second I/O bus line pull-up or pull-down circuit 400, if the inverted signal of that on the line 92 and the signal on the line 91 have the same logical value, delivers to the I/O bus line 14 the same logical value as that on the line 92. As a result, each of the first and second I/O bus line pull-up and pull-down circuits 300 and 400 works to completely isolate data bus lines 11 and 12 and I/O bus lines 13 and 14 with the control clock signals ~WDT and ~DTB. Subsequent to writing the data signal on the I/O bus line 13 or 14 into the memory array through the I/O gate 40, both I/O bus lines 13 and 14 are precharged to a logic high state under the precharge operation of the I/O bus line equalising circuit 500 receiving clock signals ~IOEQ and ~IOP.

Referring to Figure 3, data bus lines 11 and 12 are connected to the output line of the data input buffer 10 and I/O bus lines 13 and 14 are connected to the I/O gate 40 and the I/O sense amplifier 30.

Transistors M2, M3, M6, M7, M9, Mull, M12, M14, M16, M18, M20 and M22 are all N-channel MOS transistors and transistors M1, M3, M5, M8, M10, M13, M15, M19, M21 and M23 through M27 are all P-channel MOS transistors.

VDD depicts a power supply source voltage and the remaining reference numerals are used to designate like elements or parts to those in Figure 2.

Referring to Figure 4, Figure 4(A) and Figure 4(B) are respectively waveform diagrams of data signals DIN and DIN on data bus lines 11 and 12 provided by the data input buffer 10. Figure 4(C) and Figure 4(D) represent timing diagrams of the write data transmission clock signal ~WDT and the I/O bus line equalising clock signal ~IOEQ respectively. Figure 4(E) and Figure 4(F) represent output waveforms of the first and second transmission gate 100 and 200 respectively. Figure 4(G) represents a timing diagram of the block selecting clock signal ~DTB. Figure 4(H) and Figure 4(I) represent waveforms on lines 41 and 42 respectively. Figure 4(J) and Figure 4(K) represent waveforms on lines 51 and 52 respectively.Figure 4(L) represents a timing diagram of the I/O bus line precharging clock signal 8ION. Finally, Figure 4(M) and Figure 4(N) represent output waveforms of I/O bus lines 13 and 14 respectively.

Operation of the circuit of Figure 3 will now be described in detail in connection with the waveform diagrams of Figure 4.

Before data signals DIN and DIN on data bus lines 11 and 12 are supplied from the data input buffer 10 (prior to the time tl of Figure 4), the write data transmission clock ~WDT is maintained at a logic low state and the I/O bus line equalising clock signal ~IOEQ and the I/O bus line precharging clock signal ~IOP are remained at a logic high state and a logic low state respectively. Therefore, pull-down transistors M7 and M12 respectively constituting first and second I/O bus line pull-up and pull-down circuits 300 and 400 are turned on and both lines 31 and 32 become low.Also, pull-up transistors M26 and M27 constituting the I/O bus line equalising circuit 500 are turned on by the clock signal 8WOP, thereby each of I/O bus lines 13 and 14 is precharged to a logic high state (VDD) or a half VDD level.

Assuming that the true data signal DIN and the complement data signal DIN were respectively applied on data bus lines 11 and 12 as shown in Figure 4(A) and Figure 4(B) following the time tl and the clock signal ~WDT became high at the time t2 as illustrated in Figure 4(C), both the first transmission gate 100 composed of transistors M1 and M2 and the second transmission gate 200 composed of transistors M3 and M4 would be turned on by the inverted clock signal ~WDT through an inverter 600 and by the inverted clock signal ~WDT of the clock signal ~WDT through an inverter 700, and then each of signals on lines 31 and 32 would become low and high as shown in Figure 4(E) and Figure 4(F) due to OFF states of both transistors M7 and M12 gates of which are coupled to the clock signal ~WDT. Transistors MS, M6, M8 and M9 constitute one NAND gate 310 and transistors M10, M11, M13 and M14 another NAND gate 320. The source-drain path of the transistor M5 and the drain-source paths of the transistors M6 and M9 are connected in series between the power supply source voltage VDD and the ground potential and the source-drain path of the transistor M8 is connected between the power supply source voltage VDD and the common connection point 302 of each drain of transistors M5 and M6.Transistors M10, Mull, M13 and M14 constituting the NAND gate 320 are connected in the same manner as the NAND gate 310. Therefore, the line 41 coupled to the point 302 becomes high(VDD) with the low state on the line 31 which is applied to gates of transistors M5 and M6 and the high state of clock signal ~DTB which is supplied to gates of transistors M8 and M9, while the line 42 coupled to the point 304 becomes low with the high state on the line 32 which is applied to gates of transistors M10 and M11 and the high state of the clock signal ~DTB which is supplied to gates of transistors M13 and M14. The high state on the line 41 is coupled to gates of transistors M15 and M16 constituting an inverter and the output line 51 of the inverter becomes low. Therefore, the transistor M20 whose gate is coupled to the line 51 is turned off and the transistor M19 constituting a clocked inverter together with the transistor M20 whose gate is coupled to the line 92 connected to the line 42 is turned on. Then, the I/O bus line 13 becomes full VDD through the sourcedrain path of the transistor M19.

On the other hand, the low state on the line 42 is coupled to gates of transistors M17 and M18 constituting the other inverter and the output line 52 thereof becomes high. Therefore, the transistor M22 whose gate is coupled to the line 52 is turned on and the transistor M21 constituting the other clocked inverter together with the transistor M22 whose gate is coupled to the line 91 connected to the line 41 is turned off.

Then, the I/O bus line 14 is discharged to the logical low state (the ground level state) through the drainsource path of the transistor M22.

As a result, in a write cycle, I/O bus lines 13 and 14 respectively are sure to remain at a full VDD level and a ground level, or at the reversed levels.

These true and complement data signals on I/O bus lines 13 and 14 are supplied to the memory array through the I/O gate 40 of Figure 2.

Thereafter, at time 13, the low state of the I/O bus line equalising clock signal ~IOEQ turns on transistors M23 through M25 and at the same time the low state of the clock signal ~IOP turns on transistors M26 and M27. Also, lines 31 and 32 are both low states due to the high state of the clock signal ~WDT and then both lines 41 and 42 become high states with the low states of lines 31 and 32 through NAND gates 310 and 320.

Therefore, transistors M19 through M22 are turned off and both I/O bus lines 13 and 14 are charged to a full VDD or a half VDD. As described above, in a write cycle, since data signals on lines 41 and 42 respectively control not only the transistor M22 through the line 91 and the transistor M19 through the line 92, but also the transistor M20 through the inverter constituted by transistors M15 and M16 and the transistor M22 through the other inverter constituted by transistors M17 and M18, I/O bus lines 13 and 14 can always maintain an inverting relationship each other.

Also, since each of the first and second transmission gates 100 and 200 is composed of a P-channel MOS transistor and an N-channel MOS transistor having good transfer characteristics of high and low states respectively, they have good data transmission characteristics regardless of any states of data bus lines 11 and 12.

As another advantage, a decreased size of the load transistor of the data input buffer may be achieved because the data input buffer treats only the parasitic capacitance of the data bus lines as a load with the circuit arrangement of the I/O bus line pull-up and pulldown circuit between the transmission gate and the I/O bus line. Moreover, the size of each transmission gate can be lower than a conventional transmission gate because of the current flow charging only the parasitic capacitance of the line between the respective transmission gate and the I/O bus line pull-up and pulldown circuit.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (5)

1. An integrated CMOS data transmission circuit including true and complement data bus lines (11, 12) for receiving input data signals from respective ones of true and complement output terminals of a data input buffer, first and second transmission gating means for respectively transferring the data signal on said true and complement data buses to first and second lines in response to a first clock signal during a write cycle, first and second input/output bus line pull-up and pulldown means connected respectively between said first line and a true input/output line, and between said second line and a complement input/output bus line for pulling one of said input/output bus lines up and pulling the other of said input/output bus lines down in response to the data signals on said first and second lines in said write cycle, and equalising means connected between the true and complement input/output bus lines for precharging and equalising both the said input/output bus lines to a power supply voltage (Vdd) or fraction thereof in response to second and third clock signals during a precharge cycle, wherein said first pull-up and pull-down means comprises a first inverting means connected to said first line for inverting data signals on said first line in response to a fourth clock signal to provide said inverted data signals to a third line, a second inverting means for inverting data signals on said third line, and a first clocked inverting means connected between said second inverting means and said true input/output bus line for inverting data signals from said second inverting means in response to data signals on a fourth line to provide said inverting data signals to said true input/output bus line, and said second pull-up and pulldown means comprises a third inverting means connected to said second line for inverting data signals on said second line in response to said fourth clock signal to provide said inverted data signals to said fourth line, a fourth inverting means for inverting said data signals on said fourth line, and a second clocked inverting means connected between said fourth inverting means and said complement input/output bus line for inverting data signals from said fourth inverting means in response to data signals on said third line to provide said inverted data signals to said complement input/output bus line.

2. An integrated CMOS data transmission circuit as claimed in Claim 1, wherein each of said first and second pull-up and pull-down means further comprises a pull-down transistor having a gate coupled to receive said first clock signal and a drain-source path connected between one of said first and second lines and a reference potential.

3. An integrated CMOS data transmission circuit as claimed in Claim 1 or 2, wherein each of said first and third inverting means is a two-input CMOS NAND gate inputting data signals on one of said first and second lines and said fourth clock signal.

4. An integrated CMOS data transmission circuit as claimed in Claim 1, 2 or 3, wherein said fourth clock signal is an address decoding signal for selecting one or more memory cell array block and said first clock signal is a write enable signal.

5. An integrated CMOS data transmission circuit as claimed in Claim 1, 2 3 or 4, wherein each of said first and second transmission gating means comprises a Pchannel MOS transistor having a gate coupled to receive said first clock signal and whose source-drain path is connected between one of said data bus lines and a corresponding one of said first and second lines, and an N-channel MOS transistor having a gate coupled to receive an inversion clock signal of said first clock signal and whose drain-source path is connected in parallel with said source-drain path of said P-channel MOS transistor.