GB2204730A - Bipolar transistors - Google Patents
Bipolar transistors Download PDFInfo
- Publication number
- GB2204730A GB2204730A GB08711300A GB8711300A GB2204730A GB 2204730 A GB2204730 A GB 2204730A GB 08711300 A GB08711300 A GB 08711300A GB 8711300 A GB8711300 A GB 8711300A GB 2204730 A GB2204730 A GB 2204730A
- Authority
- GB
- United Kingdom
- Prior art keywords
- polysilicon
- emitter
- window
- bipolar transistor
- emitter window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 239000002019 doping agent Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
In a bipolar transistor a polysilicon emitter contact is provided, the polysilicon essentially filing the emitter window and having a substantially planar upper surface. The planar top eases subsequent metal deposition and patterning and also results in a more nearly planar dopant drive front when the polysilicon is used as a dopant source in forming a shallow (</=0.15 mu m) emitter (12). <IMAGE>
Description
BIPOLAR TRANSISTORS
The present invention relates to bipolar transistors and in particular to the configuration of polysilicon emitter contacts in such transistors.
The continuing reduction in size of bipolar transistors in bipolar microcircuits has forced the abandonment of direct metal emitter contacts for small (ie. those having emitter widths of less than 3 devices. The reason for the abandonment of metal for emitter contacts is that metal gives rise to a high recombination velocity at the emitter surface: use of polysilicon results in a much lower recombination velocity, making it possible to produce good shallow emitters. A further reason for abandoning metal emitter contacts is that as the size of the emitter window is reduced a point is reached where the metal, which does not deposit conformally, no longer penetrates adequately the emitter window, so that it becomes impossible to ensure reliable and repeatable contact with the emitter.
Unlike metal, polycrystalline silicon (polysilicon) deposits conformally and is therefore better able to coat the sidewalls and floor of the emitter window (the site of the emitter contact) uniformly. Unfortunately although it is possible to achieve good contact between the polysilicon and the emitter, the conductivity of polysilicon is much less than that of metal even when the former is heavily doped (at the saturation limit of about 1E 21 cm3) Since the principal reason for reducing transistor size is to increase the speed of operation, and since resistance in series with the emitter effectively reduces the transistor's transconductance and hence reduces the slew rate it is important that the thickness of the polysilicon in the emitter contact is kept to a minimum (without being "transparent" to charge carriers such that the recombination velocity at the emitter surface rises). Again, since polysilicon deposits conformally it is relatively easy to deposit a satisfactory thin polysilicon layer to which contact can be made by subsequent metallisation.
Although such an arrangement works relatively well for emitter widths of about 3 tm, a number of problems become increasingly more severe as the emitter width is reduced further. In order to be able to define the required small feature sizes with the necessary tight tolerances it becomes essential to use anisotropic etching processes such as plasma etching, in place of the isotropic (usually wet) etching processes used formerly. A result of this is that the emitter sidewalls and other "vertical" features are now likely to be substantially normal to the wafer plane rather than inclined at 45 to 600 to the wafer plane as they were formerly. Additionally, the height of the emitter window increases with reduced emitter size, particularly with self-aligned processes.
Unfortunately the problem of providing satisfactory metallisation of the emitter window sidewalls becomes increasing more serious as they become taller and steeper. Furthermore even if a metal layer free from defects can be produced its uneven surface will mean that it cannot readily be patterned using optical lithography since at the feature size of interest the depth of field of the imaging optics is very shallow.
A further problem manifests itself when the polysilicon emitter contact is used as a dopant source for the production of a shallow diffused emitter. When a shallow diffused emitter is to be formed the polysilicon is heavily doped with a dopant species such as arsenic by implantation. Unfortunately as the width of the emitter window is reduced, the proportion of the emitter width which is under the polysilicon formed against the window watts increases, and the thickness of polysilicon normal to the wafer surface increases as the inclination and height of the sidewall increase, so that during the dopant drive a very non-uniform dopant front can be formed. The result of this non-uniformity is that the base thickness varies considerably across the width of the emitter, to the detriment of device performance.
The present invention seeks to mitigate at least in part these disadvantages of the prior art.
According to the present invention there is provided a method of fabricating a bipolar transistor, the method including the steps of: a) defining an emitter window in a dielectric layer to
expose the semiconductor of the active region; b) depositing polysilicon over the dielectric layer to
fill the emitter window; and c) planarising the surface of the polysilicon.
Embodiments of the invention will now be described with reference to the accompanying drawings in which:
Figure 1 is a schematic cross section through a semiconductor wafer, showing the emitter window prior to formation of an emitter contact;
Figure 2 shows a conventional polysilicon emitter contact;
Figure 3 shows the emitter window of Figure 1 filled wth polysilicon;
Figure 4 shows the emitter window of Figure 3 after the polysilicon has been planarised;
Figure 5 shows the emitter window of Figure 4 after the emitter contact has been cut and a shallow emitter formed.
In Figure 1 a base regionlis formed by doping in a body of semiconductor 2 on a wafer substrate. Polysilicon base contacts 3, 3' have been formed on the base and are covered with a dielectric layer 4 which may be oxide. An emitter window 5 has been opened in the dielectric layer 4 to expose the surface of the base region.The width W of the emitter window is preferably less than 1.5 rm and more preferably less than 1.0 pm. The height H of the emitter window is typically between 0.5 and 1.0 tim. As a result of the use of an anisotropic etching process, such as plasma etching or some other dry process, which is necessary for accurate definition of the emitter window and its position, the walls 6 of the emitter window will be substantially normal to the surface of the wafer although the upper end of the window will tend to have an outward taper due to erosion of the mask used during etching.
A conventional polysilicon emitter contact formed in the emitter window of Figure 1 comprises a conformal polysilicon layer 7 deposited to a thickness T of between about 0.2 and 0.4 pm. As can be seen from Figure 2, the polysilicon forms a thin layer of a "gull-wing" configuration covering the floor and sidewalls of the window. If such a configuration is used when a shallow emitter is formed by driving dopant from the polysilicon, the problem of non-uniformity in the doping front becomes severe when the polysilicon which is over the floor of the emitter window, and from which dopant will be driven into the base region, varies appreciably in height. In the example shown, the shaded region signifies the relevant polysilicon. As can be seen, at the periphery of the window the polysilicon has a height which is about 3 to 4 times that in the centre of the window. The effect of such a polysilicon profile on the doping profile of an emitter diffused from it can be seen by comparing the predicted profile P with the ideal profile I shown in the
Figure.
In the method according to the invention the polysilicon is deposited to a greater initial thickness so that the emitter window is substantially, or more preferably completely filled. Preferably deposition of the polysilicon is continued until the conformal coatings on opposed parts of the window side wall grow together.
In practice, a realistic upper limit on the minimum emitter window width is 1.5 pm, since above this figure an excessive thickness of polysilicon needs to be deposited in order to fill the window. As a consequence of the original profile of sidewall of the emitter window, there will generally be a slight depression 10 in the surface of the polysilicon where the coatings of the sidewalls meet, as shown in Figure 3. The line 11 along which the coatings from the major sidewalls meet may also be marked by a concentration of grain boundaries, although in practice the grain boundaries will tend to be largely eliminated during dopant implantation.
When the emitter window has been filled, the polysilicon is planarised using an appropriate planarising layer, such as photoresist, and a planarising etch.
Preferably the etching is continued until only about 1000-2000A of polysilicon remains over the oxide flanking the emitter window, as shown in Figure 4.
The polysilicon is then heavily doped (in excess of the solid solubility limit) to about l-2x1016 cm 2, typically with arsenic. The lateral extent of the emitter polysilicon is then defined lithographically. The polysilicon is then capped, with for example an oxide of silicon, to prevent out diffusion of arsenic during subsequent processing. The emitter 12 is formed by heating, preferably using rapid thermal annealing for at least a few seconds at 1050-1150 0C, to drive dopant from the polysilicon into the base region.
Further processing is conventional. If oxide was used for the capping layer, it may be left in place to be covered by the dielectric which is subsequently deposited.
It is possible to reduce the thickness, and hence the resistance, of the polysilicon between the emitter metal and the emitter region by siliciding the upper part of the polysilicon. Preferably if silicide is used, the planarising etch of the polysilicon is continued until the polysilicon surface is about 1000-2000A beneath the surface of the oxide which flanks the emitter window. The polysilicon is then heavily doped and as before annealed, using for example a nitride capping layer which is subsequently removed. A metal suitable for siliciding, for example titanium, is then deposited over the surface of the structure and reacted with the polysilicon. After siliciding the unreacted metal is "washed" away by etching. The emitter metal is then formed over the silicide and defined with conventional lithography.
Claims (7)
1. A method of fabricating a bipolar transistor
having a polysilicon emitter contact, the method
including the steps of:
a) defining an emitter window in a dielectric layer
to expose the semiconductor of the active region;
b) depositing polysilicon over the dielectric layer
to fill the emitter window; and
c) planarising the surface of the polysilicon.
2. A method as claimed in claim 1 wherein the
emitter window has a minimum width of no more than
1.5 pm.
3. A method as claimed in claim 1 or claim 2 wherein
after planarisation the thickness of polysilicon on
the active region is greater than or equal to 0.3 pm.
4. A method as claimed in any one of the preceding
claims, the method further comprising the steps of
implanting a dopant species into the planarised
polysilicon, and forming an emitter region by driving
the dopant species into the semiconductor of the
active region.
5. A bipolar transistor made according to the method
of any one of the preceding claims.
6. A bipolar transistor having a polysilicon emitter
contact wherein the surface of the polysilicon emitter
contact which is remote from the active region and
which is over the floor of the emitter window is
essentially planar.
7. A bipolar transistor as claimed in claim 6
wherein the polysilicon emitter contact has a
thickness under said surface of at least 0.3 pm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08711300A GB2204730A (en) | 1987-05-13 | 1987-05-13 | Bipolar transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08711300A GB2204730A (en) | 1987-05-13 | 1987-05-13 | Bipolar transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8711300D0 GB8711300D0 (en) | 1987-06-17 |
| GB2204730A true GB2204730A (en) | 1988-11-16 |
Family
ID=10617266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08711300A Withdrawn GB2204730A (en) | 1987-05-13 | 1987-05-13 | Bipolar transistors |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2204730A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0077921A2 (en) * | 1981-10-23 | 1983-05-04 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US4686763A (en) * | 1985-10-02 | 1987-08-18 | Advanced Micro Devices, Inc. | Method of making a planar polysilicon bipolar device |
-
1987
- 1987-05-13 GB GB08711300A patent/GB2204730A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0077921A2 (en) * | 1981-10-23 | 1983-05-04 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US4686763A (en) * | 1985-10-02 | 1987-08-18 | Advanced Micro Devices, Inc. | Method of making a planar polysilicon bipolar device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8711300D0 (en) | 1987-06-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |