GB2202712A - Telecommunication switching network - Google Patents

Abstract

A telecommunication switching network, e.g. for use in a transit centre, has a three storage switching array with the centre stage including one more switch than needed by the Clos formula. Alternatively it could be a five stage array with the middle three stages forming sub-arrays of which there is one more than needed by Clos. The first and final stages are relatively small matrices (2 x 4 or 4 x 8) which each form a physically integrated assembly with the associated interfacing arrangements. <IMAGE>

Description

TELECOMMUNICATION SWITCHING NETWORK This invention relates to a space switching network which is substantially non-blocking, and which has a low level of blocking under most failure conditions.

Such networks have been used in the past for the switching of speech in analogue, non-multiplex, form.

However, in contemporary practice a more important use of such networks is for switching time division multiplex (TDM) highways, which usually convey speech in puise-code modulation (PCM) form. Other forms of intelligence can also be conveyed digitally, however. In such a system the traffic carried is relatively heavy, so that it is desirable for the network to be non-blocking. It is also desirable for the blocking level to be low under relatively heavy failure conditions.

One switching arrangement designed to meet these criteria has been described in our Patent SpecIfication No. 8607951 (F.H. Rees 31), and this arrangement was intended for use in a system such as that of our Patent Specification No. 8523583 (D.G. Waters 5).

An object of the invention is to provide an improved switching arrangement which is also usable, inter alia, in the system of the above-quoted Paten Specification No. 8523583.

According to the invention there is provided an automatic telecommunication switching arrangement, which includes a multi-stage switching network having a first stage, one or more intermediate stages, and a final stage, wherein all of the switch units of said stages are co-ordinate matrices of fully electronic cross-point elements, wherein the switch units used for the first and the final stages are of small size compared with the switch units used for the intermediate stage or stages, wherein each switch unit of the first stage serves a plurality of inlets to the arrangement and each switch unit of the final stage serves a plurality of outlets from the final stage, wherein each switch unit of the first stage is assembled as a single equipment unit with the inlets which it serves and the interfacing arrangements between those inlets and that first stage switch unit, and wherein each switch unit of the final stage is assembled as a single equipment unit with the outlets which it serves and the interfacing arrangements between that final stage switch unit and the outlets it serves.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a schematic representation of a three stage switching network for use in an arrangement embodying the invention.

Fig. 2 is a schematic representation of a five-stage switching network for use in an arrangement embodying the invention.

Fig. 3 shows a receive line circuit arrangement for use in a system embodying the invention.

Fig. 4 shows a transmit line circuit arrangement for use in a system embodying the invention.

Fig. 5 is another form of receive line circuit.

Fig. 6 is another form of transmit line circuit.

Fig. 7 shows schematically a large transit switching arrangement using a number of switching arrays according to the invention.

The switching arrangement provides traffic port, i.e. inlet and/or outlet, interfaces for transmission links up to the following design maxima (a) 2Mb/sec 4096 ports (b) 8Mb/sec 1024 ports (c) 34Mb/sec 256 ports.

The links are in general multi-channel TDM-PCM links.

Dependent on the size of the arrangement, the switching network may be folded or non-folded, and we will first describe the latter first.

Where an installation has to handle more than one transmission bit rate, physically separate switching arrangements are provided for the different bit rates, and each such arrangement is a three stage or a five stage array. In the interests of security, the central stage of a three stage array, or the middle three stages of a five stage array, include separate sections, so arranged that failure of one section does not cause blocking of the switch. Further, no single failure will disable more than one section. Section in this context means the central stage of a three-stage array or the middle three stages of a five stage array.

First we consider the three-stage switching array, Fig. 1. This follows the Clos formula, but provides one more centre stage than needed for non-blocking operations. Hence the extra section means that one section, a single co-ordinate matrix switch in this case, can fail before blocking occurs. The first and third stage switches are small matrices, as will be seen below.

For the centre stage, the largest size at present envisaged is a 128 x 128 array. This could be assembled from smaller matrices, as will be seen.

The arrangement shown in Fig. 2 is the five stage switching arrangement, which can be regarded as a three stage array in which each centre stage section is itself a three stage array.

For 2Mb/sec or 8Mb/Sec switching arrangement, we use a five-stage switch when more than 512 ports, i.e.

inlets and outlets have to be handled, while for smaller 2Mb/sec and 8Mb/sec and 34Mb/sec arrangements, three-stage structures are used.

Thus a five stage arrangement - Fig. 2 - for 2Mb/sec and 8Mb/sec links uses the following values of X, Y and Z, these letters appearing in Fig. 2 X = 64 for up to 4096 ports X = 32 for up to 2048 ports X = 16 for up to 1024 ports X = 8 for up to 512 ports Y = 16 Z = 4.

A three stage arrangement, Fig. 1, for 2Mb/sec and 8Mb/sec uses the following values of X and Y, Fig. 1 X = 128 for up to 512 ports X = 64 for up to 256 ports Y = 4.

A three stage arrangement, Fig. 1, for 34Mb/sec uses the following values of X and Y, Fig. 1 X = 128 for up to 256 ports X = 64 for up to 128 ports Y = 2.

These values are lower than for the 2Mb/sec and 8Mb/sec case since the links are much heavier traffic carriers in this case, and only 2 ports are desirable in one line card unit for reliability considerations.

Each switching arrangement is constructed from two basic physical sections, a line section and a switch section. The switch section consists of the centre stage of a three stage array, or the middle three stages of a five stage array. The line section to be described below includes the inlet/outlet interfaces and the first or last stage switches, which switches are relatively small (4x8, 2x4) size switches.

These are two basic types of line card unit, one for 2Mb/sec and 8Mb/sec use, and the other for 34Mb/sec. Block diagrams for the line card units for the lower two bit rates are shown in Figs. 3 and 4, and for the highest bit rate in Figs. 5 and 6.

Fig. 3 shows the line card unit for interfacing four PCM links to the switching arrangement. The intelligence is, in the present case, conveyed outside the switch, using the well-known HDB3 format. Each of the four links served has a line interface 1, which re-shapes and amplifies the pulses in the bit stream, and passes them on, still in HDB3 format, to a regeneration and clock extraction unit 2. This passes the bit stream and clock to an encoder 3, which encodes the words in the HDB3 bit stream into a 3B-6B or 17B-18B line code as used in the switching array. The encoded bit stream are then passed on to a first stage switch matrix 4.

The matrix 4 in the present case has four inlets and eight outlets, which go to eight centre stage switch matrices, or eight three stage arrays. These go via a set of eight output drivers 5 to the switch matrices.

In the system described, as set out in our Application No. 8623583 (D.B. Waters 5), the line code used in the switching network has spare combinations so that additional switching and control information can be conveyed. The encoding Is controlled in this way from a control/alarm block 6. This also controls the setting of the switch matrix 5.

The line card unit used at the other side of the network, i.e. at the final switch side, Fig. 4, is in effect the inverse of that just described, so it is not felt that any detailed description of it is needed.

The two line circuits for use for the 34Mb/sec switching arrangement are similar, except that each of the switch matrices is a 2 x 4 switch. This connects two lines, inlets or outlets, to four outlets to the middle stages of the system. One other difference is that the line code used in the switching arrangement is in this case of the 17B-18B type.

If the switching network is of the folded type pairs of outlets from the final switch are interconnected. Alternatively the control means for the final switches can be so designed as to be able to operate the crossports of one switch in such a way that two inlets from the centre stage switch are interconnected. The three lower bit rate systems preferably use folded networks.

Where the system has to provide inter-rack traffic data interfacing with CMOS level signals, the coupling uses balanced differential circuitry, with CMOS drivers to differential receivers. In the present arrangements this has only been found necessary for the 2Mb/sec arrangement; for the other two bit rates, the inter-rack interfacing uses balanced differential signals.

Each line card unit has its own micro-controller - in the control-alarm box - to interface to a shelf controller bus. A shelf accommodates a number of line card units. The micro-controller controls all operations of the line card needed to set up the traffic paths, the code conversion, and test signalling. It also monitors alarms, and co-operates with the other control arrangements, such as those of the switch cards and for the overall system.

Structually the line card unit is either two co-operating cards or one card, dependent on the complexity of the integrated circuit chips. Thus it will be seen that from the structural aspect that the line circuits of the system are integrated with the first or last stage switches.

There are a number of different switch cards, dependent on the bit rates and the switch sizes. These are (a) 2Mb/sec and 8Mb/sec Second and Fourth Stage Card Each such card has circuitry for a 16 input-32 input second stage switch, and a 32 input-16 output fourth stage switch. All input and output signals to the third stage cards use CMOS receivers and drivers connected to the backplane of the shelf in which the cards are accommodated. These give balanced differential signals.

(b) 2Mb/sec, 8Mb/sec and 34Mb/sec Centre Stage Card This is the second stage card for a three stage array and the third stage card for a five stage array.

There are two variants, one of which is a 32 input-32 output switch while the other is a 32 input-64 output switch. Here CMOS is used or Schottky TTL circuitry.

Eight of the 32x64 cards combine on a shelf to provide the largest array used, which is 128x128.

In both cases the cards each have control logic for the switches, including a micro-controller to interface to a shelf controller bus. This enables any one switch crosspoint to be set or cleared under software control without disturbing any other crosspoint. The monitor points for the switch elements can also be connected to the micro-controller to provide for diagnostic monitorings.

The physical assembly, in the three stage arrays, also uses buffer cards - shown in Figs. 3 to 6 as the output driver boxes but actually parts of the line cards - since the signals from the line cards are of different types for the three bit rates. As already indicated, these cards for 2Mb/sec use opto-isolation between the second/fourth stage switch matrices and the line card units. Since each line card unit has access to 4 or 8 centre stage switch units, fan out and fan in are needed.

Thus in the three stage arrays, buffer cards are used to convert the differential signals to/from the line cards into -the CMOS/TTL as needed by the 32x64 and 32x32 switch cards. The buffers are in the switch shelf and are cabled on the front for the differential signals and on to the backplane for the CMOS/TTL signals.

All connections from the line card unit's buffers to the switch card units are made via the shelf's backplane.

As already indicated, a number of cards on the same shelf of a rack share a shelf controller, which is the interface between that shelf and the overall system control means. Further, shelf controllers can each control two shelves, to provide security in the case of failure.

From the physical aspect, one shelf, in the case of a five-stage switching array may carry both second and fourth stage switches, which are cabled by ribbon cables to another shelf which accommodates third stage switch matrices.

Each shelf, whether it is a line card shelf or a switch card shelf has its own power units, which are capable of dualled operation, with two such power units driving two shelves. Hence if one power unit or its input supply fails, the appropriate shelf is still powered.

Fig. 7 shows schematically a large transit switching system which uses switching arrangements, referred to on the figure, as switch blocks. This interconnects a number of 140Mb/sec trunks, which could be optical fibre trunks, and has connections at the other side to local exchanges. The conversion to the exchange side level is effected via a number of stages. Thus from 140Mb/sec conversion is effected in some cases to 45Mb/sec and in others to 34Mb/sec. In addition, conversion from 45Mb/sec is effected to 2Mb/sec in two stages via 6Mb/sec, while the 34Mb/sec is converted to 8Mb/sec, which is then converted to 2Mb/sec. As one progresses rightwards in the upper half of the diagram the numbers of links increases, while in the lower half it decreases leftwards.

The 140Mb/sec and 4SMb/sec switch blocks can be constructed using similar techniques to those used for the other ones. Alternatively they can be basically single stage co-ordinate matrices.

Note that folding is effected at four stages in the system via the TRANSIT PATHS.

Claims (8)

1. An automatic telecommunication switching arrangement, which includes a multi-stage switching network having a first stage, one or more intermediate stages, and a final stage, wherein all of the switch units of said stages are co-ordinate matrices of fully electronic cross-point elements, wherein the switch units used for the first and the final stages are of small size compared with the switch units used for the intermediate stage or stages, wherein each switch unit of the first stage serves a plurality of inlets to the arrangement and each switch unit of the final stage serves a plurality of outlets from the final stage, wherein each switch unit of the first stage is assembled as a single equipment unit with the inlets which it serves and the interfacing arrangements between those inlets and that first stage switch unit, and wherein each switch unit of the final stage is assembled as a single equipment unit with the outlets which it serves and the interfacing arrangements between that final stage switch unit and the outlets it serves.

2. An arrangement as claimed in claim 1, and wherein the switching network has three stages,m the central switching stage having one more co-ordinate matrix than is called for by the Clos formula to avoid blocking.

3. An arrangement as claimed in claim 1, wherein the switching network has five stages with the second, third and fourth stages made up of a number of three-stage sub-networks is one more than called for by the Clos formula to avoid blocking.

4. An arrangement as claimed in claim 1, 2 or 3, and wherein each of the first and the last stage switches is a 2x4 or 4x8 co-ordinate matrix.

5. An arrangement as claimed in claim 1, 2, 3 or 4, wherein the equipment units at the first stage end each include means to convert incoming bit streams into a line code for use within the switching network, and wherein at the final stage end the equipment units each include means to convert the bit stream out of said line code.

6. An arrangement as claimed in claim 1, 2, 3, 4 or 5 and wherein the switching network is at least partly folded.

7. An automatic telecommunication switching arrangement substantially as described with reference to the accompanying drawings.

8. An automatic telecommunication switching system which includes a number of arrangements each as claimed in any preceding claim, but which functions at different bit rates.