GB2202356A - Configurable combinational logic circuit - Google Patents

Description

a 1 22_02356 Q381OGB/ALM/mkf

Description of Invention

11Configurable Combinational Logic Circuit" THIS INVENTION relates to configurable combinational logic circuit and, in particular, to such a logic circuit for a configurable logic element which is composed of the configurable combinational logic circuit, a configurable storage circuit and a configurable output select logic. The output signals of the configurable storage circuit serve as input signals to both the configurable combinational logic circuit and the output select logic. The output signals of the output select logic are selected from the output signals of the combinational logic circuit and the output signals of the storage circuit.

In US Patent Application Serial No. 06/588,478, filed March 12, 1984 by Ross H. Freeman and entitled 11CONFIGURABLE LOGIC ARRAY", a structure is described which allows changing the configuration of a finished integrated circuit from time to time (even when the integrated circuit is installed in a system) to provide any one of a plurality of logical functions from the same integrated circuit. This is accomplished by providing a number of 11configurable logical elements" (herein referred to as 11configurable logic elements") each of which is capable of bieng configured to implement any one of a plurality of logic functions depending on the task which it is called upon to perform. By conf igurable logic element is meant a combination of devices which are capable of being electrically interconnected by switches operated in response to control bits stored on the chip (or transmitted to the chip) to perform any one of a plurality of logical functions. The configurable logic element disclosed in Application No. 06/588,478 may include all of the circuit elements necessary to provide one or more of the functions provided byg for example, an AND gate, flip-flop, inverter, NOR gate, exclusive OR gate, and combinations of these functions to form more complex functions. The particular function to be carried out by a configurable logic element is determined by control signals applied to the configurable logic element from control logic. Depending on the control signals, a configurable logic element can function as an AND gate, an OR gate, a NOR gate, a NAND gate, or an exclusive OR gate or any one of a number of other logic functions without change in physical structure. Structure is provided on chip to allow any one of a plurality of functions to be implemented by the configurable logic element. This is done by providing control logic to store and generate control signals which control the configuration of the configurable logic element.

In one embodiment, the control signals are stored and transmitted by control logic formed integrally with and as part of the integrated circuit chip containing the configurable logic elements. However, if desired, the control information can be stored and/or generated outside the integrated circuit and transmitted through pins to the configurable logic element.

In general, a given set of control signals in the form of control bits is transmitted from the control logic to a configurable logic element to control the configuration of that configurable logic element. The actual set of control bits provided to the configurable logic element on the integrated circuit chip depends on the function to be carried out by the configurable logic element on the chip.

1 Our Co-pending - Patent Application No. 8604761, from which the present Application is divided, claims a configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary, feedback signals; means for selecting K of said M+N binary signals (where K4=N+W; combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating binary output signals; a configurable storage circuit for receiving selected ones of said binary output signals of, said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configrations; and a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic.

The present invention provides a configurable combinational logic circuit for such a configurable logic element, comprising first configurable means for receiving K binary input signalsp said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of output signals said second set being a second subset of said K input signals wherein said first set is not equal to said second set; first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit; and first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory.

In order that the invention may be more readily understood, an embodiment thereof will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 illustrates some of the various logic functions capable of being implemented by a configurable logic element in a configurable logic array; Figure 2 illustrates the internal logic structure of one possible configurable logic element capable of implementing a number of useful functions of two variables A and B; Figure 3A illustrates a 16 bit RAM circuit wherein any one of sixteen possible input states is capable of bieng identified and 2 16 functions are capable of being implemented; Figure 3B illustrates a selection structure for selecting any one of sixteen bits capable of implementing 216 functions, for transmittal to an output lead; Figure 3C illustrates one possible Karnaugh map for the structure of Figure 3A; Figure 3D illustrates the logic gates represented by placing a binary one in the Karnaugh map of Figure 3C at the intersections,of the first and second rows and the 1 first column.

Figure 4A illustrates a plurality of configurable logic elements (shown as nine logic elements) formed on an integrated circuit chip together with programmable interconnects formed between selected leads to yield desired logic functions and with selected input/output pads and interconnections of the leads between logic elements; Figure 4B shows the key to the cross-connections between crossing conductive leads in Figure 4A; Figure 5 represents a portion of the circuitry of a novel combination static and dynamic shift register appropriate for use with the configurable logic array; Figures 6A through 6H represent wave forms of use in explaining the operation of the structure of Figure 5; Figure 7 shows a configurable logic element according to the invention of co-pending Application No.

8604761; Figure 8 shows one embodiment of the configurable logic element of Figure 7 including a configurable combinational logic circuit according to the present invention; and Figure 9 shows one embodiment of a storage element included in the logic element of Figure 8.

The following detailed description of this invention is meant to be illustrative only and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the following disclosure.

Figure 1 illustrates certain logic functions capable of being implemented by a configurable logic element. The (1 1 1 2 3 4 6 7 8 9 11 12 13 14 16 17 18 19 21 22 23 24 26 27 28 29 31 32 33 output.

34 27 "D" flip-flop. with set 28 M" flip-flop with set and inverted outDut 36 of course, other logic functions can also be imple37 mented in a configurable logic element. 38 6 7 9 10 11 12 13 14 15 16 17 is 19 20 21 22 23 24 25 26 28 functions shown in Figure 1 are merely illustrative and other elements not shown can, if desired, be implemented by a config-urable logic element. The following functions are shown:

Element Function AND gate NAND gate AND gate with inverted input NAND gate with inverted input OR gate NOR gate exclusive OR gate exclusive NOR gate 3 input AND gate 3 input NAND gate 3 input OR gate 3 input NOR gate OR gate with one input comprising AND gate NOR gate with one input comprising AND gate AND gate with one.input comprising OR gate NAND gate with one input comprising OR gate 3 input AND gate with one input inverted 3 input NAND gate with one inverted input 3 input OR gate with one inverted input 3 input NOR gate with one inverted input one of two inputs multiplexer inverting one of two inputs multiplexer "D" flip flop with reset Set-Reset latch "D" flip-flop with reset and inverted output set-reset latch with reset and inverted 1 c 1 8 9 11 12 13 14 is 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 signal of AND gate 24 is a logical 0, and since the 31 tr-t-state control input signal to NOR gate 26 is a logi32 cal 0, it ' is easy to see that AND gate 25, AND gate 24 33 and NOR gate 26 function together as a NAND gate with 34 respect- to input signals A and B. Since the tri-state 35 control signal input to NOR'gate 27 is a logical 0 (except 36 during reset), NOR gate 27 serves as an inverter with 37 respect to the out-nut signal of NOR gate 26. The output 38 2 Figure 2 illustfates the internal logic structure of 3 one possible configurable logic element which is capable of implementing all useful basic functions of the two 4 variables A and B, with the functions being selected by configuration control signals CO, E5, Cl, through 6 CS on control leads CO, CO, through CS. (In this 7 example, all control leads are connected to the gates of N channel enhancement mode pjass transistors.) To implement an AND gate function using the structure shown in Figure 2, the input leads labeled A and B are shunted past inverters 21 and 22, respectively, to AND gate 25 by high level signals on the Cl and CO configuration control leads. which, being connected to the gates of N channel enhancement mode pass transistors 29c and 29d, cause pass transistors 29c and 29d to turn on.

Low level signals are applied to the configuration control leads 23 and M, thus blocking the output signals of inverters 21 and 22 from AND gate 25. In addition, a high level signal on lead CS is applied to enable AND gate 25. Thus three input AND gate 25 functions as a two-input AND gate with respect to the signals A and B. The output signal of AND gate 25 provides one input signal to NOR gate 26. A second input signal to NOR gate 26 is provided by the output signal of AND gate 24. 'The output signal of AND gate 24 is held at a logical 0 by applying a logical 0 to configuration control lead C4. Thus the control signals C2 and C3 are "don't cares", that is, these signals can be high or low without affecting the outiDut signal of AND gate 24. -. Since the output If T 9 10 11 12 13 14 is 16 17 18 Figure 3A illustrates a 16 bit RAM capable of producing 19 an output signal in response to any one of sixteen possible 20 combinations of input signals. Thus input signals A and 21 B control the X decoder to select any one of the four 22 columns in the 16 bit RAM. Input signals C and D contrio 1 23 the Y decoder to select any one of the four rows in the 24 16 bit RAM. The 16 bit RA14 produces an output signal 25 representative of the bit at the intersection of the 26 selected row and column. There are 16 such intersections 27 and thus sixteen such bits. There are 2 16 possible 28 combinations of functions capable of being represented by 29 16 bits.' Thus, if a NOR gate is to be simulated by the 30 16 bits in the RA14, the Karnough map for the RAM would be 31 as shown in Figure 3C. In Figure 3C all bits are 11011 32 except the bit at the intersection of the first row 33 (representing A=O, B=O) and the-first column (representing 34 C=O, D=O). Should a less frequently used function be 35 desired to be generated by the 16 bit RAM, (for example, 36 should a '11" output signal be desired for A=l, B=O, C=0 37 and D=O) then a binary 11111 is stored at the intersection 38 1 signal of NOR gate 26 is applied to the gate of N channel 2 transistor 29a (the source of which is grounded and the 3 drain of which is connected to output lead 28) and the complement of the output signal of NOR gate 26 is applied to the gate of N channel transistor 29b (the source of 6 which is connected to a power supply and the drain of 7 which is connected to both the output lead 28 and the 8 drain of N channel transistor 29a). Thus, transistors 29a and 29b function as an inverter with respect to the output signal of NOR gate 26. Thus, the structure of Figure 2 configured as described above performs the function of an AM gate with respect to the signals A and B. Other logic functions can also be produced by appropriate selection of the control signals to be supplied to the configuration control leads CO through CS to activate the appropriate pass transistors and gates within the structure.

t 1 2 3 1 of the second row and the first column. Should a binary "1" be desired both when A=O, B=O, C=0 and D=0 and also when A=l, B=O, C=0 and D=O, then a binary 11111 is stored 4 at each of the intersections of the first column with the 5 first row and the second' row. The logic circuit repre6 sented by this loading of the RAM is as shown in Figure 7 3D. Thus the RAM of Figure 3A represents an elegant and simple implementation of any one of 216 logic functions.

Figure 3B shows another structure for yielding any one of sixteen select bits. Each of registers 0-15 in the vertical column to the left labeled 1116 Select Bits", contains a selected signal, either a binary 1 or 0. By 8 9 10 11 12 13 selecting the proper combination of A, B, C, and D, a 14 particular bit stored in a particular one of the sixteen 15 locations in the 16 Select Bits register is transmitted 16 to the output lead. Thus, for example, to transmit the 17 bit in-the 11111 register to the output lead, the signal A, 18 B, C, D is applied to the leads so labeled. To transmit 19 the signal labeled 111511 in the sixteenth location in the 20 16 Select Bits register to the output lead, the signal A, 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 and f) is applied to the appropriate columns.

16 Again, any one of 2 logic functions can be implemented using this structure.

Figures 4A illustrates a configurable logic array containing nine configurable logical elements. As shown in Figure 4a, each CLE of the nine CLEs 40-1 through 40-9 has a plurality of input leads and one or more output leads. Each input lead has a plurality of access junctions each conn--cting a selected general interconnect lead to the input lead. The access junctions for input lead 2 of CLE 407 are labeled A1 through A4 in Figure 4a. The access junctions for the other input leads are indicated schematically but are not labeled for the sake of clarity. Similarly, each outDut lead of each CLE has a plurality of access junctions each connecting the output lead to a corresponding one of the general interconnect leads. The access junctions are indicated schematically for each output lead of each CLE in Figure 4a. The access junctions for the output lead of CLE 40-7 are labeled B1 through BS. The leads in Figure 4a which are neither input leads nor output leads are called general interconnect leads and the junctions in Figure 4a which are not access junctions for input and output leads are called general interconnect junctions. As shown in 8 Figure 4A, nine logic elements are placed on an integrated 9 circuit chip together with programmable access junctions and a general interconnect structure which comprises 11 general interconnect leads and programmable general 12 interconnect junctions for connecting various leads to 13 other leads. The general interconnect structure includes 14 a set of general interconnect leads and of programmable junctions interconnecting the general interconnect leads 16 having the property that for each general interconnect 17 lead in the general interconnect structure there is a 18 programming of the general interconnect junctions which 19 connects the given general interconnect lead to one or 20 more other leads in the general interconnect structure. 21 Moreover, there is a programming of the junctions (both 22 access and general interconnect) such that for any given 23 output lead of any CLE in the CLA, and for any given 24 input lead of any other CLE in the CLA, there is a pro- gramming of the junctions such that the given output lead 26 is connected to the given input lead. An electrical path 27 from a given output lead to a given input lead always 28 contains at least two access junctions and at least a 29 portion of a general interconnect lead.. For example, one 30 31 32 33 34 36 37 38 electrical path from the output lead of CLE 40-8 to the second input lead of CLE 40-9 contains access junctions A7 and B7 and the marked portion P of a general interconnect lead. Typically, an electrical path from an output lead of one CLE to an input lead of another CLE will also contain one or more general interconnect junctions. Each of logic elements 40-1 through 40-9 represents a collection of circuitry such as -Ehat shown in Figure 2 or some 1 1 t similar structure capable of being configured as described 2 above in Figure 2 to perform any one of a number of logic 3 functions. To program the circuitry (both the configurable 4 interconnect switches and the configurable logic elements), 5 selected signals are applied to input leads identified as 6 configuration control input leads thereby to generate a 7 desired logical function in each of the logic elements 8 9 11 12 13 14 -15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 and to interconnect the logic elements as desired. In Figure 4A, no specific lead has been identified as an input lead for the configuration control signals. However, any particular I/P pad can be selected for this purpose. The configuration control bits can be input into the configurable logic array either in series or in parallel depending upon design. considerations where they are typically stored in a programming register (shown in Figure 5). Alternatively, the configuration control bits may be stored in a memory on chip. In addition, another I/0 pad will be used for an input clock signal which is used, inter alia, for the loading of the configuration control signals into the programming register. When the configurable logic array shown in Figure 4A has been configured, selected output signals of logic elements 40-1 through 40-9 are provided to selected I/0 pads. Figure 4B illustrates the meaning of the junction symbols used in Figure 4A.

To configure a logic element such as logic element 40-1 (Figure 4A), a number of bits must be applied to the configuration control leads such as leads CO through CS, as shown,' for example, in Figure 2. To do this a shift register, for example, is utilized as part of each configurable logic element. Figure 5 illustrates a shift register which may be used. The shift register of Figure 5 is illustrated showing two basic storage cells. Each storage cell is caDable of storing one bit of information. of course, an actual shift register will contain as many storage cells as required to configure the logic element of which the shift register is a part, to its desired 1.2 configuration. in operation, an input signal is applied to input lead 58. This input signal (shown in Figure 6D) contains bit stream to be stored in the shift register as configuration control bits to configure the conf igurable logic element to perform a desired logic function or to 6 configure (program) an access junction or a general 7 interconnect junction between general interconnect leads 8 in a manner to be described shortly. Thus the sequence of pulses applied to input lead 58 represents those pulses which when stored in the storage cells of the 11 shift register will activate the configuration control 12 bits in the proper manner to achieve the desired functional 13 and/or interconnection result. For example, if the 14 circuit of Figure 2 is to be configured to form an AND gate, the pulses CO, Cl, C2, C3, C4, and CS would be 16 represented by 1,1,X,X, 0,1.

17 The sequence of pulses applied to input lead 58 is 18 synchronized with clocking pulses 01 and 02 applied to 19 leads 57 and 59 respectively. Thus in the first period of operation clocking pulse 4)l goes high (Fig. 6A), 21 clocking pulse 4)2 is low (Fig. 6B), the hold signal (Fig.

22 6C) is low during shifting thereby facilitating the.

23 passage of data through sequentially connected cells 5-1, 24 5-2 et al. of the shift register. To shift the pattern 01010 into the shift register, the following operations 26 occur: The input signal on lead 58 is low during approx 27 imately the first half cycle of the clocking period ti.

28 The output signal N of inverter 51-1 goes to a high.

29 level in response to the low level input signal and cpl high to enable pass transistor 53-1. Some time through 31 the first clocking period tl, the clock signal 4)l goes 32 low (Fig. 6A) and the clock signal (P2 shortly thereafter 33 goes high (Fig. 6B) to enable pass transistor 55-1.

34 Consequently, the higi level output signal N is trans mitted to the inDut lead of inverter 52-1 by enabled pass 36 transistor 55-1 and thereby produces a low level output 37 signal Q1 on the out-cut lead of inverter 52-1. Thus at 38 1 13 1 the end of period ti, the output signal Q1 (Figure 6F) 2 from inverter 52-1 is low level. The output signals 2 3 and Q2 from inverters 51-2 and 52-2 in the second cell 4 are still indeterminate because no known signal has yet propagated to the second storage cell 5-2 to change the 6 signals of these inverters to a known state.

7 At the beginning of the'second period (labeled "t2" 8 in rig. 6A), 01 goes high (Fig. 6A) and 02 is low (Fig.

9 6B) having gone low before period tl ended. The input signal (Figure 6Dj now has risen to a high level repre 11 senting a binary 1 and thus the output signal 1 of 12 inverter 51-1 has gone low. The output signal 91 of 13 inverter 52-1 remains low because pass transistor 55-1 is.

14 held off by the low level 02 signal. Some time through the second period 01 goes low followed a fraction of time 16 later by 02 going high. At this time, the output sig 17 nal 1 is transmitted through pass transistor 551 to 18 inverter 52-1 thereby driving the output signal Q1 from 19 inverter 52-1 to high level. Meanwhile, during period t2 the previous low level signal on Q1 has driven the output 21 signal 2 of inverter 51-2 to a high level when Q1 was at 22 a high level to enable pass transistor 53-2 and the 23 change in 4)2 from a low level to a high level in the 24 second half of period t2 to enable pass transistor 55-2' drives the output signal Q2 from inverter 52-2 to a low 26 level. In this manner, the input signal on lead 58 (Fig.

27 6D) is transmitted through each of the cells 5-1, 5-2, 28 5-3 et al. in the shift register. Upon the transfer into 29 the shift ' register of the desired information, the hold signal (Figure 6C) is enabled (i.e., driven to a high 31 level) thereby to connect the fe edback leads 50-1, 50-2, 32 and 50-3 et al. from the but-Dut leads of inverters 52 to 33 the input leads of inverters 51 so as to hold the infor 34 mation then in each cell indefinitely. In operation, the signal stored in a given cell e.g. 5-1 is connected to a 36 con-figuration control or to an interconnect pass device.

37:such as devices 60-1. an-d 6D-2 illustr'ate.d - sc:hefnatib.ally 38 in 'Figure 5.

/I/- - The output signals QV QV Q27 Z2, etc., of the shift register are directly connected to the (configuration) control inputs of a logic element or the pass devices of the general interconnect junctions.

When 1 is low, 42 and hold may be brought highp thus holding the data indefinitely. The entire shift' register may be set or cleared by setting or clearing the input with 1 and 42 both high and HOLD low. Enough set/reset time must be allowed for the signal to propagate the entire length of the shift register to clear the shift register in this manner. Naturally this time is dependent upon the length of the shift register.

The shift register operates in its dynamic phase by storing the information being shifted as charge on the gates of the transistors (not shown in Figure 5 but well known) comprising inverters 51-1, 52-1, 51-2, 52-2 et al of the shift register. These inverters are of well-known design and will not be described in detail. The use of a dynamic shift register is important because a dyanmic shift register uses six transistors and thus takes up very little area. The dynamic shift register is converted to a static latch by adding only one transistor. Thus the dynamic shift register (static latch) can be easily fabricated as part of a configurable logic element without adding significant complexity to the circuit or consuming significant semiconductor area. Because of the "hold" signal, the dynamic shift register can become a static latch because placing the shift register on hold automatically refreshes the data. Thus a separate refresh circuit is not needed.

It is apparent from the above description that the dynamic shift register (static latch) circuit does not need refreshing once it has been latched into a hold state. This is accomplished by use of the feedback circuit comprising lead 50-1 and pass transistor 54-1 in cell"5-1, for example.

A /5 - t 1 Fig. 7 shows a block diagram of the configurable logic element 99 of the present invention which includes 3 configurable combinational logic 100, configurable stor4 age circuit 120 and configurable output select logic 140. 5 The combinational logic 100 receives the N binary input 6 signals to the configurable logic element 99 and M binary 7 "feedback" signals from storage circuit 120. Combinational 8 logic 100 is configurable into a plurality of configura- 9 tions. Each con'figuration implements one or more selected 10 combinational logic functions of one or more selected 11 subsets of the input signals to the combinational logic. 12 Since combinational logic 100 is configurable, it can be 13 employed to implement a variety of different functions.

14 Moreover, two or more selected functions may be implemented simultaneously, appearing on separate output leads of the 16 configurable logic element 100. In more detail, combina 17 tional logic 100 selects K binary input signals from 18 among its M+N binary input signals (K<M+N). Combinational 19 logic circuit 100 is responsive to a plurality of sets of values of a first set of configuration signals including 21 at least a first set of values for which configurable 22 combinational logic 100 implements a first set of func'23 tions, each of which is a function of some of said K 24 binary signals, and a second set of values for which 25 configurable combinational logic 100 implements a second 26 set of functions, each of which is a function of some of 27 said K binary signals, where said first set of functions 28 29 30 31 32 33 34 35 36 37 38 is not the same as said second set of functions. In one embodiment combinational logic 100 has a first configura- K 1 tion which implements a selectable 1 of the 2 binary valued functions of these K binary signals and a second configuration which implements both a selectable 1 of the 2 (K 0 - 2 binary valued functions of a first selected (K-1) of the Y, selected binary input signals and a selectable 1 of 2 (K -/) the 2 binary value functions of a second selected (K-1) of the K selected binary inputsignals.. (The second set 16 1 lk- ' 1 of K-1 signals need not be distinct from the first set.) 2 The operation of combinational logic 100 will be more 3 readily understood after a consideration of the specific 4 embodiment described in Fig. 8 which is explained hereafter.

Storage circuit 120 is also configurable and may be 6 prog.rammed..to implement, depending on the configuration, 7 one or more storage elements each of which may.be, for example, a transparent latch with set and reset, a D flip-flop with set and reset, an edge detector, a stage 8 9 11 storage circuit 120 receives the output signals of combina 12 tional logic 100 on bus 161 as well as a clock signal and 13 selected ones of the N input signals of combinational 14 logic 100 on input bus 160. output select logic 140 is configured to provide output signals which are selected 16 from among the output signals of the combinational logic 17 element and the storage circuit.

18 Fig. 8 shows the details of one embodiment of the 19 configurable logic element 99 in Fig.7.. In Fig. 8, the four input signals to the confi ' gurable logic element 99 21 are denoted by A, B, C, D (i.e., N=4). Since the storage 22 circuit 120 provides only a single feedback signal Q to 23 switch 107, M=1. In Fig. 8, K=4 since the signals A, B, 24 C and either D or Q are selected from among the five signals A, B, C, D, and Q. Configurable combinational 26 logic element 100 includes config-urable switches 101 27 through 107, 113, and 114, 8-bit RAMs 108 and 109, one of 28 eight select logics 110 and 111, multiplexer 112, and 29 configuratibn control lead 115 to switches 113 and 114.

Each of the config-urable switches is configured by control 31 bits from a programming register (not shown) on leads 32 (not shown except for lead 115) as previously explained.

33 -Switch 101 may be configured to provide signal A as its 34 output signal or it may be configured to provide signal B as its output signal. Similarly, each of the switches 36 102 through 107 may be configured to provide a selected 1 37 of its two input signals as its output signal. Thus, for 38 example, for one selection of configuration control bits, of a shift register, or a stage of a counter.

A Configurable r 1 17 _ 1 (---2 3 switch 107 provides signal D and the binary signals A, C, and D are provided to both one of eight select logic 110 and one of eight select- logic ill by switches loi through 4 103 and 104 through 107, respectively. For each of the 5 eight possible combinations' of binary signals A, C and D, 6 select logic 110 selects a unique storage element in RAM 7 108 and outputs the bit stored in the selected location. 8 one of eight select logic ill- operates similarly with respect to 8-bit P-AM 109. Multiplexer 112 provides either the output signal from select logic 110 or the output signal from select logic 111, depending on the state of signal B. For this configuration, the control bit applied on lead 115 causes switches 113 and 114 to simultaneously pass the output signal from multiplexer 112 to output leads Fl and F2 of combinational logic element 100. The two 8-bit RAMs 108 and 109 can be 16 programmed with binary bits in 2 different ways. Each choice of programming of the 8-bit RAI4s causes the combi national logic of element 100 to implement one of the 16 2 2 =2 possible logic functions of the four binary variables A, B, C and D. (Here K=4. (A logic function is a binary valued function of binary variables.) For another selection of configuration control bits,_ switch 107 provides feedback signal Q from storage circuit 120 and switches 101 through 103 and 104 through 107 and 113 and 114 are configured as before. Then the combina- 11 12 13 14 is 16 17 18 19 21 22 23 24 26 27 28 29 31 32 33switthes 1'0.1-r-hrough 103 provide signals A, C and Q, and 34 switches 104 through 106 Drovide signals B, C, and Q, resDectively, and the control- signal applied to lead 115 36 causes switches 113 and 114 to provide the output signal 37 of select 110 on lead F2 and the output signal of se 38 lect 111 on lead Fl, respect^ ively. Thus., this configura- tional logic element 100 implements one of the 2 16 =2 21r possible logic functions of.the four binary variables A, B, C and 9_ for each choice of programming of the two 8 bit rams 108 and 109. (Here again K=4.) For another selection of configuration control bits, 1 tion implements on lead Fl one of the iB =2 2 logic func2 tions of the three binary variables A, C, and Q for each 3 of the 2 a possible programmings of 8-bit RAM 108 and on 4 lead F2 implements one of the 2 8 logic functions of the 3 6 three binary variables B, C and Q for each of the 2 a =2 2 7 possible programmings of RAM 109.

8 9 10 11 12 13 of the first selection of three variables on output lead 14 F2 for each of the 2 8 possible proarammings of 8-bit RA14 is 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 In general, for any first selection of three of the four variables A, B, C and D/Q, and for any second selection of three of the four variables A, B, C and D/Q, there is a configuration of the combinational logic ele2 ment 100 which implements one of the 2 2 logic functions -9 108 and one of the. 2 2 logic functions of the second selection of three variables on output lead Fl for each of the 2 8 possible programmings of RAM 109.

In another embodiment (not shown), each of the 8-bit RAMs may be "subdivided" by providing each with two additional one of four select logic so that any four binary functions of two of the variables A, B, C and D/Q are implemented on four additional output leads of the combinational logic element 100. Similarly, in another embodiment (not shown) a 32 bit RAM and the signals A, B, C, and D and the feedback signal Q are all used (so that J5" K=5) to implement in one configuration one of the 2 binary functions correspondi,ng to each.programing of the 32 bit RAM (here N=4, M=l, and K=5) In another configura tion (not shown) N=4, M=l, K=5, and a first binary function Fl of the variables A, B, C a second binary function F2 of the variables B, C, D and a. third binary function F3 of the variables B, C, D, Q are implemented. It is Kt Kt K KO 2 3 important to observe -hat 2 1 + 2 + 2 2 where K' 1 is the number of variables of which F i is a function for i=l, 2, 3. Returning to Figure 8, it is also important 1 1 1 l- 1 C7 to observe that configurable switches 101, 102 and 103 select a subset of their input signals and provide the selected subset of input signals on a one-to-one basis to selected input leads of circuit 110. For example, in response to one set of values of configuration signals, configurable switches 101, 102 and. 103 provide signal A 7 to lead 110-3, signal B to lead 110-2, and signal C to lead 110-1.

9 The output signals on leads Fl and F2 are input signals to config-urable storage circuit 120. Signals A, 11 C, and D are also input signals to storage circuit 120.

12 Configurable storage circuit 120 includes programmable 13 switches 122, 123, 126, 127 and 128, exclusive OR gates 14 124, 129 and 130, AND gates 125, 131 and 132, and storage element 121. Storage element 121 has a set, reset, data 16 and clock input leads denoted by 5, R, D and Ck, respec 17 tively, and output leads Q FF and Q LA 18 Switches 123, 126, 127 and 128 are each configured 19 to select one of their input signals as an output signal.

The set, clock, and reset functions associated with the 21 set, clock, and reset input leads of storage element 121 22 are all active high but each may be rendered a ctive low 23 relative to the output signal of switches 123, 127, and 24 129 respectively by applying a logical 1 to the leads INVS, INVC, and INvR of exclusive or gates 124, 129, and 26 130 respectively. (If a logical 0 is applied to leads 27 -INVS, INVC, and INVR, the polarity of the output signals 28 of the exclusive-or gates 124, 129, and 130 is the same 29 as that 61 the input signals. If a logical 1 is applied to leads INVS, INVC, and INVR, the output signals of 31 exclusive-or gates 124, 129, and 130 are the inverse of 32 33 34 35 36 37 38 the input signals.) The AND gates 125, 131, and 132 are enabled by applying a logical 1 to the input leads ENS, ENC, and ENR respectively (and disabled by applying a logical 0). if a logical 0 is applied to one of the input leads ENS, ENC, or ENR, the output of the AND gate is a logical 0 1 and the associated function of memory circuit 121 is 2 disabled regardless of the state of the corresponding 3 exclusive OR gate. Q= provides a flip-flop output signal and Q LA provides a latch output signal as explained later in conjunction with Fig. 9. Configurable switch 6 122 selects one of the binary singals on leads Q FF and QLA and the output signal Q of switch 122 is an input signal to the output select logic 140 and to the configurable combinational logic 100.

Fig. 9 shows one embodiment of memory circuit 121.

7 8 9 10 11 Memory element 121 comprises two I'DII latches LA1 and LA2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 connected in series thereby implementing a flip-flop. Latch LA1 includes N channel pass transistors P1 and P2 and NOR gates GI and G2. The gates of pass transistors p 1 and P 2 are controlled by the signals UKand CK, respectively. Similarly,. latch LA2 includes N channel pass transistors P3 and P4 and NOR gates G3 and G4. The g ates of transistors P3 and P4 are controlled by the signals CK and UKR, respectively. The-D input lead is the data input lead of latch LAI. The S input lead serves as the set input lead of latch LA1 and as the reset input lead of latch LA2. The R input lead serves as the reset input lead of latch LA1 and as the set input lead of latch LA2.

The output signal QLA of NOR gate G1 is connected to the data input lead of. latch LA2. The output lead QLA is connected to the output lead of NOR gate G2 of latch LA1 and the output lead QFF is connected to the output lead of NOR gate G3 of latch LA2.

Configurable storage circuit 120 (Fig. 8) operates as a transDarent latch with set and reset by configuring switch 122 to connect output lead Q to output lead Q LA The output signal on lead Q LA follows the input signal while the clock signal CK is low. The output signal on QLA is held when the clock signal CK goes high, turning off pass transistor P 1 and turning on pass transistor P 2 Thus, the data signal is transmitted to output lead Q LA 1 21 t fl Storage circuit 120 may also be configured to operate as a D flip-flop with set and reset. In this configura tion, switch 126 is configured to select the signal on 4 lead F 1 and gates 125, 131 and 132 are enabled by applying -5 a logical 1 to leads ENS, ENC, and ENR, respectively.

6_ Finally, switch 122 is config-ured to select the output 7 signal on lead Q FF of storage element 121. Storage 8 element 120 may also be configured as a D flip-flop 9 without set and reset by modifying the above configura tion by applying a logical zero to leads ENS and ENR.

11 Configurable storage circuit 120 may also be config- 12 ured to be an RS latch by enabling AND gates 125 and 132,.

13 and disabling AND gate 131 so that a logical 0 input 14 signal is provided on the Ck input lead of storage element 121. The logical 0 on lead Ck turns off pass transistor 16 P3 and turns on pass transistor P4. Switch 122 is then 17 configured to select the output signal on Q FF 18 Finally, storage circuit 120 may also be configured 19 to be an edge detector. For example, to configure storage element 120 as a rising edge detector, AND gate 125 is 21 disabled to provide a logical 0 on input lead S, AND gate 22 131 is enabled to pass a clock signal to input lead Ck, 23 and switch 126 is configured to select input lead 126a so 24 that a logical 1 is provided to input lead D. AND gate 132 is enabled. A logical 1 reset signal forces the 26 output signal on Q FF to a logical 0. A low clock signal 27 turns off pass transistor P2 and P3 and turns an pass 28 transistor P1, permitting NOR gate Cl to invert the 29 logical 1. on lead D, thus providing a logical 0 on node Q-LA When the clock signal rises. transistors P1 and P4 31 are turned off, transistors P2 and P3 are turned on, and 32 the logical 0 on node LA is inverted by NOR gate 23, 33 thusproviding a logical 1 on' output lead Q FF which 34 signals that a rising edge has been detected. QFF is then reset to 0 using the reset input and the edge detector 36 is then ready to detect the next rising edge. (Note that 37 when the clock signal falls, transistors P2 and P3 are 38 C2.2 turned off and transistor P4 is turned on, and the signal 2 on Q FF remains a logical 0 and does not change state 3 until the next rising edge.) 4 Similarly, storage circuit 120 may be configured as a falling edge detector by applying a logical one signal 6 to lead INVC -of exclusiveor gate 129. Clearly, storage 7 circuit 120 may also serve as a stage of a shift register 8 or a stage of a counter.

9 The output select logic 140 includes configurable switches 141 and 142 which are each configured to select 11 an output signal from among the output signals on leads 12 F1 and F2 from the combinational logic 100 and the output 13 signal of storage element 120.

14 The above embodiments are intended to be exemplary 15 and not limiting. It will be obvious in view of the 16 disclosures made ahove that various substitutions and 17 modifications may be made without departing from the 18 S'dope of the inventfan.,.

19 In the claims which follow, the phase "means having a configuration in which said means" performs a particular 21 function is used in place of the detailed wording "means 22 which are capable of being configured in response to a 23 selected set of values of a set of configuration signals 24 and which, when configured by said selected set of values," 25 performs a particular function.

26 27 28 29 30 31 32 33 34 35 36 37 38 3

Claims (6)

CLAIMS:

1. A configurable combinational logic circuit for such a configurable logic element, comprising first configurable means for receiving K binary input signals, said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of output signals said second set being a second subset of said K input signals wherein said first set is not equal to said second set; first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit; and first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory.

2. A configurable combinational logic circuit as in claim 1, further including: second configurable means for receiving said K binary input signals, said second configurable means having at least a first configuration in which said second configurable means generates a third set of output signals, said third set being a third subset of said K input signals, and a second configuration in which said second configurable means generates a fourth set of output signals, said fourth set being a fourth subset of said K input signals, wherein said third set is not equal to said fourth set; second memory means having a plurality of storage locations, 2 41- each of said storage locations for storing a binary bit; second location selection means for receiving said output signals of said second configurable means and for selecting a storage location within said second memory means in response to said output signals of said second configurable means said second location selection means providing a second output signal representing the data bit stored in said selected storage location within said second memory; and steering logic means for receiving said first and said second output signals of said first and said second location selection means, said steering logic means having a first configuration in which said steering logic means provides a first output signal equal to said first output signal of said first location selection means and a second output signal equal to said second output. signal of said second location selection means, said steering logic means having a second configuration in which said steering logic means provides an output signal equal to a selected one of said first and said second output signals of said first and said second location selection means.

3. A configurable logic circuit as in claim 2, wherein the number of signals in each of said first, said secondy said third and said fourth sets of output signals is L where L is a selected positive integer less than or equal to K.

4. A configurable combinational logic circuit as in claim 3, wherein L = K 1.

5. A configurable combinational logic circuit as in claim 15, wherein said first memory means comprises 2 K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed and wherein said second memory means comprises 2 K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed; n

6. A configurable combinational logic circuit substantially as hereinbefore described with reference to the accompanying drawings.

v# Published 19B8 at The Patent Office, State House, 86171 High Holborn, London WC1R 4TP. Further copies may be obtained from The Patent Office, Wee Branch, St Mary Cray, Orpington, Kent BR5 3BD. Printed by Multiplex techniques ltd, St Mary Cray, Kent. Con. 1187.