GB2199708A

GB2199708A - Digital automatic frequency control

Info

Publication number: GB2199708A
Application number: GB08626167A
Authority: GB
Inventors: Robert Jensen
Original assignee: Storno AS
Current assignee: Motorola Solutions Danmark AS
Priority date: 1986-11-01
Filing date: 1986-11-01
Publication date: 1988-07-13
Anticipated expiration: 2006-11-01
Also published as: GB8626167D0; GB2199708B

Abstract

There is provided a system for digital automatic frequency control in an FM receiver by comparing the received frequency (CL1) against a frequency reference (CL2) and outputting digital signals indicative of the difference therebetween, accumulating (2) the frequency difference signals, and periodically converting (3) the accumulated frequency difference signals (A-H) from-digital form to analog form. Up/downcounter (2) is incremented or decremented according as the divided ( DIVIDED 3640) received frequency is below or above the divided ( DIVIDED N1/N2) reference frequency. The count is periodically loaded into D/A converter (3) which provides a pulse-width modulated output (VOUT) controlling the local oscillator. Lock detection is performed by counting ( DIVIDED 16) transitions in the up/down count (U/D); counter (2) is clocked more slowly during lock, if loss or fading of input signal is detected (RSSI), the counter (2) is stopped to store the current value. <IMAGE>

Description

DIGITAL AUTOMATIC FREQUENCY CONTROL Field of Invention This invention relates to automatic frequency control (AFC). More particularly, this invention relates to digital AFC in a frequency modulated receiver.

Background of the Invention In frequency modulated (FM), mobile, two-way radio communication receivers, frequency stability becomes increasingly important as the center frequency of a receiver is increased (to around the 900 MHz spectrum, particularly), while maintaining narrow channel separation.

Analog AFC circuits are generally known and commonly used to maintain frequency stability. Typically, they utilize a tuned, low stability LC network as a frequency reference and an analog discriminator to generate a control voltage for the receiver's frequency oscillator. However, analog AFCs have their limitations. For example, when the FM signal is lost or fades, the AFC control voltage is not remembered or stored and, therefore, must be regenerated anew when the FM signal reappears.

A digital AFC, on the other hand, overcomes some of these limitations and provides further advantages. It is able to store a representation of the control voltage generated just before the loss of the received FM signal.

Thus, frequency control can be quickly reinstated when the FM signal returns. It is able to simply detect when the received frequency is out of its control range. Moreover, it may be more easily integrated to save-valuable space and current consumption.

It is, therefore, one object of the invention to provide a system for digital automatic frequency control.

Summary of the Invention According to the present invention, there is provided a system for digital automatic frequency control by comparing the received frequency against a frequency reference and outputting digital signals indicative of the difference therebetween, accumulating the frequency difference signals, and periodically converting the accumulated frequency difference signals from digital form to analog form.

Brief Description of the Drawings An exemplary system in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a 900 MHz FM receiver incorporating the present invention.

Figure 2 is a block diagram of the digital AFC according to the present invention.

Figures 3A-3D comprise a logic diagram of the digital AFC integrated circuit according to the present invention.

Figure 3A continues from the right onto Figure 3B and continues from the bottom onto Figure 3C. Figure 3C continues from the right onto Figure 3D and Figure 3B continues from the bottom onto Figure 3D.

Detailed Description of the Invention Figure 1 is a block diagram of a 900 MHz FM receiver incorporating the present invention. In operation, the AFC compares the 455 KHz intermediate frequency with a reference frequency (X0) and generates a control voltage (Vcontrol) to control the oscillator (VCX0) and synthesizer in a frequency-locked loop.

Figure 2 is a block diagram of the digital AFC according to the present invention. It includes a frequency comparator (1), an up/down counter (2), a pulse-width digital-to-analog (D/A) converter (3), and a clock generator (4).

In operation, if the divided (:3640), received intermediate frequency (CL1) is below the divided (:N1/N2) reference frequency (CL2), the up/down counter (2) increments and accumulates a count. The accumulated count is periodically loaded into the pulse-width D/A (3) and a pulse, whose width is proportional to the count, is output (Vout). Thus, a proportionately longer pulse is output (Vcontrol) to the oscillator (VCX0) which, in turn, brings up the intermediate frequency (CL1). If the divided, recieved intermediate frequency is above the divided, reference frequency, the up/down counter is decremented and a proportionately shorter pulse is output, bringing down the intermediate frequency.If the received intermediate frequency is substantially identical to the reference frequency, the up/down counter will reach a relatively quiescent value and the output (Vout) will be nearly quiescent. For inverted operation, the PHASE input alters the sense of the counter's (2) accumulations and, therefore, the output voltage (Vout).

In the frequency comparator (1), the received 455-KHz intermediate frequency (CL1) is divided (:3640) to-a nominal 125 Hz signal. Simultaneously, the reference frequency (either 8 MHz or 11.132 MHz; CL2) is also divided (N1 or N2, respectively) to the same nominal rate (125 Hz).If the received intermediate frequency (CL1) is too low, the reference divider (:N1/N2) will reach its count first, reset the comparator's flip-flop, increment the up/down counter (2), and simultaneously reset both dividers (:3640 & BR< :N1/N2). Similarly, if the received intermediate frequency (CL1) is too high, its divider (:3640) will reach its count first, set the comparators flip-flop, decrement the up/down counter (2), and simultaneously reset both dividers. When the divided, received intermediate frequency and the divided reference frequency are substantially equal, the counter will toggle about its quiescent value.

Frequency lock detection is performed by counting (:16) the number of polarity transitions in the up/down count (U/D). While the receiver is searching for the proper frequency (455 KHz), the counter (2) will be predominantly either incrementing or decrementing with pulses of like polarity. (Although modulation may cause some opposite transitions, it is, largely, balanced by the high divider ratio, i.e., :3640). The number of polarity transitions will suddenly increase as the counter toggles about its quiescent value, generating a lock detect signal (:16) indicating that the receiver is locked on frequency. Further, the lock detect signal (:16) is used to clock the counter (2) more slowly (15 Hz rather than 125 Hz), resulting in less noise and better tracking.Further, the divisors (:3640 & N1/N2) could be scaled to obtain even finer frequency resolution, if desired.

In the up/down counter (2), when the received FM signal is lost or fades, the received signal strength (RSSI) drops and stops the counter at its present count. Thus, when the FM signal reappears, the count can proceed from its present setting. Meanwhile, the output voltage (Vout) is held at its present value and the receiver is held on frequency.

Also, when the counter overflows or underflows, an OUT-OF-RANGE condition can be detected. The size of the up/down counter (2) is determined by the clock and the divider ratios (:3640 & :N1/N2). If the clock is too slow compared with the output of the frequency comparator, the output voltage (Vout) will not change fast enough. Too fast, overshoot will result. This one is eight bits (A-H).

These eight bits (A-H) are parallel-loaded into the D/A convertor (3). This count (A-H) is clocked through the output flip-flop at 2 MHz to form a pulse train whose length is proportional to the count. The output pulse train (Vout) is smoothed with an RC pad that provides the control voltage (Vcontrol) to the oscillator (VXCO). A conventional D/A convertor with resistor network and switches is not acceptable for gate-array integration.

Generally, it includes the received frequency divider (A, B & C), the reference frequency divider (D, E & F), the frequency comparator (8), the up/down counter (U & V), the D/A converter (X & Y), the lock detector (Figure 3B: 80, 57, 111, 58 & 60), the timing generator (Figure 3C), and their supporting circuitry.

Frequency stability of count accumulations is provided by flip-flops 61, 62, 64, 65, and 68 and their supporting circuitry (63A & 6) to stop the counter (U & V) every time a polarity transition occurs and to reset the flip-flop (68) to re-enable the counter (U & V) with the next clock pulse.

This slows down up/down toggling once the quiescent frequency is reached. Thus, the AFC may remain unclocked for a long time with very little frequency error and very little output noise.

In summary, there has been provided a system for digital automatic frequency control by comparing the received frequency against a frequency reference and outputting digital signals indicative of the difference therebetween, accumulating the frequency difference signals, and periodically converting the accumulated frequency difference signals from digital form to analog form.

While the preferred embodiment of the invention has been described and shown, it will be understood by those skilled in the art that other variations and modifications of this invention may be implemented.

Claims

Claims

What I claim and desire to secure by Letters Patent is: 1. A system for digital automatic frequency control characterized by: comparing the received frequency against a frequency reference and outputting digital signal(s) indicative of the difference therebetween and converting the frequency difference signal(s) from digital form to analog form.
2. A system for digital automatic frequency control characterized by: means for comparing the received frequency against a frequency reference and outputting digital signal(s) indicative of the difference therebetween and means for converting the frequency difference signal(s) from digital form to analog form.
3. A system as claimed in Claims 1 or 2 wherein the conversion is further characterized by: accumulating the frequency difference signals and periodically converting the accumulated frequency difference signals from digital form to analog form.
4. A system as claimed in Claims 1, 2 or 3 wherein the conversion is further characterized by: pulse width digital-to-analog conversion.
5. A system as claimed in Claims 1, 2, 3 or 4 wherein the conversion is further characterized by: storing the accumulated frequency difference for later recall.
6. A system as claimed in Claim 3 wherein the digital frequency comparison and accumulation is further characterized by: frequency searching at a relatively higher rate and frequency tracking at a relatively lower rate.
7. A system as claimed in Claim 6 wherein the frequency tracking is further characterized by: supressing frequency difference accumulations about the tracked frequency.