GB2199458A

GB2199458A - Toggle flip-flop circuit

Info

Publication number: GB2199458A
Application number: GB08728572A
Authority: GB
Inventors: Tadato Yamagata; Hiroshi Miyamoto; Michihiro Yamada; Shigeru Mori
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1986-12-10
Filing date: 1987-12-07
Publication date: 1988-07-06
Also published as: DE3741877A1; JPS63146612A; DE3741877C2; GB8728572D0

Description

2199458

TITLE OF THE INVENTION

Toggle Flip-Flop Circuit BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a toggle flip-flop circuit and, more particularly, it relates to an improvement of this circuit for reducing power consumption. Description of the Prior Art

Fig4 1 is a block diagram showing one example of a simplified circuit of a 1-M bit conventional dynamic RAM (Random Access Memory) having 1048576 memory cells. A summary of the basic operation of the dynamic RAM and the function of "CAS before RAS Refresh" in relation to the resent invention will be hereinafter described.

A clock generator 51 receives a RAS (Row Address Strobe) signal,-CAS (Column Address Strobe) signal and WE (Write Enable) signal from a CPU (Central Processing Unit) and generates control signals 61. In a normal writing and reading operation of the dynamic RAM, an address buffer 54 receives external address signals EXT. A 0 to A 9 on a time share basis and outputs internal address signals A 0 to A 9 on a time share basis, a row decoder 55 and a column decoder 56 decode the internal address signals A 0 to.A,,, and decoded signals are applied to the memory cell array I- 58 and 1/0 gates 57. The writing operation of an input data D IN and the reading operation of an output data D are carried out on the memory cells having addresses designated as described above. An input buffer 59 receives the input data D IN and transfers the input data 0Trr D IN to the memory cell array 58 via the 1/0 gates 57 and the sense amplifiers 63 in response to the control signals 64 from an 1/0 controller 65. The control signal 64 is generated by the 1/0 controller 65, which receives the internal address signal Aq., in response to the control signal 61. On the other hand, an output buffer 60 receives data from the memory cell array 58 via the sense amplifiers 63 and the 1/0 gates 57 and outputs the output data D OUT in response to the control signals 64.

As is well known, a refresh operation, namely, reading and rewriting operation of all memory cells, is carried cut between the above described reading and writing operation in a dynamic RAM. Referring to Fig. 1, in a refresh operation a refresh controller 52 generates a driving signal 62 for driving a refresh counter 53 in response to the control signals from the clock generator 51. The refresh counter 53 carries out the counting operation upon receipt of the driving signal 62 and applies an output signals Q 0 to Q 8 to the address buffer 54. The address buffer 54 receives the output signals Q 0 z Z c is to Q 8 from the refresh counter 53 instead of the external address signals EXT. A 0 to A 8 and applies the internal address signals A 0 to A 8 to the row decoder 55. in the memory cell array 58, the reading operation of already written data and the rewriting operation are carried out successively on the memory cells having the addresses designated by the internal address signalsA0 to A 8 Since the refresh counter 53 successively outputs the output signals, the refresh operation of all memory cells can be accomplished by the repetition of the above described operation.

The refresh operation, in which the signals for refreshing are not applied externally as the external address signals EXT.. AO to A 9 but the signals are generated by the refresh counter 53 provided in the chip as described above, is called 11CAS before RAS Refresh", which is one of the standard functions of the dynamic RAM.

Although a dynamic RAM having 11CAS before liS RefresW' function is described as an example in the foregoing, the application of the present invention is not limited to the dynamic RAM having 11CAS before RAS RefresW' function, as is pointed out by this description.

An application of the prior art of particular interest to the present application concerning a dynamic memory device having internal refresh function is seen in

U.S. Patent. No. 4,207,618 entitled "ON-CHIP REFRESH FOR DYNAMIC MEMORY", issued to L.S. White, Jr. et al. on June 10, 1980.

Fig. 2 is a block diagram of a circuit of a conventional refresh counter 53 shown in Fig. 1. refresh counter circuit shown in Fig. 2 comprises a cascade connection of nine toggle flip-flop circuits 70 to 78. In Fig. 2, a driving pulse 0 and the inverted driving pulse are signals for driving the refresh counter circuit and they are applied to a toggle flip-flop 70 of the first stage. 0 to Q 8 and VO to Q 8 are respective output signals and inverted output signals of each of the toggle flip-flop circuits 70 to 78 and, except the toggle flip-flop circuit 78, they are the input signals to the toggle flip-flop 6ircuits of the succeeding stages. Almost at the same time, the output signals Q 0 to Q8 of;each of the toggle flip- flop circuits 70 to 78 are outputted as the output signals of the refresh counter circuit.

Meanwhile, the driving pulses 4) and and the output signals Q 0 to Q 8 respectively correspond to the driving signal 62 and the output signals Q 0 to Q 8 of the refresh counter in the block diagram of Fig. 1.

Fig. 3 is a timing chart showing the changes in each of the signals for describing the operation of the refresh is Z 1 1 counter circuit of Fig. 2. In Fig. 3, the changes in the driving pulse 0 and in the output signals Q 0 to Q 3 are shown and the changes in the output signals Q 4 to Q 8 are o itted. Fig. 3 shows that the refresh counter circuit shown in Fig. 2 outputs successively increasing binary signals as outputs Q 0 to Q. in response to the driving pulses 0 and. - In a 1 M bit dynamic RAM as an example, 512 addresses can be obtained by applying 512 driving pluses to the refresh counter circuit including nine toggle flip-flop circuits as shown in Fig. 2. Therefore, refresh of all memory cells of 1 M bit can be carried out by using this counter circuit.

Fig. 4 is a schematic diagram showing a conventional representative toggle flip-flop circuit. Almost the same circuit is shown in MOS/LSI Design and Application by W.N. CARR et at. published by McGRAW-HILL BOOK COMPANY.

Referring to Fig. 4, the toggle flip-flop circuit comprises logical circuits L1 and L2 each of which including AND circuit and NOR circuit. An n channel MOS transistor 1 has its drain connected to a supply line V cc, its source connected to an output node N1 and its gate connected to a supply line VGG The n channel MOS transistor 1 is a load _transistor of the -logic Ll. An n channel MOS transistor 3 has its drain connected to the output node N1, its source connected to the ground line v ss and its gate connected to an output node N2. An n channel MOS transistor 5 has its drain connected to the output node N1, its source connected to the drain of a n channel MOS transistor 6 via a node N3 and its gate applied with a driving pulse 0. The n channel MOS transistor 6 has its source connected to the ground line v ss The n channel MOS transistor 5 and the n channel MOS transistor 6 constitute an AND circuit. An n channel MOS transistor 7 has its drain connected to the output node N1 and its source connected to the gate of the n channel MOS transistor 6 via a node N4 as well as to one electrode of the capacitor 20. The other electrode of the capacitor 20 is connected to the ground line V ss A driving pulse which does not become high level simultaneously with the driving pulse (p, is applied to the gate of the n channel MOS transistor 7. The n channel MOS transistor 7 is a transistor for transferring the voltage of an output to the node N4. The capacitor 20 is provided for temporarily holding the voltage of the output 5 while the n channel MOS transistor 7 is off. Since the capacitor 20 exists as a floating capacitance of the node N4, it may not be provided in some cases.

The circuit of the logic L2 is structured in the same manner as the circuit of logic Ll. An n channel MOS is I- transistor 2 has its drain connected to a supply line V cc, its source connected to the output node N2 and its gate connected to a supply line V GG The n channel MOS transistor 2 is a load transistor of the logic L2. An n channel MOS transistor 4 has its drain connected to the output node N2, its source connected to the ground line V ss and its gate connected to the output node N1. The n channel MOS transistor 4 and the n channel MOS transistor 3 constitute a latch circuit. An n channel MOS transistor 8 has its drain connected to the output node N2, its source connected to the drain of the n channel MOS transistor 9 via a node NS and its gate supplied with a driving pulse l). The source of the n channel MOS transistor 9 is connected to the ground line V ss The n channel MOS transistor 8 and the n channel MOS transistor 9 const.itute an AND circuit. An n channel MOS transistor has its drain connected to the output node N2, its source connected to the gate of the n channel MOS transistor 9 via a node N6 as well as to.one electrode of the capacitor 21. The other electrode of the capacitor 21 is connected to the ground line V A driving pulse is ss applied to the gate of the n channel MOS transistor 10.

The n channel MOS transistor 10 is a transistor for transferring the voltage of the output Q to the node-N6.

The capacitor 21 is provided for temporarily holding the voltage of the output Q while the n channel MOS transistor 10 is off. Since the capacitor 21 exists as a floating capacitance of the node N6, it may not be provided in some cases.

Fig. 5 is a timing chart for describing the operation of this toggle flip-flop circuit. The operation of this circuit will be hereinafter described with reference to Fig. 5. The driving of this circuit is performed by two-phase driving pulses 0 and which will not become high level simultaneously. Let us assume that a voltage of the output node N1 is at a "H" level and the voltage of the output node N2 is at a I'Ll' level at time t 0 When the driving pulse changes to the "H" level from the "L" level at tl.. the n channel MOS transistors 7 and 10 turn on, the voltage of the output is applied to the node N4 and the voltage of the output. Q is applied to the node N6.

That is, the node N4 is charged by the supply line V cc through n channel MOS transistors 1 and 7 and its voltage becomes "H" level while the node N6 is discharged to the ground line V ss through the n channel MOS transistor 4 and its voltage becomes 'W' level. Since the n channel MOS transistors 5 and 8 have been turned off at this time, no influence will be exerted on outputs Q and This state continues until time t 3 when the driving pulse becomes "L" level from the "H" level. The n channel MOS 8 transistors 5, 7, 8 and 10 are off from time t 3 to time t 41 and the voltages of the outputs and Q before the driving pulse $ becomes the IILII level are charged by the capacitors 20 and 21, respectively, on the nodes N4 and N6. Namely, the node N4 maintains a voltage of IIHII level while the node N6 maintains the voltage of IILII level. The voltages of the ou tputs Q and 5 do not change so that the output Q remains at the I'Ll' level while the output remains at the "H" level. Then, when the driving pulse changes from the 'W' level to the "H" level at time t 5' the n channel MOS transistors 5 and 8 turn on. Since the node N4 holds the voltage of "H" level, the n channel MOS transistors 5 and -6 both turn on. Consequently the voltage of the node.Nl which has been at the "H" level decreases to the "L" level. At the same time, since the node N6 holds the voltage of "L" level, the n channel MOS transistor 8 turns on while the n channel MOS transistor 9 remains off. Consequently, the voltage of the node N2 which has been at the 'W' level increases to the voltage of "H" level through the n channel MOS transistor 12. As a result, the outputs Q and 5 are reversed, so that the output-Q becomes "H" level from the "L" level and, at the same time. the output Q becomes "L" level from the "H" level. At time t 7 when the driving pulse 0 becomes the I'LI1.1evel from the "H" level, only the n channel MOS transistors 5 and 8 turn off and outputs Q and do not change. Therefore, the output Q remains at the "H" level while the output remains at the 11L11. After the driving pulse becomes the "H" level from the I'Ll' level again at time tl. the same operation as described above for time tl and thereafter is carried out, except that the logical circuits of L1 and L2 operate in place of each other. Hereafter the same operation is repeated and the voltages of the outputs Q and are reversed every time when the driving pulse 0 changes to the "H" level from the I'Ll' level.

Meanwhile, in a conventional toggle flip-flop circuit, since the n channel MOS transistors 1 and 2 which are load transistors have their gates connected to the sdpply line V GG, a through current constantly flows from the supply line V cc to the ground line V ss in the toggle flip-flop circuit, causing large power consumption. In other words, a current is constantly flown in order to maintain the levelsof the outputs Q and 5 stable, increasing the power consumption. SUMMARY OF THE INVENTION

Therefore, a main object of the present invention is to provide a toggle flip-flop circuit having a reduced power consumption.

Briefly stated, the present invention comprises first power supply connection means connected between the power supply and a first output for bringing the first output to the voltage of the power supply level in response to the voltage of a second output, first voltage holding means connected between the first output and the ground for temporarily holding and outputting the voltage from-the first output in response to a signal from a first input for receiving input signals of predetermined two levels, first voltage discharging means connected between the first output and the ground for bringing the first output to the voltage of the ground level in response to the signals from a second input for receiving input signals of predetermined two levels opposing to the signals inputted to the first input and from the first voltage holding means, first ground connection means connected between the first output and the ground for bringing the first output to the voltage of the ground level in response to the voltage of the second output, second power supply connection means connected between the power supply and the second output for bringing the second output to the voltage of the supply level in response to the voltage from the-first output, second voltage holding means connected between the second output and the ground for temporarily holding and outputting the voltage from the second output in response to the signal from the first input, second voltage discharging means connected between the second output and the ground for bringing the second output to the voltage of the ground level in response to the signals from the second input and from the second voltage holding means, and second ground connection means connected between the second output and the ground for bringing the second output to the voltage of the ground level in response to the voltage of the first output.

According to the present invention, only one of the first and second supply connection means operates at an arbitrary time to bring the iirst or the second output to the level of the supply voltage. Let us assume that the first supply connection means operates to bring the voltage level of the first output to the voltage level of the power supply. The first voltage holding means temporarily holds and applies the voltage from the first output to the first voltage discharging means in response to a signal from the first input. The first voltage discharging means brings the first output to the ground voltage level in response to the signals from the second 12 - C:

1 20 input and from the first voltage holding means. As soon as the voltage level of the first output changes from the power supply voltage level to the ground voltage level, the second power supply connection means brings the second output to the power supply voltage level in response to the voltage of the first output. On this occasion, the first ground connection means keeps the first output to the ground voltage level in response to the second output voltage, and simultaneously, the first supply connection means cuts the first output from the power supply in response to the voltage of the second output on this time. Therefore, the first output is brought to the ground voltage level and becomes stable. The second power supply connection means maintains the voltage of the second output by bringing the second output to the supply voltage level in response to the stable first output voltage. The second ground connection means cuts the second output from the ground in response to this stable first output voltage. In the above described operation, no constant through current flows from the power supply to the ground in this circuit. The reason for this is that the output which is brought to the ground voltage level, that is, the first output, is cut from the power supply and the output brought to the power supply voltage level, that is the second output, is cut from the ground.

in the foregoing, the operation of this circuit is described in which the voltage level of the first output changes from the power supply voltage level to the ground voltage level and the voltage level of the second output changes from the ground voltage level to the power supply voltage level. The operation in which the voltage levels of the both outputs change reversely can be similarly described, so that the description is omitted.

According to the present invention, a constant through current flowing from the power supply to the ground is eliminated, so that unnecessary power consumption can be reduced.

In a preferred embodiment of the present invention, the first and second connection means comprise first and second switching devices, respectively. By employing the first and second switching devices as the first and second connecting means, the circuit can be implemented with a simple structure.

These objects and other objects, features, aspects and advantages of the pre. sent invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS is Fig. 1 is a block diagram showing an example of a circuit of a conventional dynamic RAM; Fig. 2 is a block diagram of a conventional refresh counter circuit shown in Fig. 1; Fig. 3 is a timing chart showing changes in each signal for describing the operation of the conventional refresh counter shown in Fig. 2; Fig. 4 is a schematic diagram showing one example of a conventional toggle flip-flop circuit; Fig. 5 is a timing chart for describing the operation of toggle flip-flop circuits of Fig. 4 and Fig. 6 which will be described in the following; and Fig. 6 is a schematic diagram showing one example of a toggle flip-flop circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS one embodiment of the present invention will be hereinafter described with reference to the figures. Meanwhile, in the description of the- embodiment, the portions overlapping with the description of the prior art will be omitted appropriately.

Fig. 6 is a schematic diagram showing the toggle flip-flop circuit of one embodiment according to the present invention.

- is - The structure of this embodiment differs from the structure of the conventional toggle flip-flop circuit shown in Fig. 4 in the following points. Namely, a p channel MOS transistor 11 is employed instead of the n channel MOS transistor 1 as a load transistor of the logi Ll and a p channel MOS transistor 12 is employed instead of the n channel MOS transistor 2 as a load transistor of the logic L2. The p channel MOS transistor 11 has its source connected to the supply line V cc, its drain connected to the output node N1 and its gate connected to the output node N2. The p channel MOS transistor 12 has its source connected to the supply line VCC, its source connected to the output node N2 and its gate connected to the output node Nl.

Thus, a toggle flip-flop circuit made as a CMOS structure is driven by two-phase driving pluses q) and which do not become high level simultaneously as in the case of a conventional device and, the operation of this circuit is almost the same as the conventional one. The driving pulses 0 and are externally applied through the inputs and P.

The operation of the toggle flip-flop circuit will be described with reference to Fig. 5.

Let us assume that the voltage of the node NI is at the IIHI' level and the voltage of the node N2 is at the "Ll' - 16 c c 1 io level. When the driving pulse 4) changes from the 'W' level to the "H" level at time tl, n channel MOS transistors 7 and 10 turn on, the voltage of the output Q is applied to the node N4 and the voltage of the output Q is applied to the node N6. Namely, the node N4 is charged by the supply line V cc through the p channel MOS transistor 11 and n channel MOS transistor 7 and the voltage becomes the "H" level and, on the other hand, the node N6 is discharged to the ground line V ss through the n channel MOS transistor 4 and the voltage becomes the 'W' level. At this time, since the n channel MOS transistors 5 and 8 are off, outputs Q and do not change. This state continues until the time t 3 when the driving pulse becomes the 'W' level from the "H" level. The n channel MOS transistors 5, 7, 8 and 10 are off from time t 3 to t 4 and the voltages of the outputs Q and before the driving pulse becomes the 'W' level are charged by the capacitors 20 and 21 respectively, on the nodes N4 and N6. That is, the node N4 holds the voltage of the "H" level and the node N6 holds the voltage of the 'W' level. The voltages of the outputs Q and do not change, namely, the output Q remains at the "L" level while the output remains at the "H" level. When the driving pulse 4) changes from the "W level to the "I-I" level at time t., n channel MOS transistors 5 and 8 turn on. since the node N4 holds the voltage of the "H" level, the n channel MOS transistors 5 and 6 both turn on. Therefore the voltage on the node N1 which has been at the "H" level decreases to the "L" level. Simultaneously, since the node N6 holds the voltage of the "L" level, the n channel MOS transistor 8 turns on but the n channel MOS transistor 9 remains off. Therefore, as the voltage of the output node N1 decreases, the p channel MOS transistor 12 turns on and the voltage of the node N2 which has been at the "L" level increases to the "H" level. Consequently, outputs Q and 5 are inverted, that is, the output Q changes from the 'W' level to the "H" level and at the same time the output changes from the "H" level to the "L" level. At time t 7 when the driving pulse 0 becomes "L" level from the " W' level, only the n channel MOS transistors 5 and 8 turn off and the outputs Q and 5 do not change. Therefore, the output remains at the "H" level while the output remains at the "L" level. The operation after the driving pulse again changes from the 'W' level to the "H" level at time t 8 is carried out similarly to the operation after the time t 1 as described above, except that the logical circuits L1 and L2 operate in place of each other. Thereafter, the same operation is repeated and the outputs Q and are reversed every time the driving pulse 0 changes from the 'W' level to the "H" level.

p As described above, this circuit is a CMOS toggle flip-flop circuit in which p channel MOS transistors 11 and 12 are employed as load transistors. Therefore, different from a conventional device, no current flows constantly from the supply line V cc to the ground line VSS. A current flows from the supply line VCC to the ground line V ss- only at a moment when the voltage level of the two outputs Q and 5 are reversed, whereby the power consumption can be greatly reduced compared with a conventional device. In addition, since the output nodes N1 and N2 are latched by CMOS flip-flops 3, 4, 11-and 12, a stable voltage level of the outputs Q and 5 are obtained.

As described above, according to the present invention, one of the first power supply connection means Ll connected between the power supply V cc and a first output 5 and the'second power.supply connection means 12 connected between the power supply V cc and the second output Q brings the-connected output.to the voltage level of the power supply V cc in response to the voltage of the other output, and the other of the two means 11, 12 cuts the connected output from the power supply. At the same time, one grounding means of the first ground connection means 3 connected between the first output and theground V ss and the second ground connection means connected between the second output Q and the ground V ss, which is connected to the output brought to the voltage level of the power supply V cc cuts the output thereof from the ground VSS, and the other grounding means connects the output thereof to the ground V ss. Therefore, a toggle flip-flop circuit is provided in which no through current flows constantly between the power supply V cc and the ground V ss and in which the voltage of the outputs are stable.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

WHAT IS CLAIMED IS:

is - 1. A toggle flip-flop circuit having one of two output states in response to an input signal, comprising a first input (P) and a second input (P) for receiving input signals of predetermined two levels opposing to each other, a first output (Q) and a second output (Q) for simultaneously outputting output signals opposing to each other, first power supply connection means (11) connected between the power supply (V cc) and said first output () for bringing said first output (Q) to the voltage of said power supply (V cc).level in response to the voltage of said second output (Q), first voltage holding means (7, 20) connected between said first output (Q) and said ground (V ss) for temporarily holding and outputting the voltage from said first output (Q) in response to a signal from said first input (P), first voltage discharging means (5, 6) connected.

between said first output (5) and said ground (V) for ss bringing said first output (Q) to the voltage of said ground (V ss)-level in response to thd signals from said second input (P) and from said first voltage holding means (7, 20), first ground connection means (3) connected between said first output and said ground (V) for bringing ss said first output to the voltage of said ground (V SS) level in response to the voltage of said second output (Q) 1 second power supply connection means (12) connected between said power supply (V cc) and said second output (Q) for bringing said second output (Q) to the voltage of said power supply (V cc) level in response to the voltage of said first output (), - second voltage holding means (10, 21) connected between said second output (Q) and said ground (V ss) for temporarily holding and outputting the voltage from said second output (Q) in response to the signal from said first input second voltage discharging means (8, 9) connected between said second output (Q) and said ground (V ss) for bringing said second output (Q) to the voltage of said ground (V ss) level in response to the signals from said second input (P) and from said second voltage holding means (10, 21), and f i second ground connection means (4) connected between said second output (Q) and said ground (V ss) for bringing said second output (Q) to the voltage of said ground (VSS) level in response to the voltage of said first output ().

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2. A toggle flip-flop circuit according to claim 1, wherein said first power supply connection means comprises a first switching device (11), and said second power supply connection means comprises a second switching device (12).
3. A toggle flip-flop circuit according to claim 1, wherein said first voltage holding means comprises a first serial connection of the third switching device (7) and a first capacitance (20) connected between said fir st output 1 () and the ground (V SS), d f irst said third switching device (7) and sai capacitance (20) are connectpd. together at a first node (N4), said third switching device (7) brings said first node (N4) to the voltage of said first output () level in response to a signal from said first input (P), said first capacitance (20) is charged by the voltage of said first node (N4), - 23 said second voltage holding means comprises a second serial connection of the fourth switching device (10) and a second capacitance (21) connected between said second output (Q) and said ground (V SS), said fourth switching device (10) and said second capacitance (21) are connected together at a second node (N6).. said fourth switching device (10) brings said second node (N6) to the voltage of said second output (Q) level in response to a signal from said first input (P), and said second capacitance (21) is charged by the voltage at said second node (N6).
4. A toggle flip-flop circuit according to claim 1, wherein said first voltage discharging means comprises a third serial connection of a fifth switching device (5) and a sixth switching device (6) connected between said first output () and said ground (V SS), said fifth switching device (5) is conducted in response to a signal from said second input (P), said sixth switching device (6) is conducted in response to a signal from said first node (N4), said second voltage discharging means comprises a fourth serial connection of a seventh switching device (8) - 24 1 1 and a eighth switching device (9) connected between said second output (Q) and said ground (V ss said seventh switching device (8).is conducted in response to a signal from said second input (P), and said eighth switching device (9) is conducted in response to a signal from said second node (N6).
5. A toggle flip-flop circuit according to claim 1, wherein said first ground connection means comprises a ninth switching device (3), and said second ground connection means comprises a tenth switching device (4).
6. A toggle flip-flop circuit according to claim 1, wherein a plurality o f said toggle flip-flop circuit constitutes a refresh counter of a dynamic RAM having the function of refreshing.
7. A toggle flip-flop-circuit-according to claim 1, wherein each of said first to said tenth switching device comprises a field effect device.
8.' A toggle flip-flop circuit according to claim 7, wherein the field effect devices of said first switching device (11) and said second switching device (12) are of a certain conductivity type, and the field effect devices of other switching devices are of the opposite conductivity type.
9. A toggle flip-flop circuit according to claim 8, wherein said certain conductivity type is P type-and said opposite conductivity type is N type.
10. A toggle flip-flop circuit substantially as herein before described with reference to Figure 6.
11. A memory device comprising a flip-flop circuit according to any preceding claim.
12. A memory device substantially as hereinbefore described with reference to Figures 1 to 3 as modified by Figure 6.

Published 1988 at The Patent Ofnce. State I-louse. 66"71 High Holborn, London WCIR 4TP Further copies may be obtained from The Patent Office. Sales Branch, St Mary Cray, Orpington. Kent BR5 3RD Printed by Multlplex techniques ltd. St Mary Cray, Kent Con. 1/87.