GB2196517A - Signal labelling - Google Patents

Abstract

A digital signal handling device comprises a converter for converting a balanced pseudo ternary digital code (e.g. HDB3) into a two-level binary code at twice the bit rate of the pseudo-ternary code, the converter including means for labelling the input pseudo-ternary code by periodically inverting the bit pair (e.g. 01) of the 2-level binary code which represents logical zero, (e.g. to 10) and, when no zeroes occur, periodically inverting the bit pairs (e.g. 11,00) representing the marks of the pseudo-ternary input signal, (e.g. to 00, 11). The ternary signals are labelled and converted to double rate binary for processing in crosspoint switch 10. The scheme also allows the switch to be transparent to errors on the ternary channels 11, 12. <IMAGE>

Description

SPECIFICATION Signal labelling The present invention concerns the labelling of digital data signals so that one can be distinguished from another without affecting the data content of the signal.

A particular application for such a labelling technique is in digital crosspoint switches.

These are commonly found in telephone exchanges where it is important that the correct operation of such switches can be verified.

The present invention has for an object to provide a system incorporating such a labelling technique to a balanced digital data signal.

Accordingly from one aspect the present invention consists in a converter for converting a balanced pseudo-ternary digital code into a 2-level binary code at twice the bit rate of the pseudo-ternary code, the converter including means for labelling the input pseudo-ternary code by periodically inverting the bit pair of the 2-level binary code which represents logical zero, and when no zeros occur, periodically inverting the bit pairs representing the marks of the pseudo-ternary input signal.

From another aspect, the invention consists in a digital crosspoint switch capable of receiving a plurality of 2-level input signals each derived from a balanced pseudo-ternary digital signal, a plurality of converters for converting each of the input pseudo-ternary signals into the 2-level signals, a plurality of decoders for decoding the 2-level signals from the switch back into pseudo-ternary signals, and a controller circuit for labelling converted signals by periodically inverting pairs of digits, and for verifying that each labelled signal is decoded at the correct decoder.

In order that the present inventionmay be more readily understood, an embodment thereof will now be described by way of example and with reference to the accompanying drawings, in whichthe sole figure is a circuit diagram of a crosspoint switch according to the present invention.

The background to the present invention is as follows. A conventional binary signal carrying data, for example a PCM signal, is not d.c.

balanced. This is because the two binary values corresponding to "1" and "0" respectively do not necessarily occur an equal number of times. Such asignal may thus have a direct current component or at least a component having a relatively low frequency compared with the digit rate and this places a restriction on the type of communication path over which it can be transmitted without undue distortion.

A coding system which avoids this disadvantage results from the conversion of the binary level signal into a ternary signal which has digit values of "- 1" and "+1" alternatively representing logic "1" and "0" for logical zero. However, ternary signals of this kind, though balanced, provide additional problems in that they are not suited to processing in normal 2-state logic devices. A coding system meeting this additional problem is described in the specification of British Patent No.

1,489,178. In the system described in this Patent Specification the transmitted signal is of binary form and carries the data of a balanced ternary input signal having digit values "--1", "0" and "+ 1" at twice the digit rate of the input signal, each digit of the input signal having the value "0" represented in the transmitted signal by a pair of digits having the values "01" or "10" and the digits of the input signal having the other two ternary values being represented by pairs of digits having the values "00" and "11" respectively.

Referring now to the drawing, this shows a digital crosspoint switch 10. The switch 10 is intended to switch a plurality of ternary signals on lines 11 to a plurality of output lines 12. In this embodiment the input signals in lines 11 and the o0utput signals on lines 12 are coded in HDB3 format. This is a pseudoternary signal which follows the following rules: (1) The HDB3 signal is pseudo-ternary; the three states are denoted B+, B-, and 0.

(2) Spaces in the binary signal are coded as spaces in the HDB3 signal. For strings of four spaces, however, special rules apply [see (4) below].

(3) Marks in the binary signal are coded alternately as B+ and B- in the HDB3 signal (alternate mark inversion). Violations of the rule of alternate mark inversion are introduced when coding strings of four spaces [see (4) below].

(4) Strings of four spaces in the binary signal are coded according to the following rules: (a) The first space of a string is coded as a space if the preceding mark of the HDB3 signal has a polarity opposite to the polarity of the preceding violation and is not a violation by itself; it is coded as a mark, i.e. not a violation (i.e. B+ or B-), if the preceding mark of the HDB3 signal has the same polarity as that of the preceding violation or is by itself a violation.

This rule ensures that successive violations are of alternate polarity so that no d.c. component is introduced.

(b) The second and third spaces of a string are always coded as spaces.

(c) The last space of a string of four is always coded as a mark, the polarity of which is such that it violates the rule of alternate mark inversion. Such violations are denoted V+ or V- according to their polarity.

The HDB3 signals on lines 11 are converted in converters 13 to a binary level, twice rate code. These converters eventually operate in accordance with the coding system described in Patent No. 1,489,178. The coded, 2-level signal will be referred to for the sake of this description as CB3.

The crosspoint switch 10 functions to take any one of the signals on input lines 11 and switch it to a selected one of the output lines 12. The 2-level signals from switch 10 are converted back to the HDB3 format by decoders 14.

A switch controller 1 5 controls the switching operation and is also connected to a circuit 16 which acts both to label the signals at the input ports to switch 10 and to detect that the labelled signals emerge from the correct ones of the decoder 14.

As mentioned the basis of CB3 is the correspondence HDB3 CB3 +1 11 0 -1 00 In accordance with the invention labelling of a particular HDB3 signal being applied to a converter 13 is done by periodically inverting the 01 to 10, and ensuring that the decoders which convert the CB3 back to HDB3 recognise both 01 and 10 as HDB3 logical zero.

When zeros do not occur, such as when an Alarm Indication Signal (AIS) occurs, then HDB3 marks are periodically inverted such that 11 becomes 00 and vice-versa. Once again the decoders 14 will recognise these both as valid HDB3 marks.

In order to avoid the corruption of HDB3 violation marks by this technique as in this case the polarity of the HDB3 mark is significant, only the second one of a pair of marks in adjacent timeslots is inverted. Such a mark will never be a "violation" in HDB3 because of the HDB3 coding rules.

If d.c. balance has to be preserved, though this is unlikely to be a requirement in a switch, then the above inversion can be applied to pairs so that successive pairs of paired marks can be inverted in opposite senses, i.e. +1, -1, +1, -1, becomes: 11, 11, 00, 00 so that in the second pair of marks it is the first mark which is inverted.

The technique allows encoded HDB3 traffic which has been corrupted, to have the corruptions pass completely through the switch, at least for alarge proportion of code sequences, and errored signals can therefore be seen as such by the target receiving equipment. Conventional HDB3 and related interfaces lose error information when decoding occurs, because decoding to binary leaves no evidence of the error; only if the decoder signals the error through an auxiliary data path can the knowledge that errors are occurring at the HDB3 level be passed on. The described technique is therefore superior to the use of conventional interfaces at positions 13 and 14.

The labelling is imposed periodically by the switch controller, as part of its self-monitoring role, during scanning of each pair of ports in turn (input, and intended output, or outputs).

Continuous labelling of zeros would leave the decoder unable to resolve the ambiguity between 180 and 360 degree points in clock intervals, as 10101010 and 01010101 are indistinguishable except by the start of the sequence, and interruption could destroy any memory of the correct sequence, leading to faulty decoding of isolated marks which may occur.

Labelling of sequences of marks is also to be done periodically, not continuously, to prevent a reduction in average clock content in the signal, since +1, -1, +1, -1, has a larger clock content than + 1, + 1, - 1, - 1, by virtue of having more transitions. Clock content is important in allowing the CB3 to HDB3 convertor 14 at the switch output to operate at high data rates without inducing errors.

The preceding description has concentrated on the HDB3 code. However, the invention is applicable to other similar codes which are in use internationally.

Claims (2)

1. A digital signal handling device comprising a converter for conveting a balanced pseudo ternary digital code into a two-level binary code at twice the bit rate of the pseudo-ternary code, the converter including means for labelling the input pseudo-ternary code by periodically inverting the bit pair of the 2-level binary code which represents logical zero, and when no zeroes occur, periodically inverting the bit pairs representing the marks of the pseudo-ternary input signal.

2. A digital signalling handling device comprising a plurality of converters each capable of converting a balanced pseudo-ternary input signal into a 2-level signal, a digital crosspoint switch for receiving and distributing the converted 2-level signals from siad converters, a plurality of decoders connected to said cross-point switch each for receiving an individual one of said distributed 2-level signals, and a controller circuit for labelling signals converted by said converters by periodically inverting pairs of digits in the converted signals, and for verifying that each labelled signal is decoded at the correct decoder.