GB2196199A

GB2196199A - Associative memory cells

Info

Publication number: GB2196199A
Application number: GB08624546A
Authority: GB
Inventors: Richard John Edward Aras
Original assignee: Individual
Current assignee: Individual
Priority date: 1986-10-14
Filing date: 1986-10-14
Publication date: 1988-04-20
Also published as: GB2223373B; GB8908171D0; GB8624546D0; WO1988002919A1; GB2223373A; AU8026887A

Abstract

A memory cell for use in an associative memory, also called a content addressable memory (CAM), which comprises only six active components. The cell contains two internal nodes and four interconnecting nodes. The interconnecting nodes are required for power supply and interconnection to the memory bus system. The memory cell consists of a bistable circuit using two inverters formed from a series connected pair of complementary transistors and has only four connections, a power supply connection to one transistor in each inverter, a multipurpose connection to supply power and signals to the other transistor in each inverter, and two data lines each connected through a voltage follower to the output of one of the transistor pairs. The voltage follower may be a diode, diode connected transistor or transistor. The memory cells can be connected in arrays to form content addressable memories. The primitive (CAM) operations are performed by appropriately addressing the four interconnecting nodes.

Description

SPECIFICATION Associative memory cells This invention is related to associative memories, also known as content addressable memories (CAM), for use in data processing systems and memory cells for use therein.

Many applications for content addressable memories have been proposed but prohibitive manufacturing costs have precluded their widespread use. CAM memory systems have been proposed which use either dynamic or static memory cells. These prior CAM designs have been large and complex.

CAM designs have been proposed using dynamic memory cells in which each cell has comprised four or more transistors, see GB-A1498016, US-A-4377855 and US-A4062001. Such designs involve a higher degree of complexity than the single transistor cells used in dynamic random access memory (DRAM) cells used in current computing systems.

Static CAM designs have been proposed using six or more transistors with at least five interconnecting nodes including power supplies. CAM cells using between six and twelve MOS transistors are described in GB-A 1457423, EP-A-0075711 and US-A4296475. Bipolar implementations are even greater numbers of transistors such as those described in GB-A-1335890. These arrangments compare unfavourably with the static random access memory cell (SRAM) which has six transistors and six interconnecting nodes. CAM designs based on the six transistor SRAM cell have been proposed in JP-A128092/83 and EP-A-0096556.

Alternative designs which are non-volatile have been proposed in GB-A-1494833, which is slow in operation, and US-A-36 33 182 and US-A-4532606, which require a relatively large number of interconnections between the memory cells.

The present invention provides a content addressable memory in which each memory cell comprises only six active components.

The cell contains two internal nodes and four interconnecting nodes. The interconnecting nodes are required for power supply and interconnection to the memory bus system.

The memory cell according to the invention consists of a bistable circuit using two inverters formed from a series connected pair of complementary transistors, characterised in that the cell has four connections, a power supply connection to one transistor in each inverter, a multi-purpose connection to supply power and signals to the other transistor in each inverter, and two data lines each connected through a voltage follower to the output of one of the transistor pairs.

There are also provided a content addressable memory using arrays of such memory cells and a method for their use.

The memory cells may be fabricated by laying down appropriately doped semiconducting, conducting and insulating layer patterns of an appropriate substrate such as silicon or gallium arsenide.

The invention will now be described with reference to the accompanying drawings in which: Figure 1 shows schematically a single CAM memory cell formed from a pair of crosscoupled inverters, Figure 2 shows the transistor arrangement for forming the inverter elements used in Fig.

1, Figure 3 shows an arrangement of CAM cells in an array with common power supply, multipurpose and data lines, Figure 4 shows alternative arrangements for the voltage follower in the memory cells, and Figure 5 shows an arrangement allowing conventional reading and writing to the cells.

A cell according to the invention, see Fig. 1, consists of two inverters, 1 and 2, whose outputs are cross-coupled to form a bistable circuit. This circuit is the basic storage element and stored data is represented by its state. The output state of each inverter at each node 9 and 10 is can be sensed by the data lines 3 and 4 to which they are connected through a voltage followers, diodes 5 and 6 respectively. Two supply lines 7 and 8 provide the necessary electrical energy to the inverters 1 and 2. The supply line 8 is a multipurpose line and also acts as a signal line.

The data lines 3 and 4 carry information according to the following table: Logic Value line 3 line 4 0 H L 1 L H X L L P H H Where H and L represent the high and low states respectively, X is the 'don't care' symbol used for the matching, writing and keep modes and P is used for pre-charging of the data lines prior to a READ instruction.

Each inverter is conventional CMOS inverter formed in well known manner from a complementary pair of MOS transistors 20 and 21, see Fig. 2. As illustrated the transistor 20 is a P-channel MOSFET and 21 an N-channel MOS FET. The drain 22, of the transistor 20 is connected to a positive supply and the source 23, of transistor 21 is connected to a negative supply. The input 24 to the transistor pair is connected to the gates of the transistors 20 and 21. The output 25 is obtained from the junction of the source of transistor 20 and the drain of transistor 21.

In operation, see Fig. 1, a logic '1' is stored when the node 9, at the junction of the input of the inverter 1 and the output of the inverter 2, is at the same potential as the supply line 7 and the node 10 at the same potential as the supply line 8. The transistor 20, see Fig. 2, in the inverter 1 and the transistor 21 in the inverter 2 will be conducting while the complementary transistors in each inverter will be non-conducting. Similarly a logic '0' is stored when the nodes 9 and 10 are in the reverse states, at the potentials of lines 8 and 7 respectively.

As is well known with CMOS memory cells, the data is retained in the cell over a wide range of supply voltages between the supply line 7 and the multipurpose line 8. It is pos sible for the multipurpose line 8 to 'float' for a short time or to be driven to a range of vol tages while the bistable unit retains the cor rect relationship between its input and output voltages and maintains its logic state.

A very small current, a few nanoamperes, is required to maintain data in each memory cell.

The capacitance of the multipurpose line 8 and its associated connections ensures that while the line floats its drift away from its initial voltage is relatively slow.

Associative memory cells have four primitive operations: KEEP, MATCH, WRITE and READ.

In the 'KEEP' mode the data lines 3 and 4 are in the 'X' or 'don't care' state, and the multi purpose line 8 is held low so as to ensure the full power supply potential between lines 7 and 8 is placed across the bistable unit.

During a MATCH operation the potential on either of the data lines 3 or 4 in the memory cell is raised to that of the supply line 7 representing a '1' or '0' respectively. Simulta neously the multipurpose line 8 is allowed to float from its previous low potential. If, for example, the data line 3 goes high while the node 9 is low, then a current will flow through the diode 5 and the potential on the multipurpose line 8 will rise towards that of the supply line 7. This rise in the potential on the multipurpose line 8 can be detected by peripheral circuits, not shown, to indicate the failure of a MATCH. If the cell is in its oppo site state with the node 9 high, then no cur rent will flow through the diode 5 and the multipurpose line 8 will remain at a low poten tial. The appropriate peripheral circuit will de note a MATCH.

When a MATCH operation is carried out with data line 4 to detect whether it is in the '0' state an equivalent set of voltage changes will take place according to whether the diode 6 is caused to conduct.

If neither of the data lines 3 or 4 is set high during a MATCH cycle, representing the 'X' state, then no current can flow into the multi purpose line 8 from either of the nodes 9 or 10. This facilitates a 'wild-card' or 'match-any thing' function.

A word is constituted from a series of memory cells which all share a common multi purpose line 8. If any or all of the cells have a logic state which causes the potential of the common multipurpose line to rise then a MATCH failure is indicated by the peripheral circuits associated with that line.

The high voltage level on the data lines 3 and 4 is arranged to be slightly lower than that of the supply line 7. This ensures that there will always be a sufficient voltage differential between the lines 7 and 8 for data retention by the memory cell. A low voltage on the lines 3 and 4 appears as a voltage close to earth potential and always equal to or less than the potential on the multipurpose line 8.

A WRITE operation is achieved by setting the data lines 3 and 4 to the appropriate voltage levels while the multipurpose line 8 is held low and not allowed to float. This ensures that the cell is forced into the desired logic state. When the cells are in an array the multipurpose line 8 is allowed to float for those cells which are not to be written to; this is the same situation as when in the MATCH mode. The columns of cells which are not to be written to have their data lines set at the 'X' value and their internal logic state is unaffected.

A READ operation from a memory cell involves precharging the data lines so that the lines 3 and 4 in each cell are set approximately between earth and the potential of the supply line 7 while the multipurpose line 8 floats. The multipurpose lines for the cells associated with a particular word are subsequently reduced in potential and one data line 3 or 4 in every cell also has its potential reduced through the conduction of one of the diodes.

In use as an associative memory a large number of memory cells, such as those described with respect to Fig. 1, are connected together in a two dimensional array as shown in Fig. 3.

Memory cells M are identified by their coordinates in the array as Mx,y. Data lines A, B and multipurpose lines D are similarly identified as Ax, Bx and Dy.

As shown, the data lines from each memory cell M x,y in the vertical rows are connected together to form pairs of data lines Al to Ax and B1 to Bx. The multipurpose lines from each memory M x,y in the horizontal rows are connected together to form common multipurpose lines D1 to Dx. All the supply lines from the memory cells are connected to a common supply line 32.

The data lines Al to A4 etc and B1 to B4 etc are used to carry information concerning the states of the memory cells according to the protocol described with respect to data lines 3 and 4 in Fig. 1. The common multipurpose lines D1 to D4 etc are used to write data into the memory cells and to read data from the cells such as a word-match signal from the word. Each data line Dy is connected through an interface such as a transistor 30 and an inverter 31, see Fig. 3, to the rows of cells M. The grouping of the memory cells Mx,y into words is achieved by a wired 'OR' function. All the cells in the array have a common power line 32 which supplies the most positive voltage to the cells Mx,y.

In the 'keep' mode the data lines Ax and Bx are at 'X' and the multipurpose lines Dy are held low to maintain the full power supply potential between D and C across each of the memory cells M x,y. To achieve this state the transistor 30 maintained in a fully conducting state by applying a suitable control potential to its gate 32.

While the memory cell has been shown for purposes of illustration with diodes 5 and 6 as voltage followers, these diodes may be replaced with other semi-conductor devices according to the fabrication system used for a memory. In Fig. 4 a series of alternative ar rangements are shown. In each arrangement the numbers shown on the connections correspond with the numbers shown with respect to the memory cell shown in Fig. 1.

In the first alternative a transistor connected as a diode equivalent circuit is shown, see Fig. 4a. It is also possible to use Schottky diodes.

The action of the diodes is essentially that of a voltage follower in write and match modes and, if the read function is not required in the memory, then MOS or bipolar transistors can be used instead of the diodes such as those shown in Figs. 4b and 4c. In this configuration the transistors operate as voltage followers and draw their operating current from the supply line 7 rather than the data lines 3 and 4. This arrangement reduces the current loading on the data lines.

A fourth alternative, see Fig. 4d, shows a MOSFET acting as a voltage follower which draws its current from one of the nodes 9 or 10. When a match fails and current is passed by the transistor the internal node it is connected to will be at a high voltage level. Such a circuit may have topological advantages when fabricated according to certain process technologies.

Some of the alternative embodiments shown in Figs. 4a to 4d cannot be read onto a databus by the circuits described. However it is possible to read data from arrays of cells incorporating these embodiments in a bit-serial word-parallel manner on the multipurpose lines.

A further control signal per word may be added to the computer associative memory array that controls two additional pass transistors as shown in Fig. 5. This arrangement allows both reading and writing operations in the same manner as 6T RAM cells. Setting the line to a high level voltage switches on the pass transistors. Data can then pass from the internal nodes on to the databus for reading or into the cells for writing.

In the embodiment shown in Fig. 5 two additional pass transistors, 40 and 41, connected between the nodes 9 and 10 and the data lines 3 and 4. A common READ line 42 is connected to the gates of the transistors 40 and 41. This arrangement allows both reading and writing operations in the same manner as 6T RAM cells. Setting the line to a high level voltage switches on the pass transistors. Data can then pass from the internal nodes on to the databus for reading or into the cells for writing.

Claims

1. A memory cell for use in a content addressable memory consisting of a bistable circuit using two inverters formed from a series connected pair of complementary transistors, characterised in that the cell has four connections, a power supply connection to one transistor in each inverter, a multipurpose connection to supply power and signals to the other transistor in each inverter, and two data lines each connected through a voltage follower to the output of one of the transistor pairs.

2. A memory cell according to Claim 1, characterised in that the voltage follower is a diode.

3. A memory cell according to Claim 1, characterised in that the voltage follower is a transistor connected as a diode equivalent circuit.

4. A memory cell according to Claim 1, characterised in that the voltage follower is a Schottky diode.

5. A memory cell according to Claim 1, characterised in that the voltage follower is a bipolar or MOS transistor connected to draw its operating current from the power supply connection.

6. A memory cell according to Claim 1, characterised in that the voltage follower is a MOSFET connected to draw its operating current from the output of one of the inverters.

7. A memory cell according to Claim 1, characterised in that the voltage follower is a transistor and a pass transistor is connected between the output of each of the inverters and a data line.

8. Memory cells according to Claim 1 and as herein described.

9. A content addressable memory, characterised in that it comprises a two dimensional array of memory cells according to any of the Claims 1 to 8.

10. A content addressable memory according to Claim 9, characterised in that the power supply connections from each memory cell are connected to a common supply line, the multipurpose connection in each memory cell on one axis are connected together to form a series of signal and power supply lines, and the data lines in each memory cell on the opposite axis of the array are connected together to form a series of pairs of data lines.

11. A content addressable memory accord ing to Claims 9 or 10, characterised in that each signal and power supply line is switchably connected to a common supply line through an interface.

12. A content addressable memory according to Claim 11, characterised in that the interface comprises a transistor switch connected between the common supply line and the multipurpose supply line and an inverter.

13. A content addressable memory according to Claim 9 and as herein described.

14. A method of operating an associative memory comprising memory cells and arrays according to any of the claims 1 to 13 to perform KEEP, MATCH, WRITE and READ operations, characterised in that in the KEEP mode a full power supply potential is maintained between the power supply and the multipurpose connection; in the MATCH mode the potential on one of the data lines is raised to that of the power supply, the multipurpose line is disconnected from its power supply and its potential sensed by peripheral circuit means; and in the WRITE mode appropriate potentials are applied to the data lines to set the state of the inverters while the multipurpose line is connected to it power supply.

15. A method of operating an associative memory comprising memory cells and arrays according to Claim 14, characterised in that in the READ mode the data lines are precharged to an intermediate potential between those of the two power supply lines while the multipurpose line is disconnected from its power supply and thereafter the multipurpose line is reconnected to its power supply so that the potential on the data lines may be read by peripheral circuit means.

16. A method of operating an associative memory comprising memory cells and arrays according to Claim 14, characterised in that in the READ modes the data is read from arrays of cells in a bit-serial word-parallel manner.