GB2194858A - A process for silicon device isolation - Google Patents

Abstract

A process is described which allows the forming of narrow oxide- filled trenches in single crystal silicon. This is achieved by using an oxide-etch resistant medium eg. poly-silicon, forming from this a remanent sidewall fillet (15), and using this fillet (15) as a mask to form a narrow rib (17) in underlying material. The substrate (1), but for that narrow region masked by the rib (17), is then covered with photoresist (19), and the rib (17) is removed to expose a narrow trench feature. The substrate (1) is then etched to define an isolation trench and this trench is filled with oxide to form the isolating structure. This process can be used to isolate both MOS and bipolar components. <IMAGE>

Description

SPECIFICATION A process for silicon device isolation Technical Field The present invention concerns improvements in or relating to processes for silicon device isolation. Hitherto it has been conventional practice to use oxide isolation to separate the active areas of a silicon integrated circuit.

With the current demand for very large scale integration and therefore high packing densities, it is becoming increasingly important to define narrow isolation structures.

The invention is intended to have application in device manufacturing processes, both for bipolar and for metal-oxide-semiconductor (n MOS, CMOS) processing.

BACKGROUND ART Hitherto, oxide isolation structures have been defined by conventional processing using local oxidation of silicon (LOCOS). See for example, UK Patent No 1208574 and Appels, J.A, et al., Philips Research Reports, Vol 25 (1970) pages 1i8-132. In this processing, localised oxide structures are defined with the aid of patterned masks of non-oxidisable material, usually of silicon nitride. The oxide structures formed have the characteristic shape of a birds head and beak. The height of the birds head is often such as to introduce non-planarity and the birds beak itself encroaches into the isolated active area. The scope for very high packing densities is thus limited by these factors.

Trench isolation has been considered as an alternative. However, trenches as narrow as eg. 0.251tm cannot in general be formed using standard optical lithography. This very narrow trench size may be attained instead by electron beam lithography. This technique however is both expensive and slow. A better alternative is therefore sought.

DISCLOSURE OF THE INVENTION The present invention is intended to provide a better alternative, a process by which means it is possible to produce narrow oxidefilled trenches at relatively low cost and at a reasonable speed.

In accordance with the invention thus there is provided a process for silicon device isolation, this process including the following steps: providing a single crystal silicon substrate, which substrate is covered by a layer of etchstop material, and by a further covering layer of first masking material; forming from the first masking material a narrow rib structure; covering the surface thus exposed with resist; removing the rib structure to define a trench in the resist; and, thereafter, defining a trench in the silicon substrate and infilling the same with thermal grown oxide, this latter to provide an isolation structure.

It is both convenient and practical to form the rib structure by first forming a shallow edge discontinuity in the surface of the first masking material. This then is covered by a covering layer of a second masking material and this is etched back to leave a fillet of material at the foot of the edge discontinuity.

This latter fillet is then used as a mask during subsequent anisotropic etching of the first masking material.

Examples of etch-stop material, first masking material and second masking material, are respectively poly-silicon, undoped deposited oxide, and, poly-silicon. A layer of oxide may be interposed between the etch-stop layer and the substrate.

As will be described below, the provision of a narrow width rib structure allows the definition of a very fine trench-window in the resist.

This thus overcomes the difficulties hitherto found with optical lithography. It is also a quicker process than that of e-beam lithography and is less expensive to impliment.

Other objects and advantages of this invention will be apparent from the description that follows.

BRIEF INTRODUCTION OF THE DRA WINGS In the drawings accompanying this specification Figures 1 to 7 are illustrative cross-section views of a covered silicon device substrate as provided by the consecutive steps of a process which embodies the present invention.

DESCRIPTION OF A PREFERRED EMBODIMENT So that the invention may be better understood, a preferred embodiment thereof will now be described and reference will be made to the accompanying drawings. The description that follows is given by way of example only.

As a starting structure there is provided a single crystal silicon substrate 1, the surface of which is covered by a succession of covering layers 3 to 9. The first of these covering layers, layer 3, is of undoped oxide, which later will be utilised in part to provide a surface isolation layer in the end product of this process. It will also act as a mask during trench definition. This layer 3 in a typical process might be, say, 4000 A thick. In this example, a second covering layer 5 is provided. This is provided to protect the device oxide layer 3 during initial steps of the processing, and will act as an etch-stop during etching of a rib formed in the next successive layer 7, a step that will be explained below.

This second covering layer 5 can be of polysilicon material and this could be 1000 A thick in a typical process. The third covering layer, layer 7, from which a rib structure will be formed, is also provided and this in turn is covered by a spun-on layer of resist 9 by which means it is to be patterned during the initial steps of this process. Conveniently, the third covering layer 7 is provided by deposited oxide material and in a typical process this could be 1.2 #m thick.

At the stage shown in Figure 1, the resist layer 9 has been selectively exposed, and it has ben developed to expose part of the surface of the underlying layer 7. The exposed part of the underlying layer 7 has been etched to remove exposed material to a shallow depth and to define thus a steep-walled step discontinuity 11 in the surface of the third covering layer 7. It is important that the exposed edge 11 is vertical (or near vertical) so that in subsequent processing the position and thickness of the rib can be well characterised.

This step of the process thus is best performed by using an anisotropic reactive ion etch technique, for example using CHF3 plasma. The details of this technique are well known and therefore are not detailed herein.

The depth of the step 11 is also to some degree critical. On this will depend the width of the rib formed during subsequent processing. To form a 0.5 ,um wide oxide filled isolation trench, a step depth of 3500 A approx.

is considered suitable.

At the next stage shown in Figure 2, the remanent resist material 9 has been removed-eg by ashing or the like, and a conformal coating of masking material applied to cover the upper surfaces 13 and edge wall 11 of the third covering layer 7. The major part of this conformal coating has then been removed to leave, in relief, a narrow fillet 15 of the masking material. The coating is preferably of poly-silicon material and this is best removed by an anisotropic reactive ion etch technique, for example, SiCL4 plasma the details of which again are well known. The fillet 15 shown thus formed is typically 3000 A wide.

At the stage of the process shown in Figure 3, the major part of the third covering layer 7 has been removed, thus leaving a narrow rib 17 of remanent material. This etch step of the process is performed using an anisotropic reactive ion etch technique, for example, CHEF, plasma using the fillet 15 as a mask, and is continued until the etch-stop barrier layer 5 is reached. Some erosion of the fillet 15 is likely to occur, and the width of the fillet covered rib 17 formed would be typically 2500 A.

As shown in Figure 4, a layer 19 of resist is then spun onto the covered substrate 1 and, as a precaution, this is etched back to ensure exposure of the fillet 15 and upper portion of the rib 17. In the example shown the resist is spun-on to a thickness ~ 1 ,um and etched back #2000 A. By the next stage of the process shown in figure 5, the fillet 15 has ben removed eg by a dry etch, and the rib material 17 removed by a suitable etchant, either wet or dry as may be preferred. The exposed etch-stop material, of layer 5, has been removed also, in this example by a dry etch.

In figure 6 the exposed part of the first covering layer, oxide material, has been removed by a suitable anisotropic reactive ion etch technique-for example, CHF3 plasma, and the remanent resist material, layer 19 then removed. The second covering layer 5 can then be removed, though alternatively this may be left until after or during trench definition. The exposed material of the silicon substrate 1 is then removed by an anisotropic reactive ion etching SiCL4 plasma, to define a trench 21 of depth suitable for the isolation structure, typically 3 ,um, using the patterned second layer 5 and first layer 3 as a mask.

In the final stage of this process, Figure 7, the exposed silicon is then thermally oxidised so that the trench 21 is completely infilled with isolation oxide 23.

For simplification, a single rib and trench have been shown in the drawings. In practice these will be formed to isolate islands of device active area. In plan thus each will have the form of a closed feature.

Variants of the above will be apparent to those of skill in this art, and the example described is not intended to restrict the scope of the invention as recited in the claims that follow hereinafter.

Claims (7)

1. A process for silicon device isolation, this process including the following steps: providing a single crystal silicon substrate, which substrate is covered by a layer of etchstop material, and by a further covering layer of first masking material; forming from the first masking material a narrow rib structure; covering the surface thus exposed with resist; removing the rib structure to define a trench in the resist; and, thereafter, defining a trench in the silicon substrate and infilling the same with thermal grown oxide, this latter to provide an isolation structure.

2. A process, as claimed in claim 1, wherein the narrow rib structure is formed by first providing a shallow step discontinuity in the surface of the covering layer of first masking material; covering the surface thereafter with a conformal coating of a second masking material; etching back the second masking material to leave a fillet thereof at the foot of the step discontinuiity; and, using this fillet as a mask whilst etching away the exposed first masking material to form the rib structure.

3. A process, as claimed in either claims 1 or 2, wherein the first masking material is of deposited undoped oxide.

4. A process, as claimed in any one of the preceding claims 1 to 3, wherein the second masking material is of poly-silicon.

5. A process, as claimed in any one of the preceding claims, wherein the etch-stop layer is of poly-silicon.

6. A process, as claimed in any one of the preceding claims, wherein there is interposed between the etch-stop layer and the silicon substrate, a layer of undoped oxide.

7. A process for silicon device isolation, when performed substantially as described hereinbefore, with reference to, and, as shown in, the accompanying drawings.