GB2193823A - Information storage apparatus - Google Patents

Abstract

In an address translation system for translating a virtual address into a real address, the virtual address is hashed to form a hash address TADDR and a residue, RESIDUE. The hash address is used to access a memory, 10, each location of which contains a real address, RADDR, a tag, TAG, and a next address NADDR. The next address points to another location, thereby linking the locations together to form a number of circular chains. The tag of the addressed location is compared with the residue and, if they match, the address translation is successful. If they do not match, the memory is accessed again, this time using the next address value from the currently addressed location. In this way, a chain of locations is scanned until either a match is found, or else the first location in the chain is returned to, indicating that the translation has been successful. <IMAGE>

Description

SPECIFICATION Information storage apparatus Background to the invention This invention relates to information storage apparatus.

The invention is particularly, although not exclusively, concerned with information storage apparatus for use in a virtual memory system, as a translation table for converting virtual addresses into real addresses.

One such virtual memory system is described for example in US Patent Specification No. 3 829 840. That specification describes an address translation table comprising a memory having a plurality of locations, each of which holds a real address value and a corresponding tag value. The memory is addressed by a hash address consisting of a selection of the bits of the virtual address.

The non-selected bits of the virtual address are compared with the tag value read out from the addressed location of the memory and, if they are equal, a match signal is produced indicating that the address translation is successful. Otherwise, if no match is detected, the translation table must be updated by fetching the required real address from the main store of the system and inserting it into one of the locations of the memory.

It can be seen that, since the memory is addressed by a hash address consisting of a selection of the bits of the virtual address, each location of the memory is addressable by any one of a plurality of different values of the virtual address (differing in the non-selected bits of the virtual address). In other words, there is a many-to-one mapping between the values of the virtual address and the locations of the memory. This can give rise to problems if two or more virtual addresses, all of which map on to the same location of the memory, are being used concurrently, since clearly only one of the corresponding real addresses can be held in the memory at any one time. This can result in continual updating of the translation table and a consequent loss of performance.

The object of the present invention is to overcome this problem.

Summary of the invention According to the present invention, there is provided information storage apparatus for accessing an information item in response to an input address, comprising a memory having a plurality of locations each of which holds an information item and a tag value, each location being addressable by a plurality of different values of the input address, wherein the tag value of each addressed location is compared with at least a part of the input address to produce a match signal indicating whether or not the addressed location contains a required information item, characterised in that each location also contains a next address value pointing to another one of the locations, thereby linking the locations together to form at least one chain, and in the event that the match signal indicates that the addressed location does not contain the required information item, the next address in that location is used to address the memory thereby to access the next location in the chain.

Brief description of the drawings One information storage apparatus in accordance with the invention will now be described by way of example with reference to the accompanying drawings.

Figure 1 is a block diagram of an address translation unit, comprising the information storage apparatus.

Figures 2 and 3 are logic diagrams showing a comparison and control logic circuit in detail.

Figure 4 is a timing diagram illustrating the operation of the apparatus.

Description of the embodiment of the invention Referring to Figure 1, this shows an address translation unit, for use in a virtual memory system. The address translation unit receives an input virtual address, consisting of 40 bits VA 0-39, and converts it into a 25-bit real address RAO-24. Bits VA10-39 of the virtual address represent a virtual page address, while bits VA 0-9 point to a particular byte within the page. The virtual page address is translated to provide a 15-bit real page address RA 10-24, while bits VA 0-9 directly supply bits RA 0-9 of the real address.

The address translation unit includes a static random access memory (RAM) 10, having 16K (= 16384) individually addressable locations. Each location contains: (a) a 15-bit real page address RADDR, (b) a 16-bit tag value TAG, (c) a 14-bit next address field NADDR, (d) a header bit HEAD, and (e) access protection bits ACPR. These comprise a write protect bit WRPR, a read protect bit RDPR, and an execute protect bit EXPR.

The locations in the RAM are organised in chains, the next address field NADDR of each location pointing to the next location in the chain. The first location in each chain is indicated by the header bit HEAD being set; all the other locations in the chain have HEAD=O. The next address field NADDR of the last location in each chain points back to the first location, so that each chain is circular.

The RAM 10 is addressed by a 14-bit address signal TADDR. This is derived from one of two sources: a register 11 and a hashing circuit 12. The output of the register 11 is enabled by the low value of a control signal OEMUX, while the output of the hashing circuit 12 is enabled by the low value of the output from a NAND gate 13, which combines OEMUX and a control signal TRANS.L. Thus, it can be seen that when OEMUX is low, the output of register 11 is selected, and when OEMUX is high, the output of the hashing circuit 12 is selected, provided that TRANS.L is high.

The register li is connected to the output of a multiplexer 14, and is loaded with data from the multiplexer when a signal CLKMUX.H goes high. The multiplexer 14 is controlled by the signal TRANS.L: when TRANS.L is low, the multiplexer selects the 14 least significant bits VA 0-13 of the input virtual address;, when TRANS.L is high, the multiplexer selects the 14-bit next address NADDR from the currently addressed location of the RAM 10.

The hashing circuit 12 receives the 30-bit virtual page address VA 10-39 and selects a predetermined set of 14 of these bits as the address TADDR to the RAM 10. The remaining 16 non-selected bits to provide a. RESIDUE signal. Thr hashing circuit 12 may, for example, comprise a set of patch-plugs which can be programmed manually to select a particular combination of bits. For example, in one particular setting, the hashing circuit 12 may select bits VA10-23 as the address TADDR the remaining bits VA24-39 forming the RESI DUE.

The signals TAG, HEAD and ACPR from RAM 10 and the RESIDUE signal from the hashing circuit 12 are fed to a comparison and control circuit 15. This circuit also receives a function signal FC which indicates whether the current virtual address is to be used for a read or write access, or for accessing an instruction.

In operation, the comparison and control circuit 15 compares the signals TAG and RESI DUE, and also checks the access protection bits ACPR against the function signals FC to ensure that they are consistent. If TAG and RESIDUE match, and the access protection check is satisfactory, a HIT signal is produced, indicating that the address translation is successful.

If TAG and RESIDUE do not match, then the circuit 15 issues control signals CLKMUX.H and OEMUX which cause the next address NADDR from the currently addressed location of the RAM to be loaded into the register 11 and then to be applied to the RAM as the address TADDR. This causes the next location in the chain to be accessed. This cycle is repeated for each subsequent location in the chain in turn until either: (a) a location is found for which TAG and RESIDUE match, and the access protection check is satisfied, (b) a location is found for which TAG and RESIDUE match, but the access protection check fails, or (c) the first location of the chain, indicated by HEAD 1, is returned to.

In the first case, a HIT signal is produced, indicating that the translation is successful. In either of the other two cases, an error signal ERR is produced, indicating that the translation has failed either because the required real address is not present in the table, or because the access protection check has failed.

The translation of a virtual address is initiated by an address strobe signal AS.H which is pulsed low whenever a new virtual address is presented.

Figure 2 shows the comparison section of the circuit 15 in detail, while Figure 3 shows the control section of the circuit 15 in detail.

Referring to Figure 2, the function signal FC consists of three bits WR.L, RD.L and EX.L.

WR.L=O indicates a write access, RD.L=O indicates a read access, and EX.L=O indicates an access to an instruction for execution.

The three function bits are combined with the respective access protection bits WRPR, RDPR and EXPR in three AND gates 20 with inverting inputs. The outputs of these AND gates 20 are in turn combined in a NOR gate 21, along with a signal TRANS H, the inverse of TRANS.L.

It can be seen that, if the function bits are consistent with the access protection bits, then the output of the NOR gate 21 is low.

For example, if a write access is specified (WR.L=O) and the write protection bit is not set (WRPR=O) then the first of the AND gates 20 is enabled, which causes the output of the NOR gate 21 to go low. If, on the other hand, the function bits are inconsistent with the corresponding access protection bits, then the output of the NOR gate 21 is high, indicating that the access protection check has failed.

Normally, the signal TRANS.H is low. However, if this signal is set high, then the output of the NOR gate 21 is held low. In other words, this suppresses the access protection check.

The TAG and RESIDUE signals are compared by means of a comparator 22, which produces a low output signal if they are equal, and a high output signal if they are not equal.

The comparator 22 is enabled by a signal AS.L, the inverse of the address strobe signal AS.H.

The output of the comparator 22 is combined with the output of the NOR gate 21 in an AND gate 23 with inverting inputs. The output of the AND gate 23 is combined with the signal TRANS.H in an OR gate 24 and a NOR gate 25 to produce respective signals MATCH.H and MATCH.L.

It can be seen that if TRANS.H is low, then MATCH.H is high if and only if TAG matches the RESIDUE signal, and the access permission check is satisfactory. MATCH.L is the inverse of MATCH.H, i.e. it is high if either TAG and RESIDUE do not match or the access permission check has failed.

The output of the comparator 22 is inverted in a gate 26, and combined with the output of the NOR gate 21 in a NAND gate 27, to produce a signal ACPER.L. It can be seen that ACPER.L will be low if and only if TAG and RESIDUE match, but the access protection check has failed.

Referring now to Figure 3, this shows the control portion of the circuit 15 in detail.

The control portion comprises seven D-type flip-flops (bistable circuits) 31-37. Each of these flip-flops has a data input D, a clock input C, set and reset inputs S,R, and true and inverse data outputs Q and Q. Flip-flops 34-37 receive a clock signal CLK.H at their clock in inputs, while flip-flops 31 and 32 receive the inverse of this clock signal CLK.L.

Flip-flop 34 produces at its inverse data output the control signal OEMUX which, as described above, controls the selection of the address TADDR for the RAM 10.

Flip-flop 35 produces at its true data output the control signal CLKMUX.H which, as described above, is used to clock the next address NADDR into the register 11. The flipflop 35 also produces the inverse signal CLKMUX.L from its inverse output.

Flip-flop 36 produces the HIT signal which indicates a successful translation, while flipflop 37 produces the ERR signal which indicates failure of the translation operation.

The address strobe signal AS.H is applied to the reset inputs of the flip-flops 31,32 so that both these flip-flops are reset when AS.H goes low, i.e. when a new virtual address is presented for translation.

The address strobe AS.H is also applied to the data input of flip-flop 31, the output of which produces a signal SYAS. This signal SYAS therefore represents a version of AS.H, synchronised to the clock CLK.L.

The signal SYAS is applied to the data input of flip-flop 32, the output of which produces a signal DSYAS. This signal DSYAS therefore represents a version of SYAS, delayed by one beat of the clock CLK.L.

The signal DSYAS is applied to the reset inputs of the flip-flops 34-37, so as to reset each of these flip-flops when DSYAS is low, i.e. approximately one clock beat after AS.H goes low.

The signal SYAS is also fed to the clock input of the flip-flop 33, the data input of which is connected to a constant low logic level. Therefore, the flip-flop 33 is clocked into its reset state whenever SYAS changes from low to high. The set input of flip-flop 33 receives the signal CLKMUX.L, so that it is set whenever CLKMUX.L goes low. The inverse output of flip-flop 33 provides a signal FIRST.

It can be seen, therefore, that the flip-flop 33 is reset at the start of each address translation operation, and is then set again when the first next address NADDR is clocked into the register 11. The signal FIRST therefore indicates that the RAM 10 is currently being addressed for the first time in the current address translation operation.

The signal FIRST is combined in an exclusive-OR gate 38 with the HEAD signal from RAM 10, to produce a signal ENDSC. This signal ENDSC is therefore high whenever HEAD is high but FIRST is low. In other words, ENDSC is not produced when the first location in a chain is addressed for the first time, but is produced if that first location is returned to after scanning all the other locations in the chain.

The signal ENDSC is fed to one of the inverting inputs of the AND gate 23 (Figure 2), so as to force the output of that AND gate low whenever ENDSC is high. The signal ENDSC is also combined with CLKMUX.H in an AND gate 39 with inverting inputs. The output of the AND gate 39 is combined in an AND gate 40 with the signals MATCH.L and ACPER.L from the comparison section (Figure 2).

The output of AND gate 40 is fed to the data input of flip-flop 35. The signal CLKMUX.H is therefore set to the same value as the output of AND gate 40 at each rising edge of CLK.H.

The output of AND gate 40 is also fed to the data input of the flip-flop 34. The inverse data output of this flip-flop provides the control signal OEMUX which controls the selection of the address signal TADDR for the RAM 10, as shown in Figure 1. The signal OEMUX is also fed back to the set input of the flip-flop 34, so as to hold this flop-flop into its set state when OEMUX is low. Thus, it can be seen that the flip-flop 34 is initially reset by the low value of DSYAS at the start of each address translation operation. The flipflop 34 will then be set at the first rising edge of clock CLK.H at which the output of AND gate 40 is high. This makes OEMUX low, so that the flip-flop 34 will then be held in the set state, irrespective of the value of the output of AND gate 40, until it is reset again by DSYAS going low.

The signal ENDSC is also combined in a NAND gate 41 with the signal TRANS.L. The output of this NAND gate is in turn combined with the signal ACPER.L in an OR gate 42 with inverting inputs, to produce a signal TERM. It can be seen that TERM will go high if either ENDSC goes high (and TRANS.L is high) or ACPER.L goes low. In other words, TERM indicates that either a complete chain of locations has been scanned, without finding a match between TAG and RESIDUE, or else a match has been found but the access protection check has failed.

The signals TERM and CLKMUX.L are combined in a NOR gate 43 with inverting inputs, the output of which is fed to the data input of the flip-flop 37. The output of the flip-flop 37 provides the error signal ERR which indicates that the address translation has failed.

The MATCH.H is fed to the data input of flip-flop 36, the output of which provides the signal HIT which indicates that the address translation has been successful.

Operation The operation of the address translation unit will now be described, referring also to Figure 4 which is a timing diagram of various signals during operation. It will be assumed in the following description that the control signal TRANS.H is held low, and that its inverse TRANS.L is therefore high.

As mentioned above, whenever a new virtual address is presented for translation, the address strobe signal AS.H is pulsed low.

This resets the flip-flops 31,32, making SYAS and then DSYAS low. The low value of DSYAS resets the flip-flops 34-37.

When flip-flop 34 is reset, the signal OE MUX goes high and therefore the output of the hashing circuit 12 is selected as the address TADDR for the RAM 10. The RAM is therefore addressed by the hash address derived from the input virtual address, and the contents of the addressed location are read out. This location should be the first location of a chain, and therefore HEAD should be high.

When AS.H returns to its high level, SYAS and DSYAS go high again. The rising edge of SYAS clocks the flip-flop 33, making the signal FIRST high. If HEAD is high (as it should be), ENDSC will therefore be low. Since CLWMUX.H is also low, the AND gate 39 is enabled.

If the TAG value in the currently addressed location of the RAM 10 does not match the RESIDUE signal, both MATCH.L and ACPER.L wil be high. Therefore, the AND gate 40 is enabled, and the flip-flops 34 and 35 are both set at the next rising edge of CLK.H. This makes CLKMUX.H high and OEMUX low.

The rising edge of CLKMUX.H causes the next address- value NADDR to be clocked into the register 11 by way of the multiplexer 14.

The low value of OEMUX selects the output of the register 11 to address the RAM 10, instead of the output of the hashing circuit 12. Thus, the next location of the chain is now addressed in the RAM 10.

The high value of CLKMUX.H also disables the AND gate 39, making the output of AND gate 40 low. Thus, at the next rising edge of CLK.H, the flip-flop 35 is reset, making CLKMUX.H low again. However, flip-flop 34 remains set, because of the feedback connection of OEMUX to the set input. Hence, the RAM 10 continues to be addressed by the output from the -register 11.

The process described in the preceding three paragraphs will be repeated, for each successive location in the chain in turn, until one of the following conditions occurs: (a) The TAG value of the currently addressed location matches the RESIDUE signal, and the access protection check is satisfactory, so that MATCH.L goes low.

(b) The TAG value of the currently addressed location matches RESIDUE, but the access protection check fails, so that ACPER.L goes low.

(c) The first location of the chain is returned to, so that HEAD goes high, making ENDSC high.

If any of these conditions occurs, the output of the AND gate 40 is held low, preventing CLKMUX.H from going high. This prevents any more next address values NADDR from being clocked into the register 11.

In case (a), the signal MATCH.H is high, so that flip-flop 36 is set. The HIT signal is therefore produced, indicating that the address translation has been successfully completed.

In case (b) or (c), the signal TERM is produced, so that flip-flop 37 is set. The ERR signal is therefore produced, indicating that the address translation process has failed.

It should be noted that if the first addressed location of the RAM at the start of the address translation procedure does not have its header bit HEAD set, then the exclusive-OR gate 38 will produce a high output ENDSC when FIRST goes high. This generates an error signal ERR, since the first location in a chain should have the header bit set.

It was assumed in the above description that the control signal TRANS.H was low and TRANS.L high. If TRANS.H is set high, and TRANS.L low, the operation is as follows. As can be seen from Figure 1, the high value of TRANS.H switches a multiplexer 19 so as to select bits VA 10-24 of the virtual address, instead of the address RADDR. Hence, in this case, bits VA 0-24 of the virtual address pass transparently through the unit to provide the real address RA 0-24, without any address translation.

It will be appreciated that the present invention is not confined to an address translation table. It may, for example, be used in a data slave store, which holds data items rather than real addresses.

Claims (8)

1. Information storage apparatus for accessing an information item in response to an input address, comprising a memory having a plurality of locations each of which holds an information item and a tag value, each location being addressable by a plurality of different values of the input address, wherein the tag value of each addressed location is compared with at least a part of the input address to produce a match signal indicating whether or not the addressed location contains a required information item, characterised in that each lo cation also contains a next address value pointing to another one of the locations, thereby linking the locations together to form at least one chain, and in the event that the match signal indicates that the addressed location does not contain the required information item, the next address in that location is used to address the memory thereby to access the next location in the chain.

2. Apparatus according to Claim 1 wherein the next address value in the last location of the chain points back to the first location in the chain, so that the chain is circular.

3. Apparatus according to Claim 2 wherein each location in the chain is accessed in turn until either the match signal indicates that the location contains the required information item or else the first location in the chain is returned to.

4. Apparatus according to any preceding claim, wherein the memory is addressed by a hash address formed by selecting a predetermined combination of bits of the input address.

5. Apparatus according to Claim 4 wherein the remaining bits not selected to form the hash address are compared with the tag value to produce said match signal.

6. Apparatus according to any preceding claim wherein each location of the memory contains protection bits indicating restrictions on the use of the information contained in that location.

7. An address translation unit for a virtual memory system, comprising information storage apparatus according to any preceding claim, the input address for the apparatus being a virtual address, and the information items stored in the memory being real addresses.

8. Information storage apparatus substantially as hereinbefore described with reference to the accompanying drawings.