GB2191321A - Normaliser circuit - Google Patents

Abstract

A normaliser circuit for dividing an AC signal a sin omega t by a reference voltage to give, as quotient, an AC signal whose amplitude is related as a multiple or fraction to the reference voltage comprises a linear detector which receives the initial AC signal, followed by a divider whose denominator is the detector output a and whose numerator is the reference voltage V1 (which may be DC or long-period AC or related to the input amplitude). The divider output is fed to a balanced square-law mixer whose other input is the initial AC signal and whose output is the desired quotient. Preferably there is connected between the detector and the divider additional circuitry (Fig. 2) which limits the minimum input to the divider to the lower limit (V2) of the latter's dynamic range in order to prevent instability. A plurality of such circuits connected in series by amplifiers, (Fig 3), can be used to cover a dynamic range greater than that of a single divider and/or mixer. The circuit may be used to provide limiting without clipping, or, when the reference voltage V1 varies slowly compared with omega , to change the modulation on the ac signal. <IMAGE>

Description

SPECIFICATION Improvements in or relating to normaliser circuits This invention relates to normaliser circuits, in particular to normaliser circuits in which an AC signal is divided by a reference amplituide to give, as quotient, an AC signal whose amplitude is related, as a multiple or fraction, to the reference amplitude. In circuits of the present kind the reference amplitude will commonly be DC, but can be AC having a much longer period than the aforesaid AC signal.

The quotient will commonly have an amplitude independent of the input amplitude, eg independent of "a" where the input is of the form "a sincut", and may be of constant amplitude.

However, in some applications the amplitude of the quotient may be made some function of the input amplitude by deriving the reference amplitude appropriately from eg a longperiod varying input amplitude; in other applications, eg to replace an existing modulation by a different modulation, the reference amplitude may vary independently of the input amplitude. Thus in either of the latter examples, the amplitude of quotient will not be constant.

Such normaliser circuits can also function in some applications as a form of limiter, for preventing an AC signal exceeding a predetermined amplitude without merely clipping the signal at that amplitude and thereby introducing distortion: ie, as a limiter it functions rather in an AVC mode than in a clipping mode.

It is possible in principle to normalise an AC signal, again, for sinplicity, of the form "a sinowt", relative to a DC reference amplitude of, say, for convenience, 1 volt, by detecting the signal, to derive "a", and dividing "a sincot" by "a" (thus derived) using a conventional divider circuit as available from such companies as Burr-Brown Ltd, Analog Devices Ltd, etc.However, such an arrangement is capable only with difficulty of providing normalising/limiting action without distortion, because of the following problems: (i) the use of such a divider circuit severely restricts the frequency-handling capability of the arrangement; (ii) further to (i), harmonics of the numerator input "a snot" would soon be produced at above a fairly low dynamic range level; (iii) the lower limit of the dynamic range level of the denominator "a" tends to be severely limited by the need to keep its amplitude away from zero, at which level the resultant divider output would become unstable (ie 1/0 tends to an indeterminate value). Typical stable dynamic range levels of available dividers are from 0.5 to 10 volts.

The present invention provides forms of normaliser circuit which alleviate at least some of the above problems.

According to the present invention, a normaliser circuit comprises: a linear detector having an input connection for an AC input signal; a divider having its denoninator input connected to the detector output and its numerator input connected to a reference voltage; and a balanced square-law mixer having one input connection for said AC input signal and its other input connected to the divider output, whereby the output of said square-law mixer is said AC signal with its amplitude modified to be proportional to its input amplitude divided by said reference voltage.

The normaliser circuit may also include, connected between said linear detector and said divider, means for summing together a constant DC voltage equal to the lower limit of the stable dynamic range of the divider, the linear detector output, and a version of the linear detector output limited in amplitude to said constant DC voltage and of opposite polarity therefrom, said sum forming the input to said divider, whereby correct numerical division is maintained over the stable dynamic range of the divider.

The normaliser circuit may further comprise a plurality of circuits as defined in the immediately preceding paragraph, said circuits being connected in series with an amplifier connected between each successive pair, whereby to maintain the input to each divider and to each mixer within the dynanlc ranges of each.

The present invention will now be described, by way of example, with reference to the accompanying drawings wherein; Fig 1 is a block schematic circuit diagram of a normaliser circuit embodying the invention.

Fig 2 is a similar diagram of a modification of the circuit of Fig 1.

Fig 3 is a similar diagram of a modification of the circuit of Fig 2.

Fig 1 shows a normaliser circuit which overcomes problems (i) and (ii) referred to in the introduction. The input "a sincut" is fed to a conventional linear detector to derive a signal "a" which varies only relatively slowly, if at all, with time, and also to a conventional square-law balanced mixer functioning in a known manner as a multiplier. The signal "a" is fed as denominator to a conventional divider circuit (eg as obtainable from the two companies mentioned), to which a DC reference voltage, V1, is fed as numerator. In this example the reference V1 is 1V, so that the quotient is 1/a.This quotient is the second input of the balanced mixer, whose output therefore includes the desired product term, "sinwt". Problems (i) and (ii) are eliminated because the divider is now handling virtual DC and not the relatively high carrier frequency w.

Problem (iii) remains, but can be overcome by the circuit shown in Fig 2. In this arrange ment a constant DC voltage V2 equal to the lower amplitude limit of the dynamic range of the divider is added to the linear detector output "a". Also added thereto is a version of "a", limited in maximum amplitude to V2 (provided a > V2) and inverted in sign. Thus the input to the divider, for a > , is a-V2+V2=a, and for a cV2 the input to the divider is a-a+V2=V2.

Thus when "a" falls bellow the dynamic range limit of the divider (V2), the divider output does not become unstable and/or indeterminate, but merely declines in amplitude to 1/V2. This in turn reduces the output to a/V2 sinot instead of the nominal unity (V1 = 1V) of the normalised value. Thus the output is not fully normalised but has a "dip" in it to the value of a/V2.

Fig 3 shows a modification which reduces the magnitude of the aforesaid dip. It comprises two or more circuits 31, 32, 33 connected in series, each consisting of a Fig 2 circuit and, if needed, having amplifiers 34, 35 connected between these circuits. The final "sinwt" output is taken from the last circuit of the series. In this way a divider (and/or square-law mixer) with a dynamic range limitation of, say, 20 dB can provide a 60 dB performance, ie using three series-connected circuits as shown. The first circuit handles the top 20 dB of the total range, the second the middle 20 dB, and the last the bottom 20 dB.

In any of the described embodiments the amplitude of the final "sinwt" output can be adjusted to a desired normalised value by appropriate amplification or attenuation of the mixer output as necessary.

Although in the described embodiments the reference voltage V1 is a DC voltage, as explained in the introduction this need not always be the case. As likewise explained, the output amplitude need not be wholly independent of the input amplitude.

If required, an output of amplitude 1/a corresponding to the reciprocal of the amplitude of the original input signal can be taken from the output of the divider in Fig.1 and 2. Such an output may be used in some applications, for example, as a multiplying factor in the processing of a second input signal B, as shown by the interrupted line portion of Fig 2. In the circuit of Fig 3, this usage is effected by feeding the output of the divider in each of the circuits 31, 32, 33 to corresponding multipliers 36, 37, 38 connected in series, plus amplifiers 39, 40 if needed, to the first of which is connected the second input signal as shown. An output of amplitude "a" can likewise be taken from the output of the linear detector in Figs 1 and 2.

Claims (4)

1. A normaliser circuit comprising: a linear detector having an input connection for an AC input signal; a divider having its denominator input connected to the detector output and its numerator input connected to a reference voltage; and a balanced square-law mixer having one input connection for said AC input signal and its other input connected to the divider output, whereby the output of said square-law mixer is said AC signal with its amplitude modified to be proportional to its input amplitude divided by said reference voltage.

2. A normaliser circuit as claimed in claim 1 including, connected between said linear detector and divider, means for summing together a constant DC voltage equal to the lower limit of the stable dynamic range of the divider, the linear detector output, and a version of the linear detector output limited in amplitude to said constant DC voltage and of opposite polarity therefrom, said sum forming the input to said divider, whereby correct numerical division is maintained over the sta ble dynamic range of the divider.

3. A normaliser circuit comprising a plurality of circuits as claimed in claim 2, said circuits being connected in series with an amplifier connected between each successive pair, whereby to maintain the input to each divider and to each mixer within the dynamic ranges of each.

4. A normaliser circuit substantially as hereinbefore described with reference to the accompanying drawings.