GB2189968A

GB2189968A - Telephone interface circuit

Info

Publication number: GB2189968A
Application number: GB08709627A
Authority: GB
Inventors: Adrian Dixon; John Anthony Swanwick
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1986-04-28
Filing date: 1987-04-23
Publication date: 1987-11-04
Anticipated expiration: 2007-04-23
Also published as: GB8610348D0; GB2189968B; GB8709627D0; DE3714119A1

Description

GB 2 189 968 A 1

SPECIFICATION

Telephone Interface Circuit The present invention concerns an interface for use in a digital telephone system. Digital telephone systems have a number of advantages with respect to current analogue systems. These advantages include the easy achievement of high speed signalling in both directions, the possibility of high quality speech and 5 data transmission, and reduced cost at the exchange line termination as no analogue interfaces are required.

Public sector telephone networks have to comply with stringent international regulations which result in complex and expensive systems. However no such standardisation exists in the private sector so that much simpler systems can be utilised. Thus the present invention is particularly, though not exclusively, 10 concerned with an interface for a private sector digital telephone system.

The invention has for an object to provide an interface between a telephone circuit, a keyboard and a display.

Accordingly the invention consists in an interface for a telephone circuit capable of controlling a keyboard, but with sufficient capacity to cope with a plurality of auxiliary devices. 15 In order that the invention may be more readily understood, an embodiment thereof will now be described byway of example and with reference to the accompanying drawings, in which Figure 1 shows a basic digital telephone circuit incorporating an interface according to the present invention, Figure 2 shows the telephone circuit of Figure 1 but also incorporating additional features, 20 Figure 3 is a circuit showing a number of auxiliary circuits, Figure 4 is a circuit diagram of a key scanning mechanism, Figure 5 is a key scanning waveform diagram, Figure 6 shows an expanded key scanning mechanism, Figure 7 is an expanded waveform diagram, 25 Figure 8 is a circuit diagram of an LCD display at a terminating station, Figure 9 is a circuit showing the use of an interface according to the present invention with a display, and Figure 10 shows waveforms showing display control and data interleaved with key scanning.

Referring now to Figure 1 of the drawings this shows a telephone handset 1 coupled by a code-decode 30 (COFIDEC) 2 to a single integrated chip (IDTC) 3 which comprises a digital telephone circuit. Connected to the IDTC is a keypad 4 and a tone caller loudspeaker 5.

Figure 2 shows how the basic telephone circuit of Figure 1 can be expanded to provide additional features. Integers common to the two fingers have been given the same reference numerals. The IDTC circuit in this embodiment has additional features which are in accordance with the present invention. 35 It will be seen that the circuit of Figure 2 includes an expansion bus indicated at 10. Communicating with this expansion bus is a keybar circuit 11.

This is an integrated CMOS gate array which operates as a peripheral circuit for the IDT circuit. As a peripheral it extends the basic key scan ning/display driving mechanisms of the IDTC, and provides a mechanism for directly driving sixteen bars on a LCD. The circuit is packaged as a forty four pin surface 40 mounted device.

The keybar circuit 11 is controlled from the IDTC 3 by a ten wire interface, known as the K-interface shown at 12. This interface is unidirectional allowing buffering to be added to the IDTC when several keybar circuits and displays are used in a large terminating station.

Under control of an IDTC, the keybar circuit can, 45 - drive HIGH one of four open-drain key column outputs. - turn on/offlor flash one of sixteen directly driven LCD bars. - drive one or both general purpose output port pins. - control the sequential state of three LCD interface pins.

Each keybar is assigned a unique three bit address, which is defined bythe printed circuit board pattern 50 to which it is connected. This allows up to eight keybar circuits to be controlled independently from one IDTC, allowing, - up to 128 key switches to be scanned.

- up to 128 LC1) bars to be driven.

- up to 16 general purpose output ports to be controlled. 55 - up to 16 different alphanumeric liquid crystal displays to be controlled.

The circuit of Figure 2 also includes a bar display 20, an alphanumeric display 21, a LST (Loud Speaking Telephone) controller 22, and audio circuits and transducers 23,24 and an auxiliary keypad 30.

Figure 3 shows six keybar circuits 11 connected via the already mentioned interface to the IDTC circuit 2 GB 2 189 968 A 2 3. The 10-wire interface generally indicated at 12 includes 8 data channels and two strobe lines. In Figure 3 key matrixes are shown at 13.

The interface of the IDTC circuit 3 will now be described in greater detail. It is shown in Figure 4 and provides the mechanism by which the IDTC circuit 3 can scan up to 128 keys. The interface provides ADDRESS/DATA octets for one or several external devices such as the keybars 11. 5 Using this interface the IDTC circuit can detect and record the operation of two coincident key depressions and will operate as if to scan all 128 keys, whether they are present or not. The IDTC circuit only recognises the operation of one random key in the range 0 to 122, and the separate operation of key number 123. The operation of these two keys may be coincident allowing key number 123 to be used as a "SHIFT KEY". If more than two keys are detected simultaneously in one column, then the key with the highest key 10 number is recognised.

A key depression is recognised by the IDTC circuit 3 if the key contacts are seen to be MADE for two consecutive scans of the key matrix. A key release is recognised as a BREAK of the key contact.

The IDTC circuit 3 has an integral key scanning counter which controls the fourteen wire'K' interface 13 during periods when the interface is not being used to pass display information provided by the signalling 15 channel. Ten of these wires are used to provide column addressing signals and four wires, indicated at 15, are used to detect the voltages developed in the key matrix as a result of key depressions.

The four key matrix inputs are read by the IDTC on the failing edge of the strobe signal KST, as illustrated by arrows in Figure 6.

Figure 4 shows the eight bus wires 50 which are used to provide the eight driven column lines forthe 20 key matrix 51 shown in Figure 3 and four input lines feed into the IDTC circuit 3 from the key matrix rows.

The strobe KST wire is not required for scanning keys in this configuration. It will only be active when display control or display data has been received via the signalling channel and is being presented at the interface. The strobe pin will be de-activated for the whole key scanning cycle if at the start of the cycle the KIO input is seen to go HIGH with the control signal KCL. This will occur if the pull-down resistor, normally 25 connected to 0 volts, is connected to the control pin KCL as shown in Figure 4. This condition is only tested at the start of a key scanning cycle.

In the key scanning waveforms of Figure 5 the strobe waveform KST is shown dashed to indicate its relative position, were it to be active. During the control wire HIGH period a key control code byte will be placed on the eight bit bus ready for the strobe wire KST pulse period. Then during the control wire LOW 30 period one of the eight bus wires will be driven HIGH to provide a column drive signal for the 32 key matrix.

During the subsequent strobe pulse period the four matrix Kin inputs are read into the IDTC.

This process will be repeated with each bus wire driven individually to scan the whole 32 key matrix. In Figure 5 there is a continuous clock signal forming part of the KBO bus signal. This has no effect on the key scanning mechanism, as it occurs when the strobe is not active. 35 The interconnection of the IDTC circuit 3 with external devices is shown in Figure 6 in which all ten outputs of the IDTC circuit 3 are connected. Under control of this ten wire interface 12 the external devices drive four open-drain outputs which feed into the 4 by 4 key matrix 51. The four row wires in this matrix 51 will be connected to the Kin inputs of the IDTC circuit 3 and will be common with those four wires of the 8 by 4C) 4 matrix. The peripheral circuits are shown as auxiliary devices 60 and additional key matrices 61. 40 The waveform diagram of Figure 7 shows howthe IDTC circuit 3 controls the key scanning performed by the external device. With the control wire KCL HIGH a control byte is driven onto the eight wire bus. After a suitable settling time the strobe wire KST is pulsed to load the control byte into the external device. The control wire I(C1 is then taken LOW along with the eight bus wires and the strobe wire KST is pulsed again.

During this second strobe pulse period the external device drives one of its four matrix outputs as defined 45 by the control byte and the IDTC reads in the four Kin inputs. A NULL byte is driven onto the interface bus during this second strobe period to disable the scanning of the 8x4 matrix.

The keyscan control bytes are defined in the following table in which three bits uniquely define the byte as being a KEY control byte. Three bits define which one of eight external devices the IDTC is controlling and a further two bits define which one of the four column outputs of that device is to be driven during the 50 next strobe pulse period.

Whenever an external device detects this key control byte it ignores the presence of the following byte and only drives its four column outputs if it was addressed. After this second byte it considers the next byte as display data if "KCL" is LOW, and a control code if "KCU' is HIGH. This allows display control bytes or data bytes to be interleaved with key scanning sequence as they are received from the signalling channel. 55 Up to eight external devices can be used for display drive purposes but only six will be required to scan 128 keys.

The key control byte definition of the circuit shown in Figure 4 is as follows:

3 GB 2 189 968 A 3 K K K K K K K K B B B B B B B B 7 6 5 4 3 2 1 0 0 X X X X X 0 0 Defines byte as KEY control 0 0 0 0 X X 0 0 l st external device 5 0 0 0 1 X X 0 0 2nd external device 0 0 1 0 X X 0 0 3rd external device 0 0 1 1 X X 0 0 4th external device 0 1 0 0 X X 0 0 5th external device 0 1 0 1 X X 0 0 6th external device 10 0 1 1 0 X X 0 0 7th external device 0 1 1 1 X X 0 0 8th external device 0 X X X 0 0 0 0 l st matrix column 0 X X X 0 1 0 0 2nd matrix column 0 X X X 1 0 0 0 3rd matrix column 15 0 X X X 1 1 0 0 4th matrix column The terminating station's hookswitch is connected to the iDTC circuit 3 via a separate wire KHS. It will not be scanned by the key scanning mechanism but its operation will be detected and sent over the signalling channel just like any of the scanned keys. The key number for the hookswitch is 127. The off-hook condition of the hookswitch is similar to the key down condition on the keypad. 20 Control and character information for driving the various display options is provided via the signalling channel and passed to the external drivers by the IDTC circuit 3 using the interface.

The first byte designated for the interface is placed on the bus (KBO to KB7) with the control wire'KCL' held HIGH while the'KST'wire is pulsed, as shown in Figure 10. Subsequent bytes received via the signalling channel are then strobed CKST' pulsed) out of the interface with the control 'KCL'wire held LOW. 25 This mechanism allows the external devices to distinguish control bytes and provide the correct display control signals during the subsequent periods in which bytes from the signalling channel are passed over the interface.

Key scanning control must be suspended by the IDTC circuit 3 while a display control/data byte is being transferred from the signalling channel to the interface. Once this byte has been transferred the key 30 scanning will be resumed from the point at which it was suspended. An example of this is given in the following table:

This table is an example of suspended key scanning sequence in which LCD BAR display information has arrived via the signalling channel, destined forthe third external device in a large key system:

4 GB 2 189 968 A 4 K K K K K K K K K K K K K K W interface signals.

c B B B B B B B B S 1 1 1 1 L 7 6 5 4 3 2 1 0 T 0 1 2 3 0 0 0 0 0 0 0 0 0 0 X X X X 1 0 0 0 1 0 1 0 0 0 X X X X 2nd external device 5 1 0 0 0 1 0 1 0 0 1 X X X X 2nd matrix column 1 0 0 0 1 0 1 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 0 X X X X N U LL byte 0 0 0 0 0 0 0 0 0 1 0 1 0 0 key No. 21 pressed 0 0 0 0 0 0 0 0 0 0 X X X X 10 1 0 0 0 1 1 0 0 0 0 X X X X 2nd external device 1 0 0 0 1 1 0 0 0 1 X X X X 3rd matrix column 1 0 0 0 1 1 0 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 0 X X X X N U LL byte 0 0 0 0 0 0 0 0 0 1 0 0 0 1 key No. 27 pressed 15 0 0 0 0 0 0 0 0 0 0 X X X X 1 1 0 1 0 0 0 0 1 0 X X. X X 3rd external device 1 1 0 1 0 0 0 0 1 1 X X X X LC1) BAR No. 1 1 1 0 1 0 0 0 0 1 0 X X X X 1 0 0 0 1 1 1 0 0 0 X X X X 2nd external device 20 1 0 0 0 1 1 1 0 0 1 X X X X 4th matrix column 1 0 0 0 1 1 1 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 0 X X X X N U LL byte 0 0 0 0 0 0 0 0 0 1 0 0 0 0 No key pressed in this matrix column 0 0 0 0 0 0 0 0 0 0 X X X X 25 In this table X=Don't care states.

In Figure 10 the waveform diagram shows a key scanning sequence performed by an external device being interrupted bythe presence of a display control byte and then a display data byte on theW interface.

These bytes can only be introduced at the end of any two-byte key scanning operation, and not after a key control byte transfer, as the external device will then ignore the presence of the display byte. 30 As previously outlined the strobe signal KST can be de-activated during key scanning by connecting a resistor between the control pin KCL and the least significant key input pin K1 0. Figure 8 shows the connection of an LC1) display 30 to the interface. In this case the strobe signal KST is only active when display characters have been received from the signalling channel and are being placed on theW interface by the IDTC. Itwill be used to write characters into the display logic. 35

Claims

1. A digital telephone system comprising a code-decode circuit for connection to a telephone handset, and a digital telephone circuit, and wherein the digital telephone circuit includes an interface circuit comprising a multi-wire interface having both data lines and strobe lines for connection to peripheral circuits and a plurality of inputs to receive signals from the peripheral circuits. 40

2. A system as claimed in Claim 1 and comprising at least one additional bar display and at least one other peripheral circuit connected to the interface circuit via said data, strobe and input lines.

3. A system as claimed in Claim 2, wherein said peripheral circuits comprise a keybar circuit operative to extend the basic key scanning display driving mechanism of the digital telephone circuit.

4. A system as claimed in Claim 3, wherein said keybar circuit is an integrated CMOS gate array capable 45 of driving the bars of an LCID.

5. A system as claimed in any one of the preceding claims wherein said interface has 8 data channels and two strobe channels.

6. A system as claimed in Claim 5, wherein said inputs are operative to detect voltages developed in key matrices connected to the interface to recognised key depressions. 50

7. A digital telephone system substantially as described with reference to the accompanying drawings.

Printed for Her Majesty's Stationery Office by Courier Press, Leamington Spa. 1111987. Demand No. 8991685.

Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.