GB2189346A - Method and apparatus for erasing EPROM cell - Google Patents

Abstract

A method for erasing an EPROM cell where electrons on the floating gate 18 are excited by photons 28 generated in the substrate. A current is caused to flow through the source or drain region of sufficient magnitude to generate the photons by hot electron photoemission. The erasing method is relatively slow, but uses low voltages. <IMAGE>

Description

SPECIFICATION Method and apparatus for erasing eprom cell Background of invention 1. Field of the invention The invention relates to the field of metal-oxide-semiconductor (MOS), electrically programmable read-only memory (EPROM) cells having floating gates.

2. Prior art The most commonly used EPROM cell has an electrically floating gate which is completely surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate. In early versions of these cells, charge was injected through the insulation by avalanche injection such as in the device described in U.S. Patent No.3,660,819. Later versions of EPROMs relied on channel injection for charging the floating gate such as shown in U.S. Patent Nos.

4,142,926; 4,114,255 and 4,412,310. EPROMs are erased by exposing the array to ultraviolet radiation.

Electrically erasable EPROMs (EEPROM) are also commercially available. In some cases, charge is removed from a floating gate by tunnelling the charge through a thin oxide region into the substrate (see U.S. Patent No.4,203,158). In other instances, charge is removed through an upper electrode (see U.S. Patent No.4,099,196).

As will be seen, the present invention provides an erasable EPROM cell which is erased through the use of electromagnetic radiation, however, unlike prior art EPROM erasing, the radiation is generated within the device itself.

It has long been known that minority carriers are generated in MOS field-effect devices which are biased in deep saturation. This minority carriers can be collected at a reverse biased junction. The collection can be troublesome since, for instance, it can shorten the refresh time in a dynamic random-access memory cell. In the past, it was believed that the minority carriers were generated by secondary ionization from hot holes or from the injection of minority carriers from the source junction when currentflows to the substrate in a forward biased junction. More recently, it has been shown that the minority carriers are generated by photons. These photons in a typical MOS device emanate from hot electrons at the drain junction.

(See "SpaciallyResolved Observations of Visible-Light Emission from Si MOSFET's", IEEE Electronic Device Letters, Viol. Edl-4, No. 10, October 1983, beginning at p.386, and "Hot-Electron-lnduced Photon and Photocarrier Generation in Silicon MOSFET's", IEEE Transactions on Electronic Devices, Vol. Ed-31, No.9, September, 1984, beginning at p.1264.) The generation of these photons has been considered to be a detriment in the design of VLSI circuits. As will be seen these photons are harnessed in the present invention and used in the erasure of EPROM cells.

Summary of the invention A method and apparatus for erasing read-only memory devices which have a source and drain region disposed in a substrate and an electrically floating gate. In the preferred embodiment, electrons are removed from the floating gate by the application of a positive potential to the drain region while the control gate, source region and substrate are coupled to ground. The positive potential is applied to the drain region through a constant current source such as through a p-channel transistorforthe n-channel floating gate device described. The potential applied to the drain region is of sufficient magnitude to turn on the drain region causing a channel currentto flowthrough the substrate. The hot electrons generate photons which propagate to the floating gate (hot electron photoemission).These photons excite electrons in the floating gate causing them to be pulled from the floating gate into the substrate.

This erasing method is relatively slow, however, has the advantage of occurring at a lowvoltage.

Brief description of the drawings Figure 1 is a cross-sectional elevation view of a read-only memory device having a floating gate; this figure also illustrates the potentials used for erasing in accordance with the present invention and the erasing mechanism.

Figure2 is an electrical schematic showing a floating gate memory cell coupled in serieswith a constant current source.

Figure 3 is a graph showing a load line and several current-voltage curves associated with the erasing with the present invention.

Figure 4 is a band diagram showing various energy levels associated with erasing with the present invention.

Detailed description ofthe presentinvention An apparatus and method for erasing an electrically programmable read-only memory cell is described. In the following description, numerous specific details are set forth such as specific oxide thicknesses. Itwill beobvioustooneskilled inthe art, however, that the present invention may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail in order not to unnecessarily obscure the present invention.

The present invention describes a method for erasing an electrically programmable read-only (EPROM) memory cell, more specifically a cell having a floating gate. The method may be used on many existing cells, although the method can be optimized by using particular oxide thicknesses and through use of a cu rrent I imiter.

Atypical EPROM cell which may be used with the method of the present invention is shown in Figure 1.

For the preferred embodiment, the cell is fabricated on a p-type silicon substrate and includes spaced-apart n-type regions disposed in the substrate with a channel defined between the regions. Specifically, n+ drain region 12 and n+ source region 14 are shown in Figure 1. The memory device includes an electrically floating gate 18which is typicallyfabricated from polycrystalline silicon (polysilicon). This gate is completely surrounded by insulation such as silicon dioxide. With the method of the present invention, light must be transmitted from the substrate to the floating gate. Therefore, the insulation employed must transmit light. Silicon dioxide is suitable for this purpose. Acontrol gate 20 is disposed above and insulated from thefloating gate 18.This control gate is used for programming, that is, a programming potential (a positive potential) is applied to this gate during programming forthechannel injection of a charge (electrons) into the floating gate 18. Also, a reference potential is applied to this gate for sensing the state of the device.

A prior art cell which may be used with the invented method is described in more detail in U.S.

Patent No.4,412,310. However, to optimize the method of the present invention, shallow source and drain regions may be employed.

EPROM cells such as shown in Figure 1 are programmed by application of a positive potential to the control gate. Electrons from the channel are transferred to the floating gate and remain trapped there. These electrons raise the voltage threshold of the cell thereby providing a means of detecting a programmed device.

To erase a floating gate device with the present invention forthe n-channel device of Figure 1, the substrate 10, source region 14 and control gate 20 are coupled to ground as shown. A positive potential is applied to the drain region 12. This potential is preferably applied through a constant current source 16.The magnitude of this potential must be sufficient to cause a channel current (from the drain) to flow as shown by the arrow 24. (This potential is referred to AT VETO orthe drainturn-on voltage.) The required mangitude of this potential is a function of the parasitic coupling between the floating gate 18 and drain region as shown by the capacitor 22. In a typical cell with a silicon dioxide layer of 250A between the substrate and floating gate, a drain voltage of 10 volts is adequate. The potential applied to the drain region causes an electric field represented by the equal potential lines 26. These lines are more closely spaced in the silicon dioxide separating the floating gate 18from the substrate indicating a higher field gradient.The drain/channel current represented by the arrow 24 for a voltage of approximately 10 volts issufficienttocausethe generation of photons from the hot electrons (hot electron photoemission). These photons occur in a wide spectrum from infrared to ultraviolet. Some of the higher energy photons such as represented by arrow 28 propagate to the floating gate 18. There they excite the electrons stored on a charged floating gate. Some of these electrons become sufficiently excited thatthey are directed by the field represented by lines 26 into the drain region and substrate. This causes the floating gate 18to lose its negative charge thereby erasing the device.As this occurs, the memory device becomes more conductive and eventually currentwill flow from the drain region to the source region.

It has been found necessary to limit the current used to erase the memory device. A constant current source 16 is shown in Figure 1 coupling the positive potential to the drain region. In the currently preferredembodiment,the memorycellsare fabricated employing CMOS technology and a p-channel field-effect transistor 32 such as shown in Figure 2 is coupled in series with the n-channel EPROM ceIl 30 to provide current limiting. During the erasing of the EPROM cell 30 of Figure 2, the p-channel field-effecttransistor32 acts as a constant current source when a potential lower than Vpp is applied to its gate.Where a programming potential of 12. 5 volts is employed, as mentioned, a potential of approximately 10 volts is applied to the drain region ofthe device 30. Note in Figure2 as is the case in Figure 1, the control gate and source region of cell 30 are coupled to ground for erasing. Other current limiting means may be employed to limitthe drain current during erasing.

Referring to Figure3, a graph of drain current versus drain potential is shown. The curve 34 represents the current/voltage characteristics associated with the p-channel load device such as transistor 32 in Figure 2. The curve 40 represents the current/voltage characteristics associated with the drain junction when the floating gate is charged. The intersection of the curves 34 and 40 as shown by line 36 represents the drain potential needed to turn on the device through the constant current supply. As the electrons are stripped from the floating gate, the characteristic curve for the drain junction moves to the left as indicated by arrow 38. As can be seen, if a constant current source is not used,this current would dramatically increase and damage the EPROM cell.

The cell 30 of Figure 2 when used in an array is programmed and sensed in an ordinary manner.

That is, for instance, the control gate terminal ofthe device 30 is not coupled to ground but ratherto an appropriate potential for both programming and sensing. During non-erasing operation, the drain is coupled in an ordinary mannerto the EPROM array through line 31 and transistor 32 is deselected.

In the currrently preferred embodiment, a silicon dioxide layer of between 150A-250A is preferred between the floating gate and substrate. With a potential of approximately 10 volts applied to the drain region, erasing with the method of the present invention takes between one and ten seconds. For a thicker oxide (e.g., 350A) a longer time is required for erasing. While this erasing is relatively slow, the potential required to erase is substantially less than that required for prior art devices. For instance, where tunnelling is employed to erase the floating gate approximately 25-30volts is needed.

Figure 4 shows the energy associated with the transfer of electrons from the floating gate into the drain/substrate. The energy associated with the source region is shown by 1 4a, floating gate by 1 8a and drain region by 12a. The hot electron photoemission caused by the channel current excites the electrons, as mentioned, and provides sufficient energyforthem to overcome the energy barrier and be transferred into either the drain or substrate. The steep field gradient in the oxide shown by the lines 26 of Figure 1 is represented by the steep line 42 of Figure 4.

Thus, a method of erasing EPROM cells has been described where hot electron photoemission is used to excite electrons in the floating gate.

Claims (14)

1. In an electrically programmable read-only memory device having a source and drain region disposed in a substrate and an electrically floating gate, a method for removing charge stored in said floating gate comprising: causing a currentto flowthrough one of said source and drain regions of sufficient magnitude to generate photons which propagate to said floating gate thereby exciting said charge; and providing a path for said charge from said floating gate; whereby charge from said floating gate is removed.

2. In an electrically programmable read-only memory device having a source and drain region disposed in a substrate and an electrically programmable gate, a method for removing charge stored in said floating gate comprising: causing a currentto flowthrough said drain region of sufficient magnitude to generate photonswhich propagate to said floating gate thereby exciting said charge; providing a path for said charge from said floating gate; whereby said charge from said floating gate is removed.

3. In an electrically programmable read-only memory device having a source and drain region disposed in a substrate and an electrically floating gate, a method for removing electrons stored in said floating gate comprising: causing a currenttoflowthrough said drain region of sufficient magnitude to generate photonswhich propagate to said gate thereby exciting said electrons; providing an electrical field to direct said excited electrons from said floating gate to said drain region and substrate; whereby charge from said floating gate is removed.

4. In an electrically programmable read-only memory device having a source and drain region disposed in a substrate and an electrically floating gate, a method for removing electrons stored in said floating gate, comprising: applying a positive potential to said drain region of sufficientmagnitudeto produce hot electron photoemission such that photons propagate to said floating gate thereby exciting said electrons, said excited electrons being drawn to said drain region and substrate, whereby electrons from said floating gate are removed.

5. The method defined by Claim 4wherein said positive potential is applied to said drain region through a constant current source.

6. The method defined by Claim 5wherein said constant current source comprises a p-channel field effect transistor.

7. In an electrically programmable read-only memory device having a source and drain region disposed in a silicon substrate, a polysilicon floating gate completely surrounded with insulation, and a control gate insulated from and disposed above said floating gate, a method for removing electrons from said floating gate, comprising: coupling a positive potential to said drain region of sufficient magnitude to generate hot electron photoemission such that photons propagate to said floating gate, thereby exciting electrons on said floating gatecausing the electronsto passthrough said insulation to said drain region and substrate thereby discharging said floating gate.

8. The method defined in Claim 7 wherein said positive potential is applied to said drain region through a constant current source.

9. The method defined by Claim 7 wherein said substrate, source region and control gate are coupled to ground.

10. In an electrically programmable read-only memory device having a source and drain region disposed in a silicon substrate, a polysilicon electrically floating gate insulated from said substrate by a silicon dioxide layer and a floating gate disposed above and insulated from said floating gate, a method for removing electrons from said floating gate comprising the step of: coupling a positive potential to said drain region of sufficient magnitude to generate photons which propagate to said floating gate thereby exciting said electrons, said electrons passing through said silicon dioxide layer into said substratethemby discharging said floating gate.

11. The method defined by Claim 10 wherein said substrate, source region and control gate are coupled to ground.

12. The method defined by Claim 11 wherein said positive potential is coupled to said drain region through a constant current source.

13. The method defined by Claim 12 wherein said constant current source comprises a p-channel transistor.

14. A method for removing charge stored in a floating gate in an electrically programmable read-only memory device having a source and drain region disposed in a substrate and an electrically floating gate substantially as hereinbefore described with reference to the accompanying drawings.