GB2188211A - Semiconductor switch array - Google Patents

Abstract

A semiconductor switch array includes two sets of co-ordinates (1, 2), made from respective layers of metal separated by a substrate of insulating material. At each intersection there is a decode and latch circuit (3) which controls a set of gates for its intersection. In the arrangement shown there are 24 lines in each of the buses, so each such set of gates consists of 24 similar gates which are controlled together. To set up a connection between a bus in one co-ordinate and a bus in the other co-ordinate, a coded signal is applied to lines of one of these buses and this is offered to all decode and latch circuits of that bus. One of these circuits recognises that it is the "wanted" circuit, and responds to close its set of gates to complete the required bus connection. With such an arrangement two or more buses in one direction can be connected to the same bus in the other direction. <IMAGE>

Description

SPECIFICATION Semiconductor switch array The present invention relates to a semiconductor switch array, designed for use in conjunction with a high speed floating-point signal processor, although it has other applications.

According to the present invention, there is provided a sem iconductor switch array, which includesafirstsetofgenerallyparallel multi-conductor buses extending in a first direction so as to form a first co-ordinate of the array, a second set of generally parallel multi-conductor buses extending in a second direction so as to form a second co-ordinate of the array, an insulating substrate between said sets of buses, a set of gates at each intersection between a bus of the first set and a bus of the second set, a set of decode and latch circuits each associated with one of said bus intersections, coded connections from the buses of one of said sets to the decode and latch circuits such that said circuits are controlled via one of said sets of buses, and output connections from each said decode and latch circuit to the gates of that circuit's bus intersection, wherein to set up a connection via the array a first signal is applied to all decode and latch circuits to switch them off, so that all connections through the array are disabled, wherein after said first signal has been applied signals are applied to the appropriate bus lines of said one set to cause the desired interconnection, whereafterthe decode and latch circuit for the desired interconnection responds to close the gates appropriate to that interconnection via the output connections from the said decode and latch circuit.

An embodiment ofthe invention will now be described with reference to the accompanying drawings, in which Figure 1 shows the general arrangement of a switch array embodying the invention.

Figure2showson largerscalethan Figure 1,the arrangements for the control of interconnections through an array such as that shown in Figure 1.

Figure 3 is a schematic representation of one ofthe decode and latch circuits of Figure 2.

Figure4is a timing diagram, useful in explaining the operation ofthe switch array.

The switch array to be described herein is an electronic analogue ofthe well-known electro-mechanical cross-bar switch, and was designed for use as part ofthe single chip processing arrangement described in our co-pending Application No. 86 06587 (C.R. Ward et al 10-2-1).

However, it has many other applications, and could in fact be implemented on chip on its own.

Figure 1 shows a 15 x 15 co-ordinate array in which fifteen 24 bit input buses such as 1 extend vertically, while fifteen 24 bit output buses such as 2 extend horizontally. The input buses 1 are formed from one layer of metal while the output buses 2 shown in dashed lines, are formed from another layer of metal. These two layers are separated bythe insulating substrate ofthe chip, and at the intersections between the buses there are decode and latch circuit units such as 3.

A set of four lines clock, ground, power and latch run in between the buses 1, in Figure 1, and supply the decode and latch circuit units.

Figure 2 shows the intersections between two 24 bit input buses 5 and 6, and two 24 bit output buses 7 and 8. In the gap in the middle of these four intersections there are four decode and latch circuits 9,10,11,12, one for each intersection. These circuits have controlling inputs consisting of a ground connection 13, a power connection 14, a clock connection 15 and a latch line 16. These connections, which were mentioned above, extend parallel to, and in the same plane as, the input buses.

Each decode and latch circuit is connected by a set of connections indicated schematically by broken lines such as 16 to its input-output interconnections so that it can control the interbus gates (not shown).

These gates are provided at each intersection between an input bus line and an output bus line to set up connections through the switch. The decode and latch circuit is also connected by a group of connections such as 17 to a selection ofthe lines of the output bus associated with its input bus-output bus intersection. It is over these connections thatthe decode and latch circuit receives the address of an input bus to which the output bus is connected.

Each gate between an input data line and an output data line is of the type shown in Figure 3. Here we have a gate 20, with five inputs, four ofwhich are connected as shown in Figure 2 to four ofthe lines of an output bus. The fifth of these inputs is connected to the latch line (16, Figure 2) forthe column ofthe matrix which includes the decode and latch circuit.

The output ofthe gate 20 goes to one side of a latch formed by two cross-coupled gates 21 and 22, whose outputs go to two inverters 23 and 24 respectively.

The outputs of these inverters go to an N-type device 25 and a P-type device 26 associated with a cross-point between an input data line and an output data line.

The operations which occurwhen an input-output connection is to be set up will now be described with reference to the timing diagram shown in Figure 4.

When the main system clock CLK goes high, the clock CLK' strobes the decoders, each of which is part of a decode and latch circuit. This clock acts on the gate 22, Figure 3, of each decode and latch circuit.

It tu rns all the switches off, leaving all input and output buses disconnected with the output buses floating. Eight bits of each output bus are then fed with the appropriate connection address for each bus. When the system clock goes low again, the latch line strobes these addresses into the gates for the appropriate decode circuits, Figure 3. Then the gate 20forthe decode and latch appropriate to the required connection responds to switch the latch 21-22, which establishes the connection between the appropriate input data line and output data line.

Itshould be borne in mind that when the above operations take place, twenty four connections are actually set up. This is because each input-output connection is a connection between a twenty-four line input bus and a twenty-four line output bus.

Output buses are used to convey the decoder information so that more than one destination can be connected, if required, to one source bus.

Claims (7)

1. A semiconductor switch array, which includes afirstsetofgenerally parallel multi-conductor buses extending in a first direction so astoform afirst co-ordinate ofthe array, a second set of generally parallel multi-conductor buses extending in a second direction so as to form a second co-ordinate ofthe array, an insulating substrate between said sets of buses, a set of gates at each intersection between a bus of the first set and a bus ofthe second set, a set of decode and latch circuits each associated with one of said bus intersections, coded connections from the buses of one of said sets to the decode and latch circuits such that said circuits are controiled via one of said sets of buses, and output connections from each said decode and latch circuit to the gates of that circuit's bus intersection, wherein to set up a connection via the array a first signal is applied to all decode and latch circuits to switch them off, so that all connections through the array are disabled, wherein after said first signal has been applied signals are applied to the appropriate bus lines of said one set to cause the desired interconnection, whereafterthe decode and latch circuit for the desired interconnection responds to close the gates appropriate to that interconnection via the output connections from the said decode and latch circuit.

2. An array as claimed in claim 1,wherein each said decode and latch circuit includes a bistable latch which is reset to its off state by a said first signal, a gate connected to the appropriate ones of said bus lines, which gate, if it is atthe decode and latch circu it to be operated, responds to the coded signals on said bus lines to cause the gate to give an output, a connection from that gate to said bistable latch via which an output from said gate operates that latch to its set condition, and output means responsive to the setting of said latch to its condition to close the inter-bus gates at the appropriate intersection.

3. An array as claimed in claim 1 or2, and wherein two or more buses in one said co-ordinate can be simultaneously connected to the same bus in the other said co-ordinate.

4. An array as claimed in claim 1,2 or 3, wherein the multi-conductor buses of one said set are formed from one layer of metal whilethe multi-conductor buses ofthe second set are formed from another layer of metal, and wherein the two layers of metal are separated by a substrate of an insulating material.

5. An array as claimed in claim 4, and wherein the decode and latch circuits are located on the insulating substrate on regions thereofsurrounded bythe multi-conductor buses.

6. An array as claimed in claim 4 or 5, wherein additional conductors such as a power supply line, a ground line, a clock line and a latch control line are formed from one of said layers of metal and are located between the buses ofthe set of buses also formed from that layer.

7. A semiconductor switch array, substantially as described with reference to the accompanying drawings.