GB2183367A - Timer for appliances - Google Patents

Abstract

A timer has a frequency standard 10 and divider 11 to provide a clock signal of one pulse per minute. The clock pulses are counted by counter 12 which resets every 24 hours. The output of the counter 12 is supplied to two ON registers 14, 16 and two OFF registers 15, 17. The current count of the counter 12 is transferred to any one of the registers 14-17 by operation of its respective switch 22-25. Each comparator 18-21 receives the output of the counter 12 and of the associated register and produces an output on identity. The outputs of the comparators 18-21 are used as ON or OFF signals. These outputs are gated by circuit 26 having controls to select ONCE or TWICE per day. A switch advance circuit 27 is provided to advance the output of the output gating circuit 26 to the next stage and a start time offset circuit 28 is connected to the ON comparators 18, 20 to provide an addition to the output of the register connected to each of those comparators. <IMAGE>

Description

SPECIFICATION Timer for appliances This invention relates to timers and it is an object of this invention to provide a relativelysimpletimer.

Such a timer may be suitable for appliances of domestic heating control.

According to this invention there is provided a timercomprising a clocksource,a counterarranged to count the clock pulses and to be reset every 24 hours, and switch means connected to the counter so thatthe counter will produce an ON signal every 24 hours subsequent to a first actuation of the switch means and an OFF signal every 24 hours subsequent to a second actuation of the switch means.

In recent years there has been a proliferation of timers in the house and in industry. In particular digital electronic timers are now used because of their reliability, accuracy and flexibility. All available timers are fitted with a time of day display which may be hands, a mechanical dial ora digital display.

However in many cases, where a timer is intended to repeat a cycle of ON and OFF daily, the time of day display is superfluous. The timer according to this invention need not have a time of day display but can be used to provide a repeating daily programme. If the timer does not include a time of day display, it can be manufactured very ecoriomically.

Afirstpreferredembodimentcomprisesfirstand second registers connected to the counter, said switch means comprising first and second switches connected to the first and second registers respectively, actuation of each ofthe first and second switches causing the count of the respective register to be updated to that of the counter, and first and second comparators, the first comparator being connected to receive the outputs of the counter and the first registerandthe second comparator being connected to receive the outputs of the second register and the counter.

In use, the output of the first comparator is an ON signal and the output of the second comparator is an OFF signal.

Preferably there is provided an offset circuit connected to the first comparatorfor adding to the count of the first register a particular count before comparison is carried out.

Preferably there are provided third and fourth registers connected to receive the output of the counter, said switch means comprising third and fourth switches connected to the third and fourth registers respectively, actuation of the third switch causing the count of the third registerto be updated to that of the counter and actuation ofthefourth switch causing the count ofthe fourth register to be updated to that of the counter, and third and fourth comparators, the third comparator being arranged to receive the output of the counter and the third register and the fourth comparator being arranged to receive the output of the counter and the fourth registers The output of the third comparator is an ON signal and thatofthefourth comparator is an OFFsignal.

Preferably, the offset circuit is also connected to the third comparatorfor adding to the count ofthe third register said particular count before comparison is carried out.

Preferably, the outputs ofthefirst, second,third and fourth comparators are connected to a gating circuit.

Preferably, an advance circuit is also connected to the gating circuit and on actuation switches the output ofthe gating circuit to the state it is notin.

In another embodiment of the invention,said counter comprises first and second counter units arranged to count the clock pulses, and to be reset every 24 hours, and wherein said switch means comprises first and second switch units for resetting the first and second counter units respectively.

The output of the first counter unit may be used as an ON signal and the output of the second counter unit may be used as an OFFsignal.

Preferably, the timer comprises an offset circuit which comprises means for increasing the count of the first counter unit buy a particularvalue.

Preferably, the counter comprises third and fourth counterunits, arranged to countthe clock pulses and to be reset every 24 hours and the switch means comprises third and fourth switch units for resetting the third and fourth counter units respectively.

Again the outputofthethird counter unit is used as an ON signal and the output of the fourth counter unit is used as an OFF signal.

Preferably, the output of the offset circuit is also connected to the third counterunitforincreasing its count by said particularvalue.

In one arrangement, a reset circuit is provided for each counter unit and comprises a registerinwhich is stored a value corresponding to 24 hours atthe clock pulse rate and a comparatorarrangedto compare the output of the associated counter unit and register and to reset the associated counter unit when the counts are equal.

In an alternative arrangement, each counter unit has a capacity at the clock pulse rate such that itfills up completely in exactly 24 hours.

In one timer in accordance with this invention, the first counter unit is divided into first and second subcounter units, the total number of bits of which are such that the counter unit fills up in exactly 24 hours and the output ofthefirstsubcounterunit is connected to the clock input of the second subcounter unitth rough an inverter.

Thethird counter unit mayalso be of a similar construction.

In anothertimer in accordance with this invention, the counter comprises a first counter unit having a first period and connected to receivetheclock pulses and a second counter unit having a second period, the output ofthe first counter unit being connected to the input of the second counter unit, the switching means being connected to initiatethefirst counter unit and to reset the second counter unit, the output of the second counter unit being connected to initiate the first counter unit, the output of either of the first and second counter units being used to control the ouput. The periods ofthefirst and second counter units added together may be equal to 24 hours.

In yet another alternative arrangement in accordance with this invention, said counter comprises first and second counter units ofwhich the second counter unit has a period equal to 24 hours and which both receive the clock pulses, the output of the first counter unit being used as an output ofthe timer, the switch means being arranged to reset the first and second counter units, the output of the second counter unit being arranged to reset thefirstcounterunit.

Timers in accordance with this invention will now be described, by way of example only, with reference to the accompanying drawings of which Figure lisa block diagram of a firsttimerin accordance with this invention; Figure2 is a view of a control panel of the first timer; Figure 3 is a timing circuit showing alternative timing cycles for the timer shown in Figure 1; Figure 4 is an alternative control panel forthe controltimerasshown in Figure 1; Figures5, 6, 7A and 8A are block diagrams of second, third. fourth and fifth timers in accordance with this invention: Figures 7Band8Baretiming diagrams ofthe fourth and fifth timers respectively; and Figures 9 10, 1 lA and 7 are flow diagrams of a microprocessorform ofthe first timer.

Referring to Figure 1, a frequency standard oscillator, which may be a mains electricity supply oscillatorora crystal oscillator, produces an output at 50Hz which is divided by a divider 11 by a factor of 3,000 to provide a clock signal at 1 per minute. This clock signal is supplied to the clock input of an eleven bit counter 12, reset once every 24 hours by reset circuit 13. The reset circuit 13 comprises an eleven bit register having within it a count of 1440, and a comparator. The comparator within the reset circuit 13 compares the output of the eleven bit counter 12 and the associated register and produces a reset signal once every 24 hours; the reset signal is applied to the reset input of the eleven bit counter 12.

The output of the eleven bit counter 12 is supplied in parallel to four comparators 18 to 21 respectively, each associated with a respective one ofthe eleven bit registers 14to 17. Each comparator compares the output of its associated register and the current output ofthe eleven bit counter 12. Switches 22 to 25 are connected to the load inputs of the registers 14to 17 respectively.

In use, on actuation of any ofthe switches 22 to 25 the current output of the eleven bit counter 12 is loaded into the associated eleven bit register. For example, on actuation of the switch 22, the current output of the eleven bit counter 12 is loaded into the eleven bit register 14. Each of the comparators 1 8to 21 produces an output when its two inputs coincide, the outputs of the comparators 22 and 24 being used as ON signals and those of the comparators 23 and 25 being used as OFF signals.

In use, it will be seen that when, for example, at any time of day the switch 22 is operated, then 24 hours later the comparator 18 will produce an ON signal.

The outputs of the comparators 18 to 21 are connected to an output gating circuit 26 used to control a load, for example, a heating load and the output gating circuit may be actuated to have a single cycle or two cycles per day by means of internal circuitry; the controls are denoted ONCE and TWICE. A switch 27 connected to the output gating circuit provides an advance overridefacilitywhich can be used to switch the output to the next stage, i.e.

ifthe output is then on itwill be switched off and if off it will then be switched on. Atime offset can be subtracted or added to the eleven bit data which is applied to the comparator by the registers 14 and 16.

For this purpose a start time offset circuit 28 is connected to the comparators 18 and 20.

Figure 2 shows a typical front panel layout of an appliance timer. This panel can consist of a membrane switch panel, a discrete switch panel or any other switch input system. In thetimershown, the registers 12to 15 are designated A, B, Cand D respectively and the switches 22 to 25 are so labelled as can be seen from Figure 2. The advance switch 29 is labelled E and the output indicator lamp 30 is included to show the state of the unit.

The following description assumes that the timer of Figure 1 and Figure 2 will be used to control a domestic central heating system.

When the timer is switched ON the output will be OFF and will remain OFFunlesscertain buttons are pressed. Pressing the ADVANCE button 27 once will cause the output to switch ON. Pressing again will cause the output to switch OFF. The ADVANCE button can be used at anytimeto change the state of the output.

To set the timer, switch 22 is pressed when heating is first required in the morning (e.g. 7.00 a.m.) so that register 14 is loaded to the current count of counter 12 and so that comparator 18 produces an ON output. Switch 23 is pressed when heating is no longer required (e.g. 8.30 a.m.) so that register 15 is loaded to the current count of counter 12 and so that comparator 19 produces an OFF output. Similarly switches 24 and 25 will be pressed for heating in the afternoon/evening (e.g.3.30 p.m - 10.00 p.m).

Thereafter, each day the heating will turn ON and OFF atthese times automatically (provided no offset has been included). If at anytime it is necessaryto reset one ofthe times to a new value the appropriate switch just has to be pressed atthe newtimeofday.

This new time will be stored and used for switching on subsequent days.

For a heating system it may be inconvenient to be present in the house at the switch on time required.

Forexamplewhen getting up in the morning at7.00 a.m. it is preferable thatthe house is already warm.

To caterforthis an offset time can be preset into the control, for example, for one hour. When setting the timer,switch 22 may be pressedat7.00a.m.when getting up in the morning, but on subsequent days the heating will come on earlier, by the amount of the offset; i.e. in the example, the heating will come on at 6.00 a.m. Similarly in the afternoon the heating will come on at 2.30 p.m.

With this system the output of the offset circuit 30 is added to (or subtracted from) the output of the eleven bit register 14 and the eleven bit register 16 within the comparators 18 and 20 respectively.

Figure 3 shows the output of the output gating circuit 26 and it will be seen that the output gating circuit 26 can produce output drive signals which are any combination ofthecomparatoroutputsignals.

The most useful signals for use in heating an appliance applications are once ortwice per day signals. The output signals shown in Figure 3 in a graphical manner could be used to drive relays, triacs or other power switching devices connected to the load.

As described abovethetimerwould be suitable for control of a house central heating system probably at the boileror other heatsource. Figure 4 showsthe same timer which is suitable for controlling a zone of a heating system which could be a room, a group of rooms or a hot water cylinder(with modified temperature range). As shown in Figure 4, a thermostate is incorporated to enable the temperature of the zone to be controlled whilst the timer is on.

When temperature control is incorporated,the offset at switch ON (or switch OFF) can become variable and dependent on the actual temperature of the room (orcylinder) and the required temperature at the time set by the switches. Thus if the room is still warm just prior to the time set by the switches, the heating on time will be delayed until it isjust possible to reach the required control temperature bythetime set bythe switches. This optimising system ensures that the heating is not switched on prematurely which would be wasteful of energy.

The timer shown in Figure 1 can readily be produced using discrete logic circuits but could in fact be a specially programmed microprocessoras described laterwith reference to Figures 8 to 11.

The timer so far described has been suitable for heating applications in particular for heating boilers, central heating systems, zone control, room control, hot water cylinder and individual radiatorcontrol.

Otherfeaturescan be included intothetimerwhich although more suited to other applications may be also used for domestic heating.

Each pair of O N and OFF buttons can be replaced by a single button which can be used to set both ON and OFF times. If the output in OFF, pressing the button will switch it ON and store an ON time.

Similarly, if the output is ON pressing the button will switch it OFF and store an OFFtime. Although this operation is slightly more complex it reduces the number of buttons required to set the timer.

Some applications require only one timed output period, simplifying the timer. This control would be most useful for automatic lightcontrols such as porch lights, car park lights, security lighting, child's safety bedroom lights etc.

The number of timed periods can be extended by the inclusion of further switch inputs. The circuitry will become correspondingly more complex (or greater storage capacity will be required in a microprocessor).

The control can be extended to.include a DAY counter following the eleven bit counter of Figure 1.

Also eleven bit registers 14to 17 are included for each day of the week. The operation is similarto the description of Figure 1 except that the setting buttons have to be pressed on EACH day of the first week of operation. Thereafter the timer will repeat the WEEKLY cycle as set up. If no programme is set for any particular day that day will have no output at all.

This timerwill be most useful in commercial heating orairconditioning applications (e.g.

factories, offices, shops, surgeries etc.). In these applications temperatures need to be closely controlled during working hours, so that temperature and optimiser controls as described above would probably be used.

In certain heating applications a single timed programme repeated each day is sufficient; however it is an advantage to be able to omit days in the programme (e.g. weekends in offices orfactories). In this case a seven day counter is included as explained above and an extra button marked "START OMIT" is provided.

The timer programme is set up as explained above. For example, if it is necessary to omit Saturday or Sunday, then the START OMIT button will be pressed on Friday evening. The heating will then be switched OFF. On Monday morning button 14 (ON) is pressed to revert back to normal operation. The control stores the omitted days and repeats the patternforfollowing weeks.

For critical applications, a battery back-up will be provided to ensure that the programmes set are not lost during mains failures.

Figure 5 shows the second timer in accordance with this invention, which second timer has a somewhat simplified method of operation in comparison to that of Figure 1. In this embodiment, the frequency standard 10 and the frequency divider 11 are provided as in Figure 1 but the clock signal output ofthe frequency divider 11 is applied directly to the clock input of each ofthe eleven bit counters 14 to 17 and no intermediate eleven bit counter is provided. However, a 24 hours reset circuit is provided for each of the eleven bitcounters 14to 17 and these are designated at 30 to 33 respectively.

Each ofthese reset circuits comprises an eleven bit registerhaving within it the numberl ,440, and a comparatorwhose inputs are connected to the associated eleven bit counter and eleven bit register and whose output is connected to the reset input of the associated eleven bit counter. As before, a switch is connected to each eleven bit counter, the switches being designated at 22 to 25 respectively. When any of the switches 22 to 25 is operated, its associated counter is reset. Thus, if the switch 22 is operated, eleven bit counter 14 is reset and begins to count again. The eleven bit counter 14 will thereafter be reset every24 hours and the output of the reset circuit 30 is used as an ON output. In like manner, the output ofthe reset circuit 32 not only resets the eleven bit counter 16 but is also used as an ON output and similarly the outputs of the reset circuits 31 and 33 are used to reset the eleven bit counters 15 and 17 respectivelyand are also used as OFF outputs. As before the ON and OFF signals are gated by the output gating circuit 26 to which an advance switch 27 is connected. The output gating circuit 26 may be as that of the timer of Figure 1 .A starttime offset circuit is provided, this being designated at34 and is connected to the eleven bit counters 14 and 16.

In this arrangement, on operation of the start time offset circuit 34 an initial count is loaded into the eleven bit counters 14 and 16. Thus in each subsequent 24 hours the ON outputs will be provided at a time selected by the offset circuit before the time selected by the switches 22 and 24.

Athird timer in accordance with this invention is shown in Figure 6 and makes use of a frequency standard crystal oscillator 40 which operates at the industry standard frequency of 32.768 kHz. The output of the frequency standard 10 is divided bya divider 41 having a division ratio of 345600 producing a clock signal once every 10.546875 seconds. The significance of 10.546875 is that a count of 213 corresponds to 24 hours.

As in the embodiment of Figure 5 there are four counters, two to provide ON-times and two to provide OFF-times, In principle the timer of Figure 6 works in the manner of that of Figure 5 but has different offset arrangements. Those components common with Figure 5will not be described again.

The two ON counters are of more complex construction than the two OFF counters. All four counters receive the clock pulses in parallel.

Considering the ON counter shown at the left of Figure 6, the clock pulses are received by the clock bit of an N-bit ripple counter 50 whose output is sent through an inverter 51 to the clock input of a 13-N-bit ripple counter 52. A switch 53 is provided for resetting both counters 50 and 52. The overflow output of the counter 52 is used as the ON signal.

The clock pulses are also received by a 13 bit ripple counter54which acts as an OFF counterand has a switch 55 connected to its reset output. The overflow signal of the counter 54 is used as an OFF signal. The second ON counter circuit is similar to that described and consists of an N-bit ripple counter, an inverter circuit 57, and 13-N-bit ripple counter 58 and a switch 59. Further, the second OFF counter circuit comprises a 13 bit ripple counter 60 and a switch 61 connected in a manner similarto the counter 54 and the switch 55.

The operation of the circuit shown in Figure 6 will be described ignoring the existence of inverters 51 and 57. At whatever time of day switch 53 is operated, the counters 50 and 52 will be reset. In the subsequent 24 hours, the counter 52 will fill up completely because the number of bits of the counters 50 and 52 together is 13 so that 24 hours later an ON signal is provided. In like manner, an ON signal is provided every 24 hours afterthe switch 59 is operated and OFF signals will be provided every 24 hours afterthe switches 55 and 61 are operated. The effect of the inverter 51 is to provide an offset signal equaltothetimerequiredforthecounter50tocount up once.This is because the inverter 51 effectively switches the bit counter 52 once on startup so eliminating the time required for the N-bit ripple counter 50 to count up once. This similarly applies two the effect of the inverter 57. It will be appreciated that the offset provided in this manner is equal to 10.546875 x 10N seconds.

Obviously the crystal frequency can vary in the embodiment of Figure 6 and the same advantage - obtained.

Thetimershown in Figure 1 can be implemented in ordinary discrete logic circuitry or with a custom chip but is somewhat complex in thatform but can be implemented readily with a microprocessor program.

The timer shown in Figure 5 is equally straight forward in microprocessorprogramsform and can also be readily achieved in discrete logic circuitry' or as a custom chip.

Thetimershown in Figure 6 is particularly easyto provide in the form of discrete logic circuitry ora custom chip. The timer shown in Figure 6 could be produced using a microprocessor program but would not effectively utilise the power of microprocessor.

The fourth timer is simplified so that the whole system can be set by one button which will give a time reference for the beginning of a sequence. As shown in Figure 7A, there is provided a frequency standard 10 and a frequency divider 11 as in Figure 1 to provide an output clock signal at the rate of one per minute. This.clock signal is used to generate two sequential time delays designated A and B and the total time delay A + B is 24 hours. Forthis purpose the time delay circuit 50 having the period A receives the clock signal output of the divider 11 at its clock input and its output is supplied to the initiation input of a time delay circuit 51 having the period, both circuits 50 and 51 being counters.When a setting switch 52 is operated it initiates time delay circuit 50 and resets time delay circuit 51,the output of time delay circuit 51 also being connected to the initiation input ofthetime delay circuit 50. In use, on operation ofthe switch 52, the time delay circuit 50 counts for the period A and during this entire period the output is ON for which purposethetime delay circuit 50 is connected to the output drive circuit 53. On completion of its count, the time delay circuit 50 then initiates the time delay circuit 51 which then counts the time delay period B.At the end of that period the time delay circuit 51 reinitiates the time delay circuit 50 and astime delaysAand Baddupto24hours, time delaycircuitA maintains the output drive circuit 53 ON forthe time period A once every 24 hours beginning at the same time every 24 hours. This is illustrated in Figure 7B where the upper graph illustrates the ON period which is the output ofthe time delay circuit 50 and the lower graph illustrates the output ofthe time delay circuit 51. It will be appreciated thatthere could be a considerable number of time delay circuits 50 and 51 all connected in series buttheirtotal time delays must add up to 24 hours.

Referring now to Figure 8A, the fifth timer is somewhatsimilarto that of Figure 7A, the time delay circuits 60 and 61 being connected in parallel instead of in series. As in the embodiments of Figures 1,5 and 7A, the frequency standard 10 and the frequency divider 11 are provided to produce an output clock signal at the rate of one pulse per minute. This clock signal is provided to the clock inputs of both time delay circuits 60 ad 61, time dealy circuit 60 being arranged to drive the output circuit 63. Time delay circuit 60 has a variable period A which is the ON time. Time delay circuit 61 which has a 24 hour period has its output connected to the initiation input of the time delay circuit 60. A setting switch 62 is connected to initiation circuits of time delay circuits 60 and 61.The operation of the circuits shown in Figure 8A is as illustrated in Figure8B and it will be appreciated that on operation ofthe setting switch 60, the time delay circuit 60 begins counting up during which period the output drive signal 63 is in its ON state. When the time delaycircuit 50 completes its ON period, the output drive circuit 63 is cut off, that is at the end of the period A as illustrated in Figure8B.Time delaycircuit61 countsfor24 hours and reinitiates the cycle.

What is common to all the timers which have been illustrated in that no time of day display is provided but nevertheless a programme capable of daily repetition is provided. In fact, the programme may not be repeated every day and there may be more than one programme, a repeating daily programme is available.

Figures 9,10,1 1A and 11 Bshowflowdiagrams of a microprocessorform ofthefirsttimershown in Figure 1. Figures 9 to 11 are virtually self explanatory, Figure 9 being the main flow diagram ofthe microprocessor controller. As Figure 9 is virtually self explanatory no detailed description will be given. It will be appreciated that at the output of the clock stage 72 a pulse will appearonce per minute. It is further pointed outthatthe stage 77entitled "TIME CONTROLTEST" is shown in detail in Figure 10 which, in turn, is also clearly self explanatory.It will be appreciated that the combined function of stages 86,87,88 and 89 is to perform the function ofthe output gating circuit 26 shown in Figure 1 and selects either "ONCE" or "TWICE", i.e. selects either one operation per day ortwo operations perday. twill be appreciated that stages 79 and 80turn the output off and on respectively in accordance with whether ornotthe output condition flag is OFF and ON respectively and the condition ofthe output condition flag is itself set by the TIMED CONTROL TEST stage 77, shown in detail in Figure 10.

Figures 1 A and 118 are together one flow diagram and show a flow chart which is executed when an interrupt is generated as a result of a key being operated. As explanation ofthis flow chart is mentioned there area numberofkeyswhich can be operated. Specifically, there is an advance key corresponding to the advance switch 27 shown in Figure 5. There is also a BSTkeywhich,when operated when the system is in British Standard Time adds one hour to the clock time andwhen operated, when the system is in summertime,takes awayone hourfrom the clocktime.A standbykeyis provided which when operated turns OFF the output and similarly an ON key is provided which,when operated, turns ON the output. As already mentioned, there are "ONCE" and "TWICE" keys to perform the function of the corresponding switches on the output gating circuit 26. Further, an "OFF" key is provided. It will be appreciated that on operation of the "ON" key the system is turned ON and simultaneously the memory records that time.

Likewise when the OFF key is operated, the output is turned off and the memory memorisesthattime.

Finally, an "offset" key is provided to provide a function similar to that of the start time offset circuit 34 of Figure 1. The difference between the standby key and the OFF key is that when the standby key is operated the output isturned off until an ON key is operated whereas when the "OFF" key is operated the system is turned off and the time is memorised by the memory but the output isturned on at the next "ON" time.

Claims (21)

1. Atimercomprising a clocksource.a counter arranged to count the clock pulses and to be reset every 24 hours, and switch means connected to the counter so that the cou nter will produce an ON signal every 24 hours subsequent to a first actuation of the switch means and an OFF signal every 24 hours subsequent to a second actuation of the switch means.

2. A timer according to claim 1 which comprises first and second registers connected to the counter, said switch means comprising first and second switches connected to the first and second registers respectively, actuation of each of the first and second switches causing the count of the respective register to be updated tothatofthe counter, and firstand second comparators, the first comparator being connected to receive the outputs of the counter and the first register and the second comparator being connected to receive the outputs of the second register and the counter.

3. Atimeraccording to claim 2 which comprises an offset circuit connected to the fi rst com pa rator for adding to the count ofthefirst register a particular count before comparison is carried out.

4. Atimer according to claim 2 orclaim 3which comprises third and fourth registers connected to receive the output of the counter, said switch means comprising third and fourth switches connected to the third and fourth registers respectively, actuation ofthethird switch causing the count ofthethird register to be updated to that of the counter and actuation of the fourth switch causing the count of thefourth register to be updated to that of the counter, and third and fourth comparators,thethird comparator being arranged to receive the output of the counter and the third register and the fourth comparator being arranged to receive the output of the counter and the fourth register.

5. Atimer according to claim 4 as appendantto claim 3, wherein the offset circuit is also connected to the third comparatorforadding to the countofthe third register, said particular count before comparison is carried out.

6. Atimeraccordingtoclaim3orclaim Swherein said particular count is temperature dependent.

7. Atimeraccordingto claim4whereinthe outputs of thefirst, second,third and fourth comparators are connected to a gating circuit.

8. Atimeraccordingto claim4whereinthe gating circuit is operable to select the outputs ofall the comparators or ofthe first and fourth comparators.

9. Atimeraccording to claim 7 or claim 8 wherein an advance circuit is also connected to the gating circuit and on actuation switches the output of the gatingcircuittothestateitis notin.

10. Atimeraccordingto claim 1,wherein said counter comprises first and second counter units arranged to count the clock pulses, and to be reset every 24 hours, and wherein said switch means comprises first and second switch units for resetting the first and second counter units respectively.

11. Atimeraccording to claim l0whereinthe timer comprises an offset circuit which comprises means for increasing the count of the first counter unitbya particularvalue.

12. Atimeraccordingto claim 10 or claim 11 wherein the counter comprises third and fourth counter units arranged to count the clock pulses to be reset every 24 hours and the switch means comprises third and fourth switch units for resetting the third and fourth counter units respectively.

13. Atimeraccording to claim 11 or claim 12as appendentto claim 11 wherein the outputofthe offset circuit is also connected to the third counter unitforincreasing its count bysaid particularvalue.

14. Atimeraccording to any of claims 1 to 13 wherein a reset circuit is provided for each counter unit and comprises a register in which is stored a value corresponding to 24 hours at the clock pulse rate and a comparator arranged to compare the output of the associated counter unit and register and to reset the associated counter unit when the counts are equal.

15. Atimeraccording to anyofclaims 10 to 13 wherein each counter unit has a capacity at the clock pulse rate such that it fills up completely in exactly 24 hours.

16. A timer according to claim 10 wherein the first counter unit is divided into first and second subcounter units, the total number of bits of which are such that the counter unit fills up in exactly 24 hours and the output of the first subcounter unit is connected to the clock input of the second subcounter unit through an inverter.

17. Atimer according to claim 12 wherein the counter unit is divided into first and second subcounter units, the total number of bits ofwhich are such thatthe counter unit fills up in exactly 24 hours and the output of the first subcounter unit is connected to the clock input ofthe second subcounter unitthrough an inverter.

18. Atimeraccording to any of claim 2 to 17 which comprises a microprocessor.

19. Atimeraccordingto claim 1 whereinthe counter comprises a first counter unit having a first period and connected to receive the clock pulses and a second counter unit having a second period, the output of the first counter unit being connected to the input of the second counter unit, the switching means being connected to initiate the first counter unit and to reset the second counter unit, the output of the second counter unit being connected to initiate the first counter unit, the output of either of the first and second counter units being used to control the output.

20. A timer according to claim 1 wherein said counter comprises first and second counter units of which the second counter unit has a period equal to 24 hours and which both receive the clock pulses,the output ofthe first counter unit being used as an output ofthe timer, the switch means being arranged to reset the first and second counter units, the output of the second counter unit being arranged to reset the first counter unit.

21. Atimersubstantially as hereinbefore described with reference to the accompanying drawings.