GB2183115A - Digital to analogue converter - Google Patents

Abstract

A digital to analogue converter (DAC) suitable for use in a digital radio receiver, such as an automobile receiver having up to four loudspeakers. A DAC associated with each loudspeaker comprises a digital over- sampler (10) for oversampling a digital input signal and a second-order noise shaper (12) for approximating the signal reshaping and filtering the noise of the approximation error so that a substantially noise free audio signal is obtained which is applied to a two-level converter (14), the output of which is used to reconstruct an analogue waveform. The use of a second-order noise shaper enables up to four DACs to be integrated into a single IC. <IMAGE>

Description

SPECIFICATION A 1-Bit Second-Order Pulse Density Modulator Digital to Analogue Converter The present invention relates to a 1-bit secondorder pulse density modulator digital to analogue converter (DAC), particularly a converter which can be fabricated as an integrated circuit (IC) using CMOS technology.

For digital audio circuits fabricated as ICs it is difficult to make DACs having large dynamic ranges, greater than 90 dB, with good signal to noise characteristics. However such a digital-to-analogue conversion system is used in the compact disc digital audio system, which DAC system is implemented as two integrated circuits sold by Philips underthe type numbers SAA 7030 and TDA 1540. The IC SAA 7030 is a digital oversampling section, transversal filter and noise shaper which together substantially reduce the quantisation noise prior to a signal being applied to the DAC integrated into the TDA 1540 IC. Since the TDA 1540 is oniy a 14 bit DAC, the digital wordlength has to be reduced from 16 to 14 bits. This results in an addition of quantisation noise.This quantisation noise is reduced by digitally oversampling by a factor of four before reducing the wordlength to 14 bits which has the effect of spreading the noise across a frequency band four times greater than the wanted band and by low pass filtering the oversampled signal a large part of the noise is eliminated. This quantisation noise can be reduced further by noise-shaping which distributes the noise unevenly over the bandwidth of the over sampled signal so that the noise in the audio band that is 0 to 20 kHz is decreased whiist that outside the audio band is increased.As a result of these measures the signal applied to the DAC has maximum signal to noise ratio of the order of 97 dB. Whilst this known DAC is satisfactory it does require two ICs for each stereo channel and there are applications such as mobile stereo radio/cassette players where signals are to be supplied to four loudspeakers. Consequently there are size and cost limitations in implementing the required circuitry using the known chip sets.

An object of the present invention is to provide a DAC which has a large dynamic range and which is sufficiently compact when integrated that several similar DACs can be formed in the same IC.

According to the present invention there is provided a 1-bit second-order pulse density modulator digital to analogue converter comprising means for oversampling a digital input signal, a second order noise shaper connected to said oversampling means, and means coupled to the noise shaper for providing a two-level output.

The converter in accordance with the present invention has a large dynamic range of the order of 90 dB and by virtue of using a second order noise shaper it is sufficiently compact when integrated as to enable four DACs to be integrated into a single IC.

The noise shaper may be adapted to provide a 1 bit coded signal output which is used by a switchable signal inverter to generate a two-level output in response thereto. An analogue signal is produced by filtering the two-level output signal.

The present invention also relates to a digital radio receiver including at least one of said DACs.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein, Figure 1 is a block schematic diagram of one embodiment of the present invention, Figure 2 is the transfer characteristic of the approximator 26 shown in Figure 1, Figure 3 is a graph of noise power NP against frequency F showing the effect of noise shaping, Figure 4 is a schematic circuit diagram of a switchable signal inverter, and Figures 5A to 5N are waveform diagrams illustrating the operation of the switchable signal inverter shown in Figure 4.

In the drawings, corresponding features are identified by the same reference numbers.

In Figure 1, the circuit comprises an 11.2 MHz over sampler 10 which is connected to a second order noise shaper 12 to an output of which a two-level digital to analogue converter 14 is connected. The interconnections between these parts is done in parallel and the number of bits is denoted by the number associated with the oblique line drawn across the interconnections.

The input signal to the over sampler 10 comprises a digitised audio signal which has been linearly quantisedwith 16 bits art a sample rate of 44.1 kHz.

This signal is fed into the over sampler 10 at a clock rate of 44.1 kHz and provides an output at 11.2 MHz.

This signal is then fed into the noise shaper 12 which includes an approximator 26. This approximator 26 has a transfer characteristic which is shown in Figure 2. Assuming the input signal is a 2's complement binary number scaled in a way, that positive full scale represents a number of +1-2-15 and negative full scale represents -1,the approximator will produce an output signal in the following manner:

r+1 for input > 0 output= i input 0 1 for input < 0 This output is a very crude approximation of the 16-bit input signal and in other words contains a large amount of quantisation noise due to the large approximation error.In orderto reduce this error by means of noise shaping, an adder 30 is provided, which calculates the approximation error and feeds it into a filter 32, whose result is added to the input signal in a summing arrangement 28. The filter 32 is a digital filter with the transfer function H(z)=Pz-' -z-2.

The filter 32 comprises a first delay stage 34 having a transfer characteristic of z-1, The output of the stage 34 is applied to a shifter 36 which muitiplies the signal by 2. The output of the stage 34 is also applied to a second delay stage 38, whose output is connected to a buffer 40. To produce the output of the filter 32, the output of the buffer 40 is subtracted from the output of the shifter 36 in a subtractor 42.

This filter 32 combined with the adders 30 and 28 form a feedback loop, which changes the spectral distribution of the quantisation noise in such a way that most of it lies out of the audio band from 0 to 20 kHz.

If N is the noise power density of the approximation error without the feedback loop and NS that of the shaped noise with the feedback loop included, then the noise shaper can be described in the following manner: NS(z)= 11 -H(z) 2 N(z) = | 12z-1+z-2 fZ-2 12. N(z) = | (1Z-1)2 12. N(z) with z=exp (2rf/Fs) where Fs is the sample rate: The spectral distribution of the shaped noise is defined by NS(f)=(2-2 cos (2rf/Fs))2 - N(f).

Assuming N(f) is white noise with the noise density N(f)=N the shaped noise density will have a distribution which is shown in Figure 3. Only a small amount of noise is left in the audio band (0 to 20 kHz), while most of the noise is at higher frequencies. The residual noise energy in the audio band which is contained in the 2-level output is more than 90 dB lower than energy of the audio signal itself.

The 1-bit output of the approximator 26 is applied to the DAC 14.

In the illustrated example of the DAC 14 the 1-bit input is applied to a clock control circuit 44 which controls the operation of a 2 position switch 46.

Each pole of the switch 46 is connected to a respective bias source related to the respective binary value of +1, and -1. The output of the switch 46 is connected to a low pass filter 48 which filters the pulses to produce a smoothly varying waveform.

In another example of implementation the 1-bit output of the approximator 26 is coded into a 1 bit polarity signal. This signal controls a switchable signal converter 50 shown in Figure 4 to produce the required 2 level output. The switchable signal inverter 50 is disclosed in Netherlands Patent Application 8501896. However for the sake of completeness a brief description will be given.

Referring to Figure 4, the circuit shown converts a 1-bit coded signal into an analog signal by means of an integrator comprising an operational amplifier 52 whose output 54 is fed back to an inverting input 56 of the amplifier 52 via a first capacitor C1 and a resistor R. A non-inverting input 58 of the amplifier 52 is connected to ground. Dependent upon the value of the 1-bit coded signal either a positive or negative current impulse is applied to the inverting input 56 of the integrator. The current impulses are derived using switching circuits 60, 62 connected between a voltage reference source 64 and the inverting input 56. The switching circuit 60 generates positive current impulses and comprises a second capacitor C2 which is coupled to junctions A and B.Switches S1 and S2 respectively connect the junction A to ground and to the source 64.

Switches S3 and S4 respectively connect the junction B to ground and to the inverting input 56.

The circuit 62 for generating negative current impulses comprises a third capacitor C3 connected to junctions C and D. Switches S5 and S6 respectively connect the junction C to ground and to the source 64. Switches S7 and S8 respectively connect the junction Dto ground and to the inverting input 56. A fourth capacitor C4 of larger capacitance than that of the first, second or third capacitors C1, C2 or C3 is connected between the inverting input 56 and ground.

The operation of the switches S1 to S8 is controlled by devices 66 and 68. The 1-bit coded signal, I, is connected to the device 66 which controls the operation of the switches S3, S4, S7 and S8. A clock signal CK of higher frequency than the coded signal is applied to the device 68 which has outputs for controlling switches S1 to S7, of which those controlling the switches S1, S3, S6 and S7 are in antiphase to those controlling the switches S2, S5.

The operation of the switchable signal inverter 50 is summarised in Figures 5Ato 5N. When I is high then negative current impulses are applied to the inverting input 56 and when I is low positive current impulses are applied to the inverting input 56.

In the case of applying the digital to analogue converter to a digital radio receiver supplying four loudspeakers, then four DACs would be required and they could all be integrated into a single IC.

Claims (7)

1. A 1-bit second-order pulse density modulator digital to analogue converter comprising means for oversampling a digital input signal, a second order noise shaper connected to said oversampling means, and means coupled to the noise shaper for providing a two-level output.

2. A converter as claimed in Claim 1, wherein the noise shaper is adapted to provide a 1-bit coded signal output and wherein a switchable signal inverter is provided to generate a two-level output in response to the 1-bit coded signal, which two-level output is applied to an integrator (filter) to produce an analogue signal.

3. A converter as claimed in Claim 1 or 2, wherein the noise shaper includes a digital filter having a transfer function H(z)=2z-1-z-2.

4. A converter as claimed in Claim 1,2 or 3, wherein the oversampling means is operated at 11.2 MHz.

5. A 1 bit second order pulse density modulator digital to analogue converter, constructed and arranged to operate substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.

6. An integrated circuit comprising four converters as claimed in any one of Claims 1 to 5.

7. A digital radio receiver comprising at least one converter as claimed in any one of Claims 1 to 5.