GB2179810A - Dynamic range control of a signal - Google Patents

Abstract

A dynamic range controller consists of a multiplier 14, Fig. 1 controlled by a side chain 18 comprising: a level detector 20, a log circuit 22, a threshold subtractor 24, a non-linear circuit 26, a slope multiplier 28, and an antilog circuit 30. The level detector 20 comprises a peak detector (40, Fig. 4) with separate attack and decay time constants, in which the decay time constant is itself dependent upon the output of an r.m.s. detector (60). The slope and threshold values vary such that two or more different threshold/slope factor pairs are used for different sections of the signal amplitude so that the device provides different DRC functions (limiter, compressor, expander, or noise gate) for the different amplitude sections (Fig. 6). A smoothing recursive filter (Fig. 9) is included between the antilog circuit 30 and the multiplier 14, and has a time constant which varies as to whether the detector is in the attack or the recovery mode, this mode determination being made with a degree of hysteresis. The response time constant of the filter is between one-sixth and two-thirds of that of the level detector 20. <IMAGE>

Description

SPECIFICATION Dynamic range control of a signal BACKGROUND OF THE INVENTION This invention relates to a method of and apparatus for dynamic range control, in particular which is suitable for use in the digital processing of audio signals.

Dynamic range controllers (DRCs) are used to increase or decrease the dynamic range of audio signals both for technical purposes, such as the protection of equipment from overload or the reduction of low-level noise signals, and, increasingly, for artistic purposes to achieve a desired effect. In each case, the aim is to manipulate the dynamic range in a prescribed way without introducing perceptible distortion. This is done by imposing time constants on the gain control signal, with the result that there is no steady-state waveform distortion.

A paper by G.W. McNally and T.A. Moore published in the Proceedings of the International Conference on Accoustic Speech and Signal Processing (ICASSP) at Atlanta, Georgia, U.S.A., March 1981, pages 590-594, describes a dynamic range controller which can operate on digital audio signals. However the controller has a number of disadvantages and the present invention is directed to various improvements in dynamic range control which can be applied to such a controller.

The invention is defined in the appended claims, to which reference should now be made.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described by way of example with reference to the drawings, in which: Figure 1 is a block diagram of a DRC device described in the ICASSP paper mentioned above; Figure 2 is a block diagram of a peak measuring method for use in the signal level detector; Figure 3 is a block diagram of an r.m.s. measuring method for use in the signal level detector; Figure 4 is a block diagram of a preferred signal level detector incorporating the circuits of Figs. 2 and 3; Figure 5 shows the input/output characteristic of the function circuit 74 in Fig. 4; Figure 6 shows the input/output characteristic of a multiple function DRC device; Figure 7 shows the gain characteristic of the same device; Figure 8 is a block diagram illustrating the generation of the gain control signals for the different sectors;; Figure 9 is a block diagram of an adaptive smoothing filter for filtering the control signal after the log/antilog operation; and Figure 10 shows the control signal before and after such smoothing.

(A) BASIC DRC DESCRIPTION Fig. 1 shows a digital automatic dynamic range control (DRC) device of generalised form based on that described in the ICASSP paper mentioned above. The device can be implemented as a limiter, compressor, expander, or noise gate as required. It is simplest however to consider its operation as a limiter.

The device of Fig. 1 has an audio input 10 for receiving digital audio signals which after delay in a delay device 12 are subject to gain control in a multiplier 14. The output 16 of the multiplier 14 constitutes the output of the device.

The multiplier or control input to the multiplier circuit 14 is formed in a side chain 18. The side chain is shown in a feed forward configuration although in principle a feedback or more complex configuration can be used. The side chain includes a level detector 20 which receives the input audio signal and determines a measure of the level of this signal. The level can be the peak level or the r.m.s. (root mean square) level, as described below, and the integration or response time is determined by one or more response time parameters applied to the circuit.

In the case of a peak level detector the circuit 20 will conveniently have separately-identified attack and recovery time constants, related respectively to the speed at which the circuit responds to a sudden excursion in level and to a subsequent reversion to normal level. Typically in an audio application the attack time would be less than 10 ms and the recovery time in excess of 100 ms. However, if the detector 20 is an r.m.s. detector, then conveniently there will be a single averaging time constant which relates to level changes in either sense. A suitable value might then be 50 ms.

The output of the level detector 20 is next subject to a logarithmic operation in a log circuit 22, so that the appropriate power law of the DRC can be realised by simple multiplication. A subtractor 24 compares the output of the log circuit 22 with a predetermined threshold value to determine whether dynamic range control as specified is required to be applied to the signal.

This determination is completed in a non-linear circuit 26 which selects only positive outputs from the subtractor 24 in the case of a compressor or limiter and only negative outputs in the case of an expander or noise gate. The difference signal output of the non-linear circuit 26 is applied to a multiplier 28 where it is multiplied by the desired slope corresponding to the appropriate power law of the DRC device. The antilog of the resultant is taken in an antilog circuit 30 and this constitutes the control signal for the multiplier 14.

The delay 12, apart from compensating for any delay in the side chain 18, can be arranged to give the detection circuits in the side chain time to act before a peak occurs, and thus avoid the occurrence of overshoot at the limiter output on brief signal peaks or transients. A value of about 300 microseconds would typically be suitable.

While the circuits are described in relation to discrete circuitry, it will be appreciated that the operations may be achieved by use of a digital computer, in which case the diagrams should be treated as function diagrams rather than circuit diagrams.

Although the various features described below are shown being used together, they can be used independently in appropriate circumstances.

(B) LEVEL DETECTION In a dynamic range control device which takes the form of a protective limiter, the level detector will normally be based on peak detection. In other cases, and in particular for artistic purposes, r.m.s. detection may be used, on the assumption that it gives a better indication of loudness than either peak or average value.

A suitable peak detector 40 is shown in Fig. 2. The detector includes a full-wave rectifier 42 connected to the input 10, the output of which is connected to the non-inverting input of a subtractor 44. Positive outputs only from the subtractor are selected by a non-linear circuit 46 and multiplied in a multiplier 48 by a coefficient TA which determines the response time to an increasing input signal, i.e. the attack time. A store or one-sample delay 50 represented by the notion Z-' has its output connected both to the inverting input of the subtractor 44 and one input of an adder 52 which also receives the output of the multiplier 48. The output of adder 52 is applied through a subtractor 54 to the store 50.Thus in this part of the circuit the magnitude of the input signal is compared with the stored peak value, and when it exceeds the stored value the difference between them is multiplied by an attack response coefficient and the resultant is added to the store content. In this way an exponential attack characteristic is obtained with time constant determined by the coefficient TA.

A 'leakage' path is provided by a multiplier 56 which receives the content of the store and multiplies it by a recovery (or release) coefficient TR which determines the response time to a decreasing input signal. The resultant is applied to the inverting input of subtractor 54 to decrement the stored value. The amount of the decrement is thus a proportion of the peak value for each sampling instant, so producing an exponential recovery characteristic. For long recovery times the value of TR may be impractically small, and so the product is preferably scaled by binary shifting in a circuit 58 to extend the recovery time.

The content of the store 50 constitutes the output of the peak detector 40 and is applied to the log circuit 22.

Fig. 3 shows an r.m.s. detector 60. This includes a multiplier 62 connected to square the input values and the output of which is connected to the non-inverting input of subtractor 64, the inverting input of which receives the output of a one-sample store 66. The difference signal determined by the subtractor 64 is multiplied in a multiplier 68 by a coefficient TAV which defines the degree of averaging to be applied, i.e. the averaging time constant, and the resultant is added to the store content in an adder 70 for re-application to the store 66. The store 66 also provides the circuit output, but the square root has to be taken. This is conveniently done by a divide-by-two circuit 72 placed after the log circuit 22. In this level detector exponential averaging is applied to the square of the input.

It can be shown that the time constants of the circuits of Figs. 2 and 3 are given by: T.[(1 -a)/a2]1 seconds, where T is the sample period, and a is the coefficient TA, TR or TAV as the case may be.

One problem with both the detectors is that they fail to respond very well to an isolated peak in an otherwise generally low level signal. The peak detector provides an adequate attack time, but then decrements the signal attenuation too slowly. The r.m.s. detector fails to provide adequate attentuation to the peak at all.

Fig. 4 shows an improved circuit which can be used as the level detector circuit 20 of Fig. 1.

This comprises a peak detector 40 of the type shown in Fig. 2 in which the coefficient TR determining the recovery time is itself adaptively dependent upon the signal level. To this end an r.m.s. detector 60 as in Fig. 3 provides an output to a function circuit 74 which determines the recovery coefficient TR.

One example of the recovery time modifier 74 is shown and consists of a look-up table 76 constituted by a read-only memory, the output of which is applied to a multiplier 78 which receives the predetermined coefficient TR. The characteristic stored in the look-up table can vary considerably depending upon the desired nature of the results to be achieved and may be determined empirically. One possible characteristic is shown in Fig. 5 which plots the r.m.s. level L determined by circuit 60 in decibels against the recovery time modifier coefficient m applied to the multiplier. In this case the normal recovery time constant TR has been at one second.

With this circuit, when the average (r.m.s.) signal level is high, then the recovery time is relatively long. However, if there is an isolated peak in a part of the signal of low average level, the recovery time is relatively short, thus avoiding excessive limiting and compression.

While described in relation to digital audio signals this feature can be used in analogue DRC devices.

(C) MULTIPLE FUNCTION DRC DEVICE In a practical situation it may be desired to apply different DRC functions to the input signal depending on the signal amplitude. Fig. 6 illustrates a typical situation where low amplitude signals are expanded to reduce noise, medium amplitude signals are unaffected, high amplitude signals are compressed and very high amplitude signals limited to avoid overload. The steady state input/output characteristic is shown on a logarithmic plot in Fig. 6 and consists of a series of straight line sections. Within each section the control function is independent of signal level.

In each section, the characteristic is specified by two parameters: 1. Threshold - the signal level at which the required action (e.g. compression) is initiated, usually expressed in decibels (dB) relative to normal programme line-up level, and 2. Ratio - this is the ratio between changes inlevel, measured in decibels, at the input and output of the DRC device. These ratios are normalised so that for a limiter or compressor the change in input is related to a decibel change in output, and for an expander or a noise gate a decibel change in input is related to the change in output.

In Fig. 6 the DRC specification of a four-region DRC is defined by three thresholds and three ratios, the parameter names and typical values for which are given in Table 1.

Table 1.

ETH expander threshold -50dB ER expand ratio 1:2 CTH compressor threshold -35dB CR compressor ratio 3:1 LTH limiter threshold - 15dB LR limiting ratio 100:1 Where there are two active sections next to each other, as in the case of the compressor and limiter sections in Fig. 6, then the second of these (the limiter section) is dependent upon the first, to the extent that the input/output characteristic at the junction of the sections should be continuous and not have a discontinuity. Thus the threshold and ratio for the limiter section do not adequately specify the DRC function for this sector.

Now, a ration may be converted to a slope, corresponding to the slope of the gain characteristic, as shown in Fig. 7. For the above example three new parameters can be defined, and these are shown in Table 2 below with their corresponding values.

Table 2 ES expander slope= 1 - 1/ER - 1 CS compressor slope=1-1/CR 0.67 LS limiter slope= 1 - 1 /LR 0.99 To cover the different DRC sections, the elements 24, 26 and 28 of Fig. 1 must be repeated an appropriate number of times. The output of one of these series circuits is selected in dependence upon input signal level to provide the required control function.

For typical values of CR and LR, O < CS ( 1 and 0 < LS < 1 but for an expander, ER < 1, and so ES can have a slope greater than - 1. In an expander implementation special arrangements must be made to perform this non-fractional multiplication.

The range of threshold values may be expressed as fractional logarithms. We are concerned only with the magnitude of the input signals which for a 16 bit input for example, ranges from zero through 2-15 up to 1 - 2-15. Thus valid real logarithms, calculated with a base of 2 and excepting the zero-input case, will produce logarithms in the range - 15 to - d, where twill depend on the accuracy of computation. To obtain a fractional result, these results can be scaled by a factor of 16, the value - 1 being reserved for the zero-input case.

Considering a general case in which VMAX represents the maximum input signal level in dB, and a scaling factor S is chosen so that all combinations of DRC specifications produce fractional logarithmic values, then the parameter for the compression threshold can be calculated from: CT=(1 /S)1O92[1o cTH - VMAX)/ZO)] and the selction of S will satisfy: (CTH - VMAX) > 20 1Og,o(2-5) The parameters ET and LT can be calculated in a similar way. These values may be stored as look-up tables for a variety of DRC specifications with the benefit that no associated real-time computation is required during execution of the DRC program.

Referring to Fig. 7, it will be seen that the gain function in the limiter section requires a correction CL to be made to the gain at the limiter threshold LT to account for the effect of the compressor up to that point. From a geometrical consideration of Fig. 7 this can be calculated from: CL=CS(CT-LT) The value of CL is determined for each new compressor or limiter selection, though this does not have to be a real-time computation, but is calculated only once for a particular DRC specification.

A circuit for use in the side chain 18 in Fig. 1 in a multiple function DRC device such as represented by Figs. 6 and 7 is shown in Fig. 8. Subtractors 24a, 24b and 24c receive the input signal and the respective thresholds CT, LT and ET. Each subtractor is provided with a non-linear device 26, and a multiplier 28, the multipliers 28a, 28b and 28c recieving multipliers CS, LS and ES respectively.

To the output of multiplier 28b a correction is made in an adder 80. The adder 80 is supplied with a signal derived by subtracting CT from LT in a subtractor 24x, applying the resultant to a non-linear circuit 26x, and multiplying the output of that by CS in a multiplier 28x.

Thus a pre-fixed offset is applied to the control signal in the region where the processing is applied to logarithmic signals to avoid a discontinuity in gain at the sector junction. This is an extremely simple and elegant way of overcoming the problems of producing a continuous characteristic, making use as it does of the existing logarithmic signal processing circuitry.

An output selector 82 is controlled automatically in dependence upon input signal level to take the output for the appropriate control section. If none of the thresholds CT, LT or ET are exceeded, i.e. the input lies in the 'normal' part of the state characteristic, the selector 82 is placed in position 4, where it receives an input of zero. The antilogarithm of zero is unity, and so the control signal does not attentuate the audio signal in the direct path.

While this feature could be used in theory with analogue DRC devices, the use of logarithm and antilogarithm functions lends it to digital applications.

(D) SMOOTHING OF LO(hi/ANTILOG FUNCTIONS The log circuit 22 and antilog circuit 30 are conveniently constituted in a digital configuration by PROMs operating as 'look-up tables', possibly operating only on the the exponent of the logarithm with separate scaling in accordance with the mantissa. These conversion operations are the main source of quantising or rounding errors in the digital system, and are particularly prone to cause such errors near a threshold. Fig. 9 illustrates a smoothing circuit 100 which can be connected between the antilog circuit 30 and the multiplier 14 in Fig. 1 to reduce the effect of these errors.

The smoothing circuit 100 includes a first order low-pass filter 102 including a one-sample delay 104 connected between the output and the inverting input of a subtractor 106. The noninverting input of the subtractor receives the output of antilog circuit 30. The difference signal from the subtractor is multiplied by a smoothing coefficient in a multiplier 108 and the resultant added to the output of the delay 104 in an adder 110, to provide the control signal for the multiplier 14.

To determine the appropriate smoothing coefficient, a subtractor 112 compares the input and output of a one-sample delay 114. This establishes whether the detector is in the attack mode or the recovery mode. A circuit 116 provides a small amount of hysteresis to provide a firm boundary to these decisions, and, according to the result, one of two coefficients ATTSM or RECSM is selected in a circuit 118 for the filter 102. During periods of fast attack the filter time constant is short, determined by ATTSM, and during the recovery period the time constant is long, determined by RECSM.

The hysteresis is preferably achieved as follows. In a period which the gain control signal is decreasing, the smoothing should correspond to an attack mode, i.e. ATTSM. The change to recovery mode is identified by detecting two consecutive increases in the gain control. Only after the second is the RECSM selected. A similar analysis is used for detecting a change from recovery to attack modes.

We have found that to give optimum smoothing without significantly subjectively changing the dynamic characteristics, ATTSM and RECSM should be related to the time constants of the level detector circuit 20. In particular, ATTSM and RECSM should be set to give filter time constants of about one third the level detector attack and recovery time constants, respectively, though a range of about one-six to one-half or two-thirds could be useful in certain applications. An appropriate compromise has to be chosen between maximum smoothing and minimum influence over the selected attack/recovery time constants.

If the circuit of Fig. 9 is used in combination with Fig. 4, then RECSM can be chosen as 1/3 of the modified TR (i.e. mXTR). Since the recovery time is being automatically adjusted then it would be simpler to select 1/4 or 1/2 for easy computation, e.g.

RFCSM = l .m.TR The effect of the filter on the gain control signal is illustrated in Fig. 10 which shows the filter input at (a) and the output at (b). The use of such smoothing is extremely valuable in enabling fairly crude processing in the side chain 18 to be used effectively without introducing distortion into the signal.

Claims (5)

1. A method of dynamic range control, in which the gain of a signal is varied by a control signal which is itself dependent upon a measure of the signal level, the control signal being derived by the steps of making a determination of signal level using one or more defined response time constants to excursions of the signal level, taking the logarithm thereof, forming the difference between the logarithm and a threshold value, multiplying the resultant by a predetermined slope factor, taking the antilogarithm of the resultant, and filtering the antilogarithm value with a recursive filter having an exponential response, characterised in that the response time constant(s) of the filter are related to the response time constant(s) of the signal level determination in that the former are between one-sixth and two-thirds of the latter.

2. A method according to claim 1, in which the response time constant(s) of the filter are not more than one-half of the response time constant(s) of the signal level determination.

3. A method according to claim 1, in which the response time constant(s) of the filter are not less than one quarter of the response time constant(s) of the signal level determination.

4. A method according to claim 1, in which the response time constant(s) of the filter are about one-third of the response time constant(s) of the signal level determination.

5. Dynamic range control apparatus comprising means for varying the gain of an input signal by a control signal, and means for deriving the control signal and comprising means for making a determination of signal level, means for taking the logarithm thereof, means for forming the difference between the logarithm and a threshold value, means for multiplying the resultant by a predetermined slope factor, means for taking the antilogarithm of the resultant, and means for filtering the output of the antilogarithm-taking means with a recursive filter having an exponential response, characterised in that the response time constant(s) of the filtering means are related to the response time constant(s) of the signal level determination means in that the former are between one-sixth and two-thirds of the latter.