GB2179223A - TDM switching system - Google Patents

Abstract

A TDM switching system of the TSTST type uses modular terminals, and control is substantially decentralised. For signalling, the messages are sent ahead of the data, etc. to which they relate, and each such message identifies its source in the first T stage by the time slot in which it occurs. Each such message includes the address of the destination portion of the last stage and is broadcast to all parts of the last stage. The system may use a ring (or bus) of the area network type, in which case the network acts in effect as the central T section. <IMAGE>

Description

SPECIFICATION TDM switching system The present invention relates to automatic telecommunication exchanges.

According to the present invention there is provided a time division multiplex switching arrangement, in which communication connections are set up via a multi-stage switching arrangement, the switching stages including stages of both the time and space types, in which control of the establishment and the release of connections is effected in a decentralised manner, in which signalling information relating to connections to be set up is sent through the switching stages ahead of the communications information, and in which each message which conveys signalling information is sent at a time position in a TDM cycle which identifies the part of the first stage from which it comes, each said message including the address of the part of the last stage for which it is destined and being offered to all parts of the last stage, each said part of the last stage having control means to monitor received signalling messages for messages directed to its said part of the last stage.

According to the invention there is also provided a time division multiplex switching arrangement, in which communication connections are set up via a five-stage switching arrangement, of which the switching stages are respectively of the time, space, time, space, time type, in which the terminal units connected to the first and the last stages are modular in form, in which control of the establishment and the release of connections is effected in a decentralised manner, in which signalling information relating to connections to be set up is sent through the switching stages ahead of the communications information, and in which each message which conveys signalling information is sent at a time position in a TDM cycle which identifies the part of the first stage from which it comes, each said message including the address of the part of the last stage for which it is destined and being offered to all parts of the last stage, each said part of the last stage having control means to monitor received signalling messages for messages directed to its said part of the last stage.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a simplified schematic representation of an exchange of the time-space-time-space-time (TSTST) type embodying the invention.

Fig. 2 shows a representation of an implementation of the invention which uses a ringtype network, similar in many respects to a local area network, as the "middle" of a TSTST arrangement.

Fig. 3 is a switching and connections block diagram of a TSTST system in which the "middle" is a memory array.

Introduction Two different time-space-time-space-time, abbreviated as TSTST, architectures are described, one based on a ring in which the central T-section is a serial store and the other based on a central memory with parallel access which may for reasons of access time be broken up into a number of modules accessed through switches.

Initially a call is established across the telecommunications network between two specific end points (subscribers). In this establishment process a virtual circuit is assigned in each of the switches en-route. The establishment of such a virtual circuit will generally be by conventional means using centralised control at each switch.

Once the virtual circuit is designated information from subscribers can be in burst form and the completely distributed control architecture as here described is invoked to make the physical connections across the switch each time a burst is received.

What follows applies in principle to SM (statistical multiplexing) and PS (packet switching), though there are detail differences in the processing of routing information. The cross office transfer of packets is multiplexed in octets making for a large measure of commonality of hardware between the two approaches. In both cases the assumption is one of switching pre-concentrated traffic.

The general form of the architecture is shown in Fig. 1. Here the five stages can be seen between the incoming and the outgoing PCM links, the "outside" time stages each being referred to as AU, i.e. an access unit.

Incoming Time Section In each access unit (AU) the incoming information is demultiplexed into channels in the SM case and packets in the PS case. For simplicity we only consider 64 kb/s SM channels, the principle of operation for 8 kb/s channels or any other channel rate being the same. The signalling information is extracted in the SM case and examined and translated in the PS case. Storage is for two frames for SM and a few packets for PS. Signalling information is transmitted to the destination links in advance of the information being signalled. The latter is called "data" which in this context includes speech and video.

Decentralised Connection Algorithm Each incoming AU is allocated time slots during which it transmits signalling information which is broadcast to all outgoing AU's. The identity of the incoming AU is implicit to the outgoing AU by the time of broadcast. The broadcast contains the identity of the outgoing AU, the call identity and status information (e.g. for SM the call is active). The outgoing AU "knows" that the signalling information takes effect at a fixed time after it receives it. The method of passing the signalling information across the switch is similar to that used for data (described later) except that it is broadcast to all outgoing AU's rather than being sent to a specific one.

The Central Time Section Data and signalling from the incoming time section AU is passed in arrival order to the central time section at preset times. The throughput capability of the central time section thus needs to at least as great as the sum of all AU inputs. Where the system uses a ring these times correspond to time slots on the ring which has storage equal to a frame duration of information. In the SM case, a frame is 125 microseconds, and in the PS case it is arbitrary but could be a roughly equivalent amount. With the central memory approach both the time and the location in common memory are fixed but the storage requirement is the same. At a fixed time later the data is taken off the ring by the outgoing AU or read out of common memory into the outgoing AU. Signalling is broadcast to all outgoing AU's also at a fixed time after being written to the central time section.For a central memory which forms a time stage, memory read and write occur at the appropriate times.

The Outgoing Time Section The outgoing section assembles frames or packets for transmission. In the SM case it stores octets in an order corresponding to virtual call allocations in the bit map for the link. A system using bit maps in the control operation is described and claimed in our Application No.8518684 (R.W.A.

Scarr 36). For packets it reassembles them for transmission in an order related to time of arrival and/or priority and puts them in a queue for transmission over the link.

General Although the system has been referred to as having a "TSTST architecture" the incoming time section is to some extent degenerate as it performs a buffering function rather than a time slot interchange function whereas the outgoing time section performs full time slot interchanging.

We now describe more specifically embodiments of the general approach outlined above. The next sections are written specifically for the SM version but the PS versions are very similar. A later section describes signalling procedure for the PS case.

SWITCHING BASED ON SINGLE OR MULTIPLE HIGH SPEED RINGS These are systems in which the middle T stage is a ring, such as used in local area networks.

(i) The ring consist of P parallel data paths P3 1, S 8 (ii) The data rate throughput is C bits/s, in which case cross office rate is C/P bits/s per path (iii) With the octets sent parallel-wise on the multiple ring there are C x 125 x 106/8 time slots on the ring (i.e. the loop delay is 125 microseconds) (iv) Time slots are counted with reference to a synchronising pattern conveyed on a data or control nng (v) All the data in a given time slot is sent between one specific sender and receiver. (This implies an element of "packetisation" in that time slots could be multiuser for data rates of less than 64 kb/s and multiuser time multiplexed for data rates of less than 8 kb/s.) (vi) Signalling is broadcast to all receiving AU's in time slots specific to an incoming AU.

(vii) There are a maximum of L access units (AU's) on the ring (made up of LAU's and TAU's see below) and no access point can generate more than 1/Lth of the traffic (i.e. D/L bits/s), implying a non-blocking arrangement.

(viii) Each AU is allocated 1/Lth of the time slots in the send to ring direction. It may well be convenient to interleave these time slots sequentially in AU order to smooth the flow of data onto the ring.

(ix) Traffic between users accessing via the same local access unit (LAU) can by-pass the ring but a time slot is allocated on the ring nevertheless, which need not be used.

(x) There may be special access units for such functions as common channel signalling, maintenance and test. These are either provided on a special ring dedicated to that purpose or provided by time sharing (a few percent) of the available bandwidth on the main ring(s).

Block Schematic Fig. 2 is a block schematic of a LAU; note that it is both incoming and outgoing. The interfaces to the incoming and outgoing links are the high level demultiplex (HLDM), high level multiplex (FILM), low level demultiplex (LLDM) and low level multiplex (LLM) types, as indicated. The 8 kb/s channels are multiplexed up to P bits wide ((v) above) and a first-in-first-out (FIFO) queue is provided as a "speed changer" between the time sections and the ring. On receiving information from the ring a buffer store is provided for the same speed changing requirement. Synchronisation and clock are taken from the ring. A considerable element of "pipe lining" and "look ahead" is clearly required to get the information to and from the ring at the right time.

OPERATION OFA PARALLEL ARCHITECTURE TSTST SWITCH Fig. 3 shows the block schematic of a TSTST switch. The middle T section, Tc, is the common memory section which is modularised to a degree determined by the capability of memory technology. Four modules are assumed for illustration, three of them being shown, and each module contains a connection store MnC and a data store MnD. Links are connected to these modules sequentially, link 1 to module 1, link 2 to module 2, link 5 to module 1 and soon.

Each link on the incoming side is allocated a time slot; links 1 to 4time slot 1, links 5--8 time slot 2 and so on. Every entry in all stores can be written and read for every channel on the links it serves in 125 microseconds.

The time slots for the connection stores run ahead of the time slots forthe data stores and the connection store is written with the identity of the outgoing link, etc. for the next data item to be written into the corresponding slot in the data store.

The connection stores are read out sequentially (interleaved with writing in) and the output is broadcast to all outgoing links. An outgoing link recognises its own address and from the time of arrival of the broadcast can identify the sending link.

The broadcast also contains the relevant virtual channel number and status information sothatthe outgoing link can set up its own bit map and pack the data it receives from the switch correctly. It therefore sets up to read the output of the appropriate data module atthe appropriate time later (determined by the relative phasing of the connection and data stores). Clearly an output link may be required to read at the same time outputs from more than one T, module and must therefore have separate connection to each Tc with buffers to store the transferred data.

The 8 kb/s channels are not shown in the figure but the principles of operation for them are the same.

PACKET SWITCHING WITH FIXED TIME SLOT ALLOCATION Example of Operation with a Ring (a) Linkj has a packet for link m, and j is allocated time slot j on the ring.

(b)Attimej-t,linkj has an allocated signalling slot, and j puts the address of link m into its signalling slot and this is broadcast to all outgoing AU's.

(c) At time j-t+djm link m receives its own address, dim being the delay on the ring between j and m.

However because link m's clock runs behind link j's clock by an amount dim it receives it at "local time" jt and can identify the sender by the time of arrival.

Link m then knows that there is a COP (Cross Office Packet) in local time slot j which it will remove from the ring periodically. Initially the slot contains the packet header from which the length of the packet and the virtual call identity can be obtained. Link m therefore can handle the packet correctly.

Operation with the common memory approach is sufficiently similar to that with the background given above it should not have to be described in detail.

Rings The ring used is an optical ring with a loop delay of 125 microseconds (padded out as necessary to provide such a delay), and it can in principle be distributed over a distance of the order of 2S25 kilometres. The use of such an arrangement can be regarded as a TSTST switch in which the space switching is access to and from the ring and the time switch is storage in the ring (the middle "T"). With the necessary speeds, the cheapest arrangement should be one using a single ring but an arrangement which could be used has eight loops working at 393Mb/s.

A device called a "TDAM" (Transmission Detector and Modulator), see Fig. 2, is in effect an element of variable absorption that can be placed between optical fibre ends and acts as a detector by observing current changes under a fixed voltage and as a modulator by varying the applied voltage.

One such example of such a device is described in ourAppln. No.8517534 (P.A. Kirby 8).

Seen as part of a switch such a device must either: (a) Remove information completely and selectively from the ring and write it to the ring at predetermined times; and read information nondestructively from a second ring (i.e. carrying clock and channel allocation information) or (b) Read information on the ring either nondestructively or destructively and write it. (The nondestructive read is for broadcast or multidestination information and the destructive read is for single destination information or when multidestination information has served all its destinations).

The arrangement (b) can carry channel allocation information as a header.

To implement the above as a single ring with an adequate performance requires a ring rate of 20 Gb/ s which is within the theoretical bounds of optical technology, but to implement it as say 16 parallel rings is easier. The limitations are very much with the electrical interface to the ring, as the capability of single mode fibres is not in question.

Once the capacity of the ring is reached further traffic growth can only be achieved by the addition of rings and interconnections between them. The disctributed nature of the ring however means that growth can be distributed too and the dangers of concentrating too much traffic in one building for example can be avoided.

An alternative to a ring is a dual bus with the sender launching information on the left travelling bus or the right travelling bus according to the location of recipient. Time slots are allocated for access as with the ring. The relative advantages of these two basic configurations needs further detailed consideration.

An electrical ring is likely to be limited to a bit rate in the hundreds of megabits which implies a large number of parallel paths and with access the major cost item this is unlikely to compare favourably with other electrical solutions.

Claims (9)

1. A time division multiplex switching arrangement, in which communication connections are set up via a multi-stage switching arrangement, the switching stages including stages of both the time and space types, in which control of the establishment and the release of connections is effected in a decentralised manner, in which signalling information relating to connections to be set up is sent through the switching stages ahead of the communications information, and in which each message which conveys signalling information is sent at a time position in a TDM cycle which identifies the part of the first stage from which it comes, each said message including the address of the part of the last stage for which it is destined and being offered to all parts of the last stage, each said part of the last stage having control means to monitor received signalling messages for messages directed to its said part of the last stage.

2. A time division multiplex switching arrangement, in which communication connections are set up via a five-stage switching arrangement, of which the switching stages are respectively of the time, space, time, space, time type, in which the terminal units connected to the first and the last stages are modular in form, in which control of the establishment and the release of connections is effected in a decentralised manner, in which signalling information relating to connections to be set up is sent through the switching stages ahead of the communications information, and in which each message which conveys signalling information is sent at a time position in a TDM cycle which identifies the part of the first stage from which it comes, each said message including the address of the part of the last stage for which it is destined and being offered to all parts ofthe last stage, each said part of the last stage having control means to monitor received signalling messages for messages directed to its said part of the last stage.

3. An arrangement as claimed in claim 2, in which the middle time section of the arrangement is provided by an area network, the space stages being part of access nodes onto the network, and in which the first and the last time stages are formed by access units connected via such nodes to the network.

4. An arrangement as claimed in claim 3, in which the network is of the closed loop or ring type.

5. An arrangement as claimed in claim 4, in which the network uses a plurality of parallelly-operating rings.

6. An arrangement as claimed in claim 3, in which the network is of the bus type, each message to be sent over the network being sent leftwards or rightwards therefrom, dependent on the direction in which the destination lies.

7. An arrangement as claimed in claim 2, in which the central time stage is a memory with parallel access, which memory is modular in structure with the various modules accessible via switch means.

8. An arrangement as claimed in claim 7, in which each module of the memory which forms the central space stage includes a connection store and a data store.

9. A time division multiplex switching arrangement, substantially as described with reference to Fig. 1, Fig. 2 or Fig. 3 of the accompanying drawings.