GB2176034A - Control apparatus for actuators - Google Patents

Abstract

A flight controls simulation computer 16 controls three actuator assemblies 18, 19 and 20 for primary flight controls, and another actuator assembly 21 for a secondary flight control. The computer 16 is a multi-microprocessor based computer, each actuator assembly being controlled in accordance with a predetermined mathematical model implemented as a program in a channel processor 32 for the respective actuator assembly. The channel processors 32 receive data via either 16-bit converters 28 or 12-bit converters 28' from analogue signals 23 or 25 from the actuator assemblies. Control commands issued by the processors 32 are converted into analogue signals by the circuits 28 or 28'. Data relating to variables in the respective mathematical models are entered from a host computer interface 17 to a data link interface 35. A crosstalk processor circuit CPUX transfers this data to first areas of double-buffered RAM in respective channel I/O circuits 30 or 30', while the channel processors 32 have access to second areas of the respective RAMs. The first and second areas are interchanged at regular intervals so that the host interface 17 can be supplied with updated data from the channel processors 32, and the channel processors 32 can receive new values for the variables in the respective mathematical models. <IMAGE>

Description

SPECIFICATION Control apparatus for actuators This invention relates to control apparatus for actuators, and especially, but not exclusively, to control apparatus for simulated flight controls.

A typical aircraft primary flight control system includes a number of distinct elements. On the flight deck there is in one such system the pilot's control column, a torque tube and a drive mechanism to a forward cable drum. These components contribute mass, out-of-balance forces and friction to the overall feel of the system. The next item is the cable run connecting the forward cable drum to the components in the rear of the aircraft. The primary contribution from the cable run is a spring effect plus friction and viscous damping. Situated at the rear of the aircraft is an artificial feel system which usually comprises one or more springs, possibly with a means of adjusting the mechanical advantage so that the spring rate felt by the pilot can be varied with the aircraft speed.These items largely determine the static force/ displacement characteristics experienced by the pilot but they also contribute to the mass, friction and viscous damping in the system. The aircraft-powered surface actuatorn are situated in this area and these also contribute to the feel of system as they generally impose a velocity limit on components at the rear of the aircraft as a function of the flow availabe from the aircraft hydraulic supplies. The final component which needs to be considered is the autopilot actuator, as this usually has the ability to apply forces to the aircraft actuator input mechanism.

The "feel" of the flight controls experienced by a pilot is the results of a number of different forces.

Amongst these are spring, breakout, damping and Coulomb friction some of which are a function of velocity of movement of the controls. Compiex non-linear functions are required to describe such forces.

The conventional solution to simulation of the feel of the flight controls is to adopt a special purpose analogue computer to solve the complex functions and second order differential equations with a sufficient frequency response to achieve the necessary smooth response. This solution provides adequate performance but as such, has inherent limitations. First there is the long term drift associated with any analogue computation which, if not corrected, affects the calibration of the system. The inability to provide adequate self-check or performance monitoring increases the problem associated with lack of general stability. The calibration of non-linear functions against associated aircraft data is also a time consuming task with little possibility of applying automatic techniques and other aids within an analogue design.

Also, a unique analogue computer must be designed for each type of aircraft, and consequently there are high recurring design costs. Each circuit card in such a computer contains a part of the analogue computation and whilst the basic design is common for most aircraft types, the non-linear functions, time constants and other parameters associated with aircraft performance have to be designed into the resulting unique circuit card. The use of variable potentiometers offsets some of these problems, but this in turn leads to complicated calibration methods. The impact of this problem is exacerbated further if data associated with the aircraft being simulated is not available at the outset of design.

Recent revisions to the U.S. Federal Aviation Administration regulations for the evaluation and approval of flight simulators have also complicated the design task. Under the new rules it is no longer sufficient to compare the simulator characteristics with the aircraft manufacturer's engineering data for the control system. The simulator now has to be compared directly with measurements made on one aircraft. As the differences between individual aircraft of a particular type together with the tolerances on the measurement procedure can easily exceed the tolerances allowed on the simulator, this can result in the necessity to modify the mathematical model for each application. It is therefore desirable that a flight controls simulator be provided in which the mathematical model is easily modifiable after construction.

The performance of the type of mini computer used for flight simulators is powerful enough to achieve the required iteration rates but such mini computers are too expensive to be dedicated to simulation of flight controls.

It is an object of this invention to provide a microprocessor based flight controls simulator computer which can interface with an existing flight simulator configuration.

The simulation of the correct feel of a control system can be conveniently broken down into two parts referred to herein as the inner loop and the outer loop. The inner loop comprises an actuator, mechanically connected to the pilot's control, together with the servo system necessary to drive it. The outer loop contains the computing elements necessary to make the actuator reproduce the particular "feel" characteristic of the aircraft being simulated. The combination of an inner loop and an outer loop is referred to herein as a channel.

To simulate a primary flight control system the inner loop will contain a hydraulic actuator and a force loop servo system, but in other applications the inner loop may be a hydraulic position servo, or even an electric torque motor. Whatever inner loop is chosen, the outer loop can use the same microprocessor board and digital-to-analog conversion equipment. The use of an independent microprocessor in each channel allows the computer cycling time to be adjusted to suit each application.

The use of powered actuators to simulate aircraft control systems is not limited to the primary flight controls. This technique is also useful in the simulation of some secondary flight controls such as speed brake handles and toe brake pedals. In these cases, the servo actuator may well. be a simple positional device with a much lower output than is required for a primary control system. It is therefore also an object of the invention to provide a computer capabie of controlling a number of different servo mechanisms for flight controls.

For simulating each of the three primary flight controls and the nosewheel steering system the inner loop will normally consist of a hydrostatic hydraulic actuator coupled to the pilot's control through a force sensing load cell. The position of the actuator is measured with a linear position transducer and an analogue, force-feedback servo system provides the control signal to a servo valve in the hydraulic supply to the actuator. This arrangement produces a sensitive, high bandwidth but stabie system.

In addition to controlling the hydraulic actuator the inner loop must also "fall safe" to prevent any malfunction in the components likely to cause damage to the simulator or trainee pilot. This is achieved by monitoring power supplies, actuator force, actuator velocity etc, and de-activating a fast operating hydraulic safety valve when any of the parameters exceed pre-defined limits.

In a preferred embodiment of the invention, the outer loop for each channel comprises channel processor circuit and an input/output circuit. Two channels may be closely coupled, and run in synchronism through a FIFO interface, giving communication between the two channels at 512 Hz. This facility can be used in a simulator for an aircraft which has dual control runs from sticks to control surfaces. Normally, the two controls would be required to move as one, but in the event of a jam, the controls may be split and would then have to operate independently of each other.

The input/output circuit card comprises a sixteen channel multiplexed analogue-to-digital converter plus four channels of digital-to-analogue conversion. Although the A-to-D converter has sixteen input channels only eight are for conversions from the inner loop. The remainder are used for "wrap-around" tests of the analogue outputs and power supply level checks. In addition to these facilities, the input/ output circuit has an area of double buffered RAM through which the channel receives crosstalk parameters from the host computer of a flight simulator.For a typical Gould SEL 32/77 Host Computer, interfacing is required between the 20 Hz or 30 Hz Host tasks and flight controls simulation computer's specialised 512 Hz routines The High Speed Data (HSD) and a compatible interface can be used.-This interface contains a 1K words buffer RAM which interfaces to a crosstalk processor circuit of the flight controls simulation computer.

The main function of the crosstalk processor circuit, on interrupt from the Host, is to transfer data between the buffer RAM on the interface and the double-buffered RAMs in each channel's input/output cir- cuit. On completion of this task the crosstalk processor circuit flags the double buffered RAMs which then, in synchronism with a respective real-time clock in each channel, interchange RAM areas. Other functions of the crosstalk processor circuit include the updating of a data entry panel and control of a multi-channei RS232 link which may be reallocated to any of the CPUs in the flight controls simulation computer entirely under software control. When a VDU is not available, the data entry panel provides a single location look-and-enter facility to any of the channels.The crosstalle processor circuit may have an Intel 8086 with 4K RAM and 16K EPROM plus standard LSI circuitry to interface with the data entry panel components In addition to simulating the components of a particular aircraft flight control system the mathematical model takes account of any non-linearities which exists in the simulator installation. These non-linearities, which usually occur as a result of using aircraft parts in the flight deck area, affect the relationship between pilot force and the force measured at the load cell and the control position and the position measured by the linear position transducer.

During development, the software is downloaded from a Microprocessor Development System to RAM within the flight controls simulation computer and then programmed in EPROM when verified.

Each channel simulation program is run effectively as an interrupt task every 1.95 mS. Depending on the complexity of the task, this generally takes about 1 to 1.3 mS and, on completion the channel CPU returns to its background program. This background routine consists firstly of updating information on a debug page and secondly, of running diagnostic tests and reporting back the status of the channel to the Host in real-time. In addition to these tests the channel CPUs, at power up, pass through "Morning Readiness" checks which exercise the I/O components, perform RAM tests and ensure that the flight controls simulation computer is in a fit state to operate.

Any fault condition flags are passed back to the crosstalk processor circuit and thence to the host. Thus faults can easily be traced from system level to channel level to board level and, within certain constraints, to component level from the host.

Channels passing Morning Readiness checks automatically proceed with their simulation tasks, requiring only a manual 'Hydraulics On' switch to be pressed before full simulation commences.

In the event of the safety circuit for a particular channel tripping, then information on the status of that channel is recorded at the instant of the failure and is available for subsequent display. The recorded information includes power supply voltages, analogue-to-digital and digital-to-analogue converter status, control loading actuator force velocity, velocity error and position error.

An embodiment of the present invention can provide facilities for the use of a plurality of separate control loading channels, including a plurality of primary channels and a plurality of secondary channels.

In a preferred embodiment, a primary channel connects to a Fokker Force Loop System inner loop and has a channel CPU circuit, a channel I/O circuit, and 16-bit converter circuitry. A secondary channel has a channel CPU circuit and a channel I/O circuit and another circuit provides the relevant analogue force or position inner loop, fail-safe circuits and analogue power supply monitoring. The preferred embodiment also includes a data link circuit which communicates with an interface of a mainframe host computer, and a further circuit which has a CPU and takes the crosstalk data obtained from the host interface and distributes to the various control loading channels. Circuitry connected to the further circuit may provide for system debug and development, giving look-and-enter facilities and control of system debug VDUs.

Control loading channels are required for several different types of simulated control. Although the controls differ physically, the electronic hardware required to drive them can be made, to a large extent, identical from channel to channel, provided that the loading characteristics are modelled in software for each channel. Both primary and secondary controls have a channel processor circuit and channel I/O circuit. In addition, each primary channel has a 16 bit A-to-D converter and a 16 bit D-to-A converter which provide the main interface to the Fokker Force Loop System (FLS) inner loop. For secondaries, an extended link is used to an analogue interface circuit which comprises 12 bit A-to-D and D-to-A converters and an inner position loop, load cell amplifier, RVDT scaling, and failsafe circuitry, required for the control of a secondary actuator.The analogue interface circuit is located close to its respective actuator.

A typical controls simulator may comprise five control loading channels, e.g.

1. Ailerons (Primary) 2. Elevators (Primary) 3. Rudder (Primary) 4. Toe Brakes (Secondary) 5. Nosewheel Steering (Primary) The channel processor circuit communicates with the channel I/O circuit to pick up its input parameters via backplane wiring. Once converted from analogue to digital form, the inputs are available to be read by the channel CPU during its program cycle. A real-time clock (RTC) in the channel processor circuit boots the program off for one iteration. When a simulation program module finishes, the channel CPU returns to a background task until the next interrupt occurs from the RTC. The fast rate at which the simulation program module must be run to obtain smooth feel demands that the processor must be as fast as possible.An 8 MHz version of the Intel iAPX 86/10, the 8086-2, can be employed along with an Am 29516 sixteen bit hardware multiplier.

Most control loading channels will need an RTC frequency of 512Hz which provides a frame time of about 1.95 mS. During this time the simulation program module must pick up crosstalk parameters from the Host, deposit those that the Host requires and perform all of the required input and output functions.

Since program module times may run up to about 1.8 mS at 512HZ, there is little or no time for the channel CPU to wait for memory, inputs and outputs or dual-port memory arbitration. Therefore, crosstalk is achieved by the switching of RAM areas at the end of every Host computer frame (but synchronised with the RTC of the loading channel).

The simulation program module for each channel can be written in PUM 86 with some ASM 86 routines providing faster procedures such as that required for multiplication. Intel microcomputer development systems can be used to edit and compile the programs.

Simulation program constants such as spring rate and damping coefficients can be changed by running a background task which allows the updating of program constants held in RAM.

A Data Entry Panel provides two methods of using the background task program. The first uses thumbwheel switches and seven segment displays mounted on a front panel giving access to code and data locations in any of the channel processor circuits. No extra hardware such as VDUs are required for this and so it provides a convenient first step in system debug. Secondly, for more detailed system debug a VDU can be connected via the data entry panel allowing several locations to be examined concurrently.

The data entry panel functions are controlled by the crosstalk CPU which, in the case of the thumbwheel switches, monitors registers into which are strobed data from the switches. The crosstalk CPU interrogates the relevant channel processor circuit on behalf of the data entry panel, and deposits the location contents thus obtained in data entry panel output display latches. For the data entry panel VDU, the crosstalk CPU monitors a link between the VDU and a channel processor circuit and, if the appropriate control characters are typed in, switches the link to another channel processor circuit through multiplexers in the data entry panel circuit. The VDU may be mounted remotely, say in a flight simulator cockpit, and be switched to monitor any of the channel processor circuits simply by use of keyboard commands.

Parameters calculated by, for instance, the flight program running -in a Host Computer are required by control loading channels to enable the correct 'feel' to be generated. Similarly, for facilities such as record/replay, the Host needs to obtain data from the channels. Therefore, a data link is provided for crosstalk that will be updated at a maximum rate equal to the host frame rate, which is usually 30 Hz. This data link has a maximum of 1024 16-bit words of RAM so that, by using defined RAM area segmentation it is possible to perform all of the required crosstalk for a plurality of channels (up to fourteen). For a system of fourteen control loading channels, each channel can have up to seventy-three word locations available for read/write crosstalk. A simple protocol can define the way in which the data link RAM is filled, read and rewritten.The RAM is serviced by the crosstalk processor circuit.

A host interface initiates a blocktransfer of data from the data link interface after it receives a-command to do so from the host computer. The design of the data link interface allows the start of the transfer to occur on one of four address boundaries of the data link RAM. Once the host interface has completed a transfer to the data link interface, the data link interface issues a signal which causes an interrupt at the crosstalk processor, thereby informing the crosstalk processor that the host interface is no longer updating the data link interface and can gain unhindered access to read the new data and deposit variables into the data link RAM which the host, via the host interface, can read at the beginning of the next host frame, just before it writes its data.

The crosstalk processor sees the control loading system as sixteen segmented address areas, decoded from four of its address lines.

The first area (OOOOOH to OFFFFH) contains, at the lowest addresses, the interrupt vectors. These are loaded at power-up from EPROM into the first 200H bytes of 4K RAM that occupies OOOOOH to OOFFFH inclusive. Above this RAM, from 08000H to 087FFH is mapped the 1K-x 16 area of RAM on the data link interface.

The second to fifteenth areas are the fourteen 64K byte areas starting from 1000:6000H, 2000:6000H etc, up to E000:6000H. Each of these segments is specific to a particular channel area of double-buffered RAM, and therefore the segment addresses must be decoded at each channel. The crosstalk areas occupy 256 words per channel.

The final area, FOOOOH to FFFFFH, covers devices including an interrupt controller, a counter-timer and a UART which are at addresses starting at FBOOOH. 16K bytes of EPROM space occupy FCOOOH to FFFFFH, thereby covering a bootstrap address at FFFFOH.

Each Channel processor circuit has access to an area of double buffered RAM available in the I/O circuit. Accesses to the double buffered RAM from the crosstalk bus go unnoticed by the channel processor.

The channel processor sees this RAM as just another part of its 64K memory area.

The data link interface, the crosstalk processor and the plurality of channel areas of RAM are linked by a crosstalk bus.

The crosstalk processor updates variables in the double buffered RAM and then informs the channel processor circuit that it has done so by writing to a flag location. After synchronisation with the real-time clock of the channel processor circuit, the resulting pulse toggles aflipflop which has as its output an area control signal which constitutes the enable/disable signal for a number of address and data line buffers which form the mechanism by which two areas of the double buffered RAM are interchanged.

For example, with the area control signal high, the read, write, address and data signals for RAM AREA 1 come from the channel processor, and corresponding signals for RAM AREA 2 come from the crosstalk bus. For the area control signal low, the two areas interchange.

In this way, data from one frame cannot get muddled with that from the next since the interchange of RAM areas is synchronised both with the Host updates and with the fast real time clocks of the independently running channel processor.

The transfer of data is thus carried out as follows. During the frame time of the host computer the control loading channels must be updated and data read back from them. The host initiates this by commanding the host interface to start a transfer of data. The host interface first reads the RAM on the data link interface, thereby transferring data deposited by crosstalk processor in the previous frame. The host interface now outputs data to the data link interface, writing as many words as required for the control loading channels. Once writing is complete, the data link interface sets an interrupt line to be detected by the crosstalk processor (which will be executing a background task). The crosstalk processor responds by performing a number of block moves, the program for which is coded in its on-board EPROM.The areas of datalink interface RAM must be predefined so that the crosstaik processor transfers data to the correct channels. On completion of the distribution of data, the crosstalk processor sends a flag to the data loading channels to tell them that new data is ready and that they should, on receipt of their next real time interrupt, toggle their double buffered RAM areas. The worst case delay for this toggling, assuming that no channel's realtime clock is less than 256Hz, is 4 mS. Therefore the crosstaik processor waits for 4 mS and proceeds to block move data from the double buffered RAM areas of individual channels into predefined areas of the data link interface RAM. The crosstalk processor interrupt routine is now finished and the data in the data link interface RAM is ready to be read at the beginning of the next HSD cycle.

The flag from the crosstalkk processor to the channels commanding them to toggle their double buffered RAMs can simply be a 'write'-to an address that all of the channels can detect. From this, the channels synchronise with their individual real time clocks before toggling their area control flip flops.

The L1011 aircraft has Captain's and First Officer's elevator control columns that 'split'. For normal flight manoeuvres the two control columns are mechanically linked via a dog-toothed clutch. There is a handle in the centre console which, when pulled, separates this clutch allowing the two sticks to be moved independently, each side operating its respective elevator.

To simulate this action two control loading channels are required. For simulation of the sticks locked together, the two loading channels must link closely together to make the sticks appear to move as one.

The amount of crosstalk required for this is small (a few words) but must be fast, i.e. at the frame rate of - 512 Hz. For this reason, another means of crosstalk is provided in the form of a word-wide FIFO link, sixteen words long, there being one such link in each direction between the two closely coupled channels. Each of the two channels has a FIFO arranged to be read by the respective CPU of the channel processor circuit.

When a channel processor wishes to write into a FIFO it does so across connections into the other channel. To prevent data from one channel frame being mixed with that of the other, the two channels are synchronised by making the real time clock of one channel master. An interrupt line is provided for this purpose. In operation one channel CPU writes data whilst the other reads previously written data. To avoid the unlikely event of the read/write sequence getting out of step (due to noise etc), the FIFOs are reset after data transfer in each channel frame. In this way the FIFO data is synchronised in each channel frame.

For the channel processor to monitor four analogue outputs as well as supply voltages, eight data channels are required, along with the eight analogue input channels. The A-to-D hardware comprises a sixteen-input analogue multiplexer, a sample-and-hold circuit, an analogue to digital converter, storage RAM and free-running control logic circuit which continuously cycles through the sixteen channels of conversion. Incorporated in the control logic circuit is logic to allow access to the storage RAM from the channel processor. Simple address mapping allows random access to any of the analogue input data, which may be read at any time (with occasional short waits to allow analogue to digital converter arbitration logic to settle).This continuous conversion means that test software can read analogue outputs without danger of catching the converter with invalid data in the middle of a conversion. By incorporating the relevant software in a background program it is possible to check correct analogue output operation, obtain a level of confidence in analogue inputs and monitor +/- 15V and +5V supplies. From these inputs, diagnostic software can trace the likely source of faults and report to the operator via both VDUs and the Host computer.

Each channel processor may be an Intel iAPX86-10 8MHz version, the 8086-2. A companion chip, the 8284A can be used to generate the clock and the READY signal from the CPU. The CPU is used in its maximum mode, so the 8288 bus controller is required.

Three areas of on-board memory are available to the channel CPU. The first area is 4K bytes of workspace RAM located from address 00000H upwards. The first 200H bytes is reserved for interrupt vectors.

The remainder is available as workspace RAM.

The second area is simulation program module area. During program development, RAM can be used and loaded as and when the module is changed and run. Once finalised, the code is blown into pin compatible EPROM.

The third is an area of EPROM containing the monitoring, testing and debugging programs. This memory is at the top end of the address range, from FCOOOH to FFFFFH, and contains a power-up and reset bootstrap jump command at FFFFOH.

An 8253 timer is incorporated in the channel processor circuit to provide software programmable timing signals. Firstly, a timing signal is used to provide the baud rate generator for an RS232 link. A second timing signal is used in its mode zero to cause a real-time interrupt.

The RS232 link is for use for both monitoring and debugging. The clock input is supplied by the 8253 timer.

The channel CPU receives interrupts from several sources. An 8259A interrupt controller is used to facilitate interrupt handling. The interrupts are as follows: (i) Rx - interrupt from the 8251A informing the CPU that a character has been input from the RS232 keyboard and is ready to be read from the 8251 by the CPU.

(ii) Tx - interrupt from the 8251A informing the CPU that the 8251 is ready to receive a character for transmission down the serial link.

(iii) RTC - interrupt form the 8253 timer informing the CPU that the new frame should start.

(iv) RTC (slave) - interrupt from the 8253 on the other closely coupled CPU card (if present) informing this 'slave' CPU that the new frame should start.

The' hardware multiplier used is the Am 29516. Its data inputs and outputs connect directly with the multiplexed bus of the 8086 to minimise transceiver delays. For 16 x 16 bits multiplication, the two operands are output to the multipliers address. The 8086 can read the answer back immediately. The first 'read' collects the most significant part of the product. The second reads the least significant word. If only the most significant word is required then the second part need not be read. In either case, the logic is ready to accept the two operands of the subsequent calculation.

The word-wide FIFO is accessible to the local channel CPU via an address qualified read command and is resettable from that CPU. To ensure continued synchronism between the two CPUs' data, the FIFOs will be reset every frame after they have read. A small amount of logic can fulfil this function. The 'data in' connections to the FIFO come via backplane from the other channel. No address lines are required, but the write command must be present to strobe the data into the FIFO.

The channel I/O circuit connects with the channel processor circuit and picks up data, address and control signals. The control signals comprise read, write, double buffered RAM and input/output select signals and an acknowledge signal ACK. A real time clock signal from the channel processor circuit is connected to provide the synchronisation signal for double buffered RAM area interchanging.

The channel I/O circuit is provided with up to eight twleve-bit analogue inputs. The A-to-D conversion employs a single converter and a sixteen channel analogue multiplexer. The remaining eight channe!s are used for analogue output wrap-around tests and power supply monitoring. A control circuitcontinu- ously cycles through the sixteen channels and, for each conversion, stores the result in a 16 x 12 bits duai port RAM. Address decoding logic detects when the channel CPU requests access to the RAM. If the analogue to digital converter is currently using the RAM then the CPU is held off (by withholding ACK) unti! the converter has finished writting - a matter of a few microseconds.

Four twelve-bit digital-to-analogue (D/A) converters are provided in the channel I/O circuit. The D1As accept two's complement inputs on a single word write pulse from the channel CPU.

The double buffered RAM is incorporated in the channel I/O circuit and is connected to the crosstalk bus. Its control logic switches the read, write, data and address lines to the appropriate areas, synchronising the changeovers with the end of crosstalk flag and the real time clocks The 1024 bytes of RAM are organised as two areas of 256 words. All accesses are as words, so that each location has an even address and two bytes occupy a word.

To allow wrap around test, the outputs of four D/A channels are fed back and converted to be monitored by the CPU. Four spare channels are left out of the sixteen multiplexed input channels of the A/D converter and these are used to monitor +10V reference, scaled +15V supply, scaled -15V supply and +5V supply voltages. With suitable software it is possible to monitor analogue outputs, analogue inputs and supplies to give a reasonable level of fault detection. An error condition flag can then be both displayed on VDU and sent to the host for relevant action there.

A separate circuit provides the sixteen bit analogue input/ output in primary control loading channels.

For self-test purposes buffered versions of the D-to-A output and the A-to-D input are written to two of the analogue inputs of the channel i/O circuit. Similarly, scaled versions of the external (Fokker) power supplies are coupled so that the channel CPU can monitor these supplies via the channel I/O circuit analogue inputs.

Two other signals required between the separate 16-bit circuit and the Fokker system are 'Forward Position' input and 'Computed Force' output.

For each primary channel the single sixteen bit analogue output accepts two's complement format on a 'write' strobe and generates voltages in the range -10 volts to +10 volts.

The converter output is buffered by two non-inverting amplifiers, the first to provide a signal used as the 'Computed Force' output, and the second used as the output to the channel I/O circuit analogue inputs for self-test monitoring.

For each primary channel the sixteen bit analogue input accepts analogue voltages in the range -10 volts to +10 volts. An A-to-D conversion is booted by a single write strobe to a 'read' address for the analogue input. The output to the channel I/O circuit is coded in two's complement format and made available during a read by the channel processor. The analogue input voltage to the A-to-D converter is buffered and made available for use by the channel I/O circuit and thus by the channel CPU for self-test functions.

Each +15 volt supply is scaled so as to provide an output of +5 volts when it is at its correct output voltage. The scaled voltages are presented to analogue inputs on the channel l/O circuit, where they are converted and used by self-test routines.

In a secondary control loading channel, the analogue interface circuit is connected through a 50 way ribbon cable to the channel I/O circuit. The cable comprises sixteen data lines plus read and write control lines, and lines for analogue signals representing force, velocity, position, demanded position and two test inputs, auxiliary force and auxillary position.

Analogue signals essential for simulation are converted in the analogue interface circuit and travel the length of the ribbon cable in digital form. Power supplies and grounds required are t15 volts and signal ground, and +5 volts and digital ground. A twelve bit A-to-D converter is used to convert the scaled output of a loadcell to two's complement format at TTL level. The conversion is initiated by writing to an analogue input read address. A twelve bit analogue output accepts two's complement data written to analogue output address and generates voltages in the range -10 volts to +10 volts FSR. The analogue output is used in the analogue < interface circuit as the 'Position Demand' input.

Analogue comparators are used to monitor magnitude and rate demand outputs of servo drive circutiry. if the drive signals exceed pre-defined levels the drive to a safety valve of the secondary actuator is turned off, thus the actuator will fail-safe. To turn the actuator on again, normal operating voltages must be restored at the comparator inputs, correct working hydraulic pressure be provided and the actuator be close to its quiescent position.

Once converted to analogue form, the 'Demand Position' output is buffered and fed back down the ribbon cable to one of the channel I/O circuit analogue inputs. Similarly, the 'Loadcell' input is buffered and sent to another of the channel I/O circuit analogue inputs. By checking converter against converter, it is then possible to monitor the system for faults and, when they occur, give a good guide as to where they may lie.

The crosstalk processor circuit provides the link between the stored data in the data link interface and the various control loading channels. In each host frame the crosstalk processor circuit transfers up to 1K words and as a background task, controls the data entry panel functions. The crosstalk task runs as one of a number of interrupt routines and is initiated by an interrupt from the data link interface card and moves data to the control loading channels. The crosstalk processor circuit card includes in addition to the crosstalk CPU, two sets of bus transceivers, an interrupt controller; a counter timer, a UART and level changers for an RS232 link and clock and wait state generators. Two areas of memory are available on the card. The first, located in the bottom 2K words, is RAM for interrupt vectors and workspace.The second is'an 8K words area of EPROM at the top end of the address range and contains a bootstrap address and monitoring, debugging and crosstalk programs. Address latches are provided and an inter nal data bus connects with the data entry panel circuit. The data entry panel circuit comprises two ranks of thumbwheel switches, four seven-segment displays, a few switches and an LED, and provides the facility for examining single memory locations throughout the control loading system and changing the values held therein. To call up a memory location, an identifying number for the channel required is entered on a 'CPU NO'. thumbwheel switch. The address of the location then dialled up on four 'AD DRESS' switches. An 'ENTER ADDRESS' button is pushed, which sets an interrupt.The crosstalk proces sor circuit responds by communicating with the relevant channel CPU via double buffered RAM using protocol defined by firmware in the EPROMs of the crosstalk CPU and the channel CPU. The address entered on the data entry panel is passed to the channel CPU which responds in subsequent frames by sending back data read from the address. The crosstalk CPU reads the data in double buffered RAM, formats it and writes it out to the seven segment displays of the data entry panel.

When the power is first turned on, each channel CPU goes to the start address FFFF:OH to pick up a vector to a respective simulation program.

A small routine examines an area of EPROM/RAM to see if it is set at a pre-defined value. If so, control will immediately be transferred to Morning Readiness routines and thence to the real-time application program, thus, the channel CPU can automatically run the control loading program module on power-up and on reset.

The control loading module, running every 1.95 mS (for 512 Hz RTC frequency), is interrupt driven.

When the channel CPU is not executing control loading module code it is running a background task which is a continuously looping program.

For operation of two closely coupled channels a couple of additions must be made to the functions of the executive listed above. These are: (ia) Transfer (up to) sixteen words from the FIFO RAM to a predetermined area of buffer RAM.

(ib) Write the 'clear FIFO' flag to the FIFO's control logic. and (iia) Transfer (up to) sixteen words from buffer RAM to the FIFO on the other channel's CPU card.

This allows the transfer of up to sixteen words in each direction between two CPUs at the real time clock frequency.

On power-up, the channel CPU detects whether the EPROMs containing the module are present. If so, control is transferred to the background task. This program executes built-in-test and a real-time look and-enter facility. The look-and-enter section of the program runs in conjunction with two interrupt-driven routines. The first tells the CPU that the UART interfacing the channel RS232 link is ready to transmit a character to the VDU terminal. The CPU then takes the first character from its software FIFO output queue and writes it to the UART, and returns to background task. The second routine interrupts the CPU to inform it that a character has arrived in the UART from the RS232 link, i.e. someone has pressed a key.

The CPU takes this character, puts it in its input buffer, and return to background task. A typical sequence of events might be as follows: For each loop of the background task program, the locations called up are looked at and, if they have changed, have their new values put in the output queue to be transmitted down the RS232 link. This queue is then depleted via the 'ready to transmit' (Tx) interrupt routine. If the user wishes to, say, change the value held in a location displayed on the terminal he, first of all, presses a key defined as the cursor ('at') indicating which, in the list of displayed locations, is to be altered. Pressing the key causes a 'ready to receive' (Rx) interrupt to be issued via the UART and interrupt controller to which the channel CPU responds.Upon seeing the character as valid, the channel CPU, through the background task, issues the appropriate characters to move the cursor down the list of displayed locations. This string of characters is sent to the VDU terminal using the Tx interrupt routine. To change the value in the location the user types in the 'enter value' command followed by the new value and by 'carriage return' which the background task sees as the correct string to tell it to write the new value into the location.

Other features of the background task include: (i) Single precision 'B' scaling of the values held in the called-up locations.

(ii) Refresh page facility after a small delay (to be called by the crosstalk processor circuit when it switches over a VDU from one channel to another).

(iii) Commands for the crosstalk processor circuit to use when it is acquiring data for the data entry panel for single location reading and writing.

(iv) Software to perform Morning Readiness and Real Time Monitoring tests.

For its background task the crosstalk processor circuit runs a modified version of the background task used in the channel CPUs. The crosstalk processor circuit has memory-mapped access to the entire 1M byte address space, thus allowing it to examine locations in all of the double buffered RAMs and the 1K words RAM area of the data link interface.

The crosstalk processor circuit background task also includes the polling of the address, data and control latches of the data entry panel and the subsequent actions of fetching and changing data in the channel processor circuits.

As well as the Tx and Rx interrupt routines, another Rx interrupt routine is written to handle the keyboard eavesdropping part of the VDU control program. The crosstalk processor circuit checks each character transmitted to a channel CPU from the VDU and, if the 'change CPU' control character is sent (which the channel CPU ignores) the crosstalk processor circuit takes the next character as the new CPU number, cuts the VDU/CPU link, connects itself to the new CPU, issues a 'refresh page' command, cuts the CPU/CPUX link and connects the VDU to the new CPU by controlling multiplexers.

When the data link interface issues an interrupt to the crosstalk processor circuit, the crosstalk processor responds as follows: (i) Block move data from the datalink interface to the areas of double buffered RAM in the channel I/O circuits.

(ii) Block move data from the double buffered RAMs into the data link interfaces.

(iii) Issues an I/O 'write' command on the crosstalle bus to prompt the channel I/O circuit double buffered RAM control logic to toggle the area control signal.

(iv) Return to the background task.

The host computer contains software to initiate transfers of crosstalk data from the host interface. The crosstalk data locations will be organised so that data arrives in the correct locations. For self-test, the fault flags are sent from the channel CPUs to be available for use by the host. It is therefore left to the Host programmer to use the flags in the flight simulator self-test regime.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic illustration of a simulated flight control and a mathematical model applicable thereto; Figure 2 is a block diagram of a computer for simulating the behaviour of a plurality of aircraft controls; Figure 3 is a block circuit diagram of part of the computer of Figure 2; and Figure 4 is a block circuit diagram of another part of the computer of Figure 2.

In Figure 1 there is represented an aircraft control column 11 to be mounted in a flight simulator cockpit. The control column 11 is mechanically connected to an hydraulic actuator 12 controlled by a servo valve SV. The force exerted on the control column 11 by the actuator 12 is sensed by a load cell 13 which produces an electrical analogue output signal representative of the sensed force. A linear position transducer LVDT, which may be a linear voltage differential transducer, senses the position of the control column and produces an electrical analogue output signal representative of the position sensed. The two analogue output signals are supplied as analogue input signals to a servo drive 14 which generates an electrical analogue output control signal which is supplied to the servo valve SV which is an electrohydraulic valve.The servo drive 14 generates the analogue output control signal in dependence upon the two analogue input signals received from the load cell 13 and position sensor LVDT respectively and a 'force demand' signal representing force required to be exerted by the control column 11, received from a computational mathematical model 15 which takes into account the behaviour of the aircraft control system to which the control column 11 would be connected in the aircraft being simulated. This mathematical model 15 receives as inputs, the velocity and position of the control column 11 from the servo drive 14, and aircraft hydraulic supply rate and autopilot demand from an exterior source, which in practice is a flight simulator computer acting as host. The force demand signal is representative of the sum of forces reacting to the velocity and position of the column 11.Inertial and frictional forces arising in the mechanical connection of the simulated control to a connector cable are summed directly. The cable contributes, directly, a spring force. The cable is connected to an aircraft surface actuator through a mechanical arrangement in which frictional forces, viscous damping forces and spring forces arise. The surface actuator itself is moved hydraulically and imposes iimits of position, velocity and acceleration. The flow in the actuator hydraulic supply determines the actuator velocity limit. Autopilot demand produces forces acting directly on the aircraft surface actuator input.

Figure 2 shows schematically an aircraft controls simulator computer 16 coupled to a host computer at a host interface 17 and to three primary aircraft control actuator assemblies 18, 19 and 20, and one secondary aircraft control actuator assembly 21. The host interface 17 is connected to the controls simulator computer 16 by a multi-bit bus 22. The computer 16 is connected to each primary control actuator assembly by analogue input lines 23 and analogue output lines 24, and to the secondary control actuator assembly 21 by a set of analogue input and output lines 25. A visual display unit and terminal 26 may be connected to the computer 16 through a serial link 27.

Each of the primary control actuator assemblies 18, 19 and 20 includes an actuator 12, load cell 13, linear position transducer LVDT, and servo drive 14 as illustrated in Figure 1. The actuator 12 may, in the case of assembly 18, be connected to a control column 11. The actuators in the assemblies 19 and 20 are connected to other primary flight controls (not shown). The servo drive in each of the primary assemblies supplies an electrical analogue position signal on the line 23, and receives a electrical analogue force demand signal on the line 24. The servo valve SV is controlled by the servo drive 14 so as to achieve matching of the load cell output to the force demand signal. The analogue position signal supplied by the assembly is converted into digital form in a 16-bit analogue to digital converter in a 16-bit converters circuit 28.The resulting digital position signal is supplied over a bus 29 to a channel input/output circuit 30 from which the digital position signal passes to a channel processor circuit 32 over a channel processor bus 31. Each combination of a channel processor circuit 32, channel input/output circuit 30, 16-bit converters circuit 28 and analogue lines 23 and 24, the interconnecting buses, and an actuator assembly, is referred to herein as a primary control loading channel. Similarly, the combination of a channel processor circuit 32, a channel input/output circuit 30', an extended multi-bit bus 33, a converters circuit 28', analogue connections 25 and the secondary actuator assembly 21 are referred to herein as a secondary control loading channel.

In each primary control loading channel, the processor circuit 32 supplies a digital force demand signal over the bus 31 to the channel input/output circuit 30 which transfers the signal to the bus 29 and thus to the 16-bit converters circuit 28 where the digital force demand signal is converted into an analogue force demand signal which is supplied over the analogue line 24 to the respective primary actuator assembly.

Each channel processor circuit 32 includes a program stored in EPROM which computes the force demand signal on the basis of a mathematical model of the primary control simulated by the respective channel, and values supplied by the actuator assembly and the host computer for parameters such as control position, autopilot demand, and aircraft hydraulic supply data, as illustrated for the column control in Figure 1, or other parameters, depending on the control simulated.

Each channel input/output circuit 30 includes two 12-bit analogue to digital converters which receive respectively the analogue position signal from the actuator assembly 18, 19 or 20, and the output analogue force demand signal from the 16-bit converters circuit 28. The digital signals provided by the 12-bit converters are used by a self-testing program stored in EPROM in the processor circuit 32. An area of RAM is included in each channel input/output circuit 30 for storing the digital position signal provided by the 16 bit converters circuit, and the 12-bit test signals converted directly from the analogue signals on the lines 23 and 24.

The host computer (not shown) is a flight simulator computer and provides data relating to autopilot demand, aircraft hydraulic supply, and other parameters needed by the four control loading channels in simulating the behaviour of the three primary controls and one secondary control. The computing frame rate of the host computer is 30 Hz. At the beginning of each host frame, the hose interface 17 receives a command from the host to initiate a transfer of data from a data link interface 35 in the controls simulation computer 16. The data link interface 35 includes a RAM of 1024 x 16 bits capacity which contains data relating to the activity of each control loading channel, organised channel by channel. When the host has read this data, the host, via the host interface 17, writes fresh values for the required parameters into the RAM of the data link interface 35.As soon as the writing operation has ended, the data link interface issues an interrupt signal to a microprocessor in a crosstalk processor circuit CPUX. The crosstalk processor circuit includes EPROM holding a crosstalk program which the crosstalk microprocessor executes in response to the interrupt signal from the data link interface 35. In accordance with the crosstalk program, the crosstalk microprocessor block moves data from the RAM of the data link interface 35 to areas of double buffered RAM on each channel input/output circuit 30 and the channel input/ output circuit 30'. The crosstalk microprocessor then issues a command to the channel input/output circuits 30 and 30' to interchange areas of their double buffered RAMs. The crosstalk microprocessor then block moves data from newly accessible areas of these double buffered RAMs to the RAM in the data . link interface 35.Thus at the beginning of the next host frame, fresh channel data is ready in the data link interface 35 to be read by the host.

Figure 3 shows schematically the double buffered RAM of any one of the channel input/output circuits 30 or 30', and part of the control circuitry therefor. The RAM is divided into two areas designated RAM AREA 1 and RAM AREA 2, 36 and 37 respectively. Each channel input/output circuit 30 or 30' is connected to the crosstalk processor circuit CPUX by a crosstalk bus XB, and to the respective channel processor circuit 32 by the respective bus 31. The buses XB and 31 contain address, data and control lines.

Within each channel input/output circuit there are two buffers for the address lines, for the data lines and for the control lines from each bus. In Figure 3, the crosstalk bus XB address lines 38 are connected to two buffers 39 and 40, the crosstalk bus XB data read and write command signals XRD(-) and XWR(-) are supplied to two buffers 44 and 45, where (-) indicates the signals are active when low. The bus 31 from the respective channel processor circuit 32 has address lines 46 connected to two buffers 47 and 48, data lines 49 connected to two buffers 50 and 51, and supplies read and write command signals CRD(-) and CWR(-) to two buffers 52 and 53.Control logic is provided to ensure tht only the following pairs of these buffers can be enabled at any time: address buffers 39 and 48 or address buffers 40 and 47; data buffers 42 and 51 or data buffers 43 and 50; read/write buffers 44 and 53 or read/write buffers 45 and 52.

A control signal AR1/AR2(-) is generated to determine which of the alternative pairs of buffers are enabled. It is arranged that the pairs of buffers operate in two alternative groups: buffers 39, 48, 42, 51, 44 and 53, or buffers 47, 40, 50, 43, 52 and 45. It will be seen from Figure 3 that this arrangement ensures that either RAM AREA 1 is accessed by only the crosstalk bus XB and RAM AREA 2 is accessed by only the channel processor bus 31, or RAM AREA 1 is accessed by only the channel processor bus 31 and RAM AREA 2 is accessed by only the crosstalk bus XB. Thus it can be arranged that RAM AREA 1 is read and written to by the crosstalk processor circuit CPUX while RAM AREA 2 is read and written to- by the channel processor circuit 32, and vice versa.The control signal AR1/AR2(-) is produced by a D flip flop 54 which receives as its D input a flag signal EX indicating that the crosstalk processor circuit CPUX has finished-writing to the control loading channels and, as its clock signal, a real time clock signal RTC from the channel processor circuit 32. The control signal AR1/AR2(-) is supplied directly to the enable inputs of buffers 39, 48, 44 and 53, and through an inverter 55 to the enable inputs of buffers 45 and 52, and through an inverter 56 to the enable inputs of buffers 40 and 47. When the control signal AR1/AR2 (-) is low, the buffers 39, 48, 44 and 53 are enabled. When the control signal AR1iAR2(-) is high, the buffers 40, 47, 45 and 52 are enabled.

Figure 4 shows the logic circuit which controls the enabling of the data buffers 42,43, 50 and 51. The enable inputs of these buffers are connected to the outputs of a multiplexer 57 which may be a type 74LS158 circuit. The multiplexer 57 has four outputs 1Y, 2Y, 3Y and 4Y which are connected respectively to the enable inputs of the buffers 43, 42, 50 and 51. The eight inputs of the multiplexer 57 are arranged in two groups designated 1A, 2A, 3A and 4A, and 1B, 2B, 3B and 4B respectively. Of these inputs, 1A, 28, 3A and 4B are permanently connected to data ground as indicated. The control signal AR1/AR2(-) is supplied to the switching input of the multiplexer.When AR1/AR2(-) is low, the inputs 1A, 2A, 3A and 4A are inverted and connected to the outputs 1Y to 4Y respectively, and when AR1/AR2(-) is high, the inputs 1B to 4B are inverted and connected to the outputs 1Y to 4Y respectively. The data buffers 42, 43, 50 and 51 are enabled by a low signal, and may be of the type 74LS245. Consequently, when AR1/AR2(-) is low, buffers 43 and 50 are disabled by the ground levels at inputs 1A and 3A, and when AR1/AR2(-) is high, buffers 42 and 51 are disabled by the ground levels at inputs 2B and 4B.

The multiplexer inputs 1B and 2A, which can be connected to the buffers 42 and 43 which control the passage of data between the crosstalk bus XB and the RAM areas 36 and 37 respectively, are both connected to the output of an AND gate 58 having two inputs. One input of the gate 58 is driven bythe output of a comparator 59 which compares addresses on four address lines XBCHA of the crosstalk bus XB with a unique four bit address stored in a manually settable switch 60, this unique address being the address for the channel containing the multiplexer 57. When the address on the lines XBCHA matches the unique stored address, the comparator produces a high output signal, so that the AND gate 58 allows the signal on its input to pass through to the multiplexer inputs 1B and 2A.The crosstalk bus read and write command signals XRD(-) and XWR(-) are supplied respectively to two inputs of an OR gate 61 with inverted inputs. In correct operation, XRD(-) and XWR(-) are never both active at the same time.

When neither XRD(-) nor XWR(-) is active, the gate 61 receives two high inputs signals and produces a low output signal which appears at the multiplexer inputs 18 and 2A if the AND gate 58 is enabled by the comparator 59. If either XRD(-)-or XWR(-) is active, the gate 61 produces a high output which appears at the multiplexer inputs 1 B and 2A if the AND gate 58 is enabled. The status of the control signal ARD1/ AR2(-) determines whether the buffer 42 or the buffer 43 receives the inverted output of the AND gate 58. Thus if there is a read or a write command signal on the crosstalk bus )(B, one of the two data buffers 42 and 43 is enabled.

The multiplexer inputs 3B and 4A are both connected to the output of an inverter 62 driven by-the output of a decoder 62 which may be a programmed logic array. The decoder 63 is connected to a number of lines of the channel processor bus 31 to receive multibit input signals. One such multibit signal, termed DBRAM ENABLE, is decoded by the decoder 63 to produce a low active output signal which is supplied to and inverted by the inverter 62. The channel processor circuit 32 issued DRAM ENABLE whenever data is to be written to or read from the double buffered RAM of the channel input/output circuit. Hence whenever DBRAM ENABLE is active, one of the two data buffers 50 and 51, depending on the status of AR1/AR2(-), is enabled.

Since data must be both written to and read from the double buffered RAM, the data buffers 42, 43, 50 and 51 are bi-directional buffers and have respective direction signal inputs. The direction signal inputs of the crosstalk bus data buffers 42 and 43 are both connected to the output of an inverter 64 driven by the crnsstalk write command signal XWR(-)- so that the buffers 42 and 43 are set to pass data from the crosstalk bus data lines 41 to the double buffered RAM when the write command signal XWR(-) is active, and are set to pass data from the double buffered RAM to the crosstalk bus data lines 41 when the write command signal XWR(-) is not active.Similarly the direction signal inputs of the channel processor data buffers 50 and 51 are both connected to a channel processor has line supplying a direction control signal DT/R(-) which sets the buffers 50 and 51 to pass data from the channel processor bus data lines 49 to the double buffered RAM when the channel processor write command signal CWR(-) is active, and sets the buffers 50 and 51 to pass data from the double buffered RAM to the channel processor bus data lines 49 when the channel processor read command signal CRD(-) is active.

As shown in Figure 3, RAM AREA 1 has address inputs connected to the outputs of both address buffers 39 and 47, data pins connected to one set of input/output pins of both data buffers 42 and 50, and read and write inputs connected respectively to the outputs of both buffers 44 and 52. Similarly, RAM AREA 2 has address inputs connected to the outputs of both address buffers 40 and 48, data pins connected to one set of input/ output pins of both data buffers 43 and 51, and read and write inputs connected respectively to the outputs of both buffers 45 and 53.

Since it does not matter whether the crosstalk processor has access to the RAM AREA 1 of each chan nel and the channel processors have access to the RAM AREA 2, or vice versa, the flip flop 54 is allowed to power up in either condition.

In operation, during the interrupt program of the crosstalk processor, assuming that the crosstalk bus XB is initially coupled to the RAM AREA 1 in each channel input/output circuit 30 or 30', the crosstalk processor first block moves data from the RAM of the data link interface 35 to the RAM AREA 1 in the channels. In this way, new values provided by the host computer are transferred to the appropriate control loading channels. Having completed this transfer of data to the double buffered RAMs, the crosstalk processor issues the end of crosstalk flag signal EX and the flip flops 54 in each channel change state at the respective next real time clock pulse. Thus the crosstalk bus XB now becomes coupled to the RAM AREA 2 in each channel input/output circuit 30 or 30'. The RAM AREAs 2 contain the most recent data from each channel.If the real time clock rates are not less than 256 Hz, the crosstalk processor waits 4 milliseconds after issuing EX and then block moves the data in the RAM AREAs 2 to the RAM of the data link interface 35. The data written to the double buffered RAM by the channel processor 32 in each channel includes all the data required by the host computer for monitoring the operation of the control simulation channels, and for use in other functions of the host computer as a flight simulator computer. The host computer may be a Gould SEL 32 minicomputer, in which case the host interface should be a Highspeed Data Interface, Model 9132 as described in Gould SEL Manual 303-329131-000.

The crosstalk microprocessor and the microprocessor of each channel processor circuit 32 may be an Intel iAPX86-10, 8 Megahertz type, designated the Intel 8086-2, with an 8284 circuit to generate the processor clock signal and a ready signal.

In the secondary control loading channel, the actuator assembly 21 supplies a load cell analogue output signal to the converters circuit 28' and receives an analogue position demand signal from the converters circuit 28'. The assembly 21 may comprise servo drive circuitry for an hydraulic actuator connected to a secondary flight control member. The converters circuit 28' includes an inner, position loop circuit, amplifiers and scaling circuits for analogue signals, a 12-bit analogue to digital converter for converting a scaled signal obtained from the load cell analogue output, and a 12-bit digital to analogue converter for converting a digital position demand signal, transmitted from the channel processor circuit 32 through the channel input/output circuit 30' and the bus 33, into the analogue position demand signal.

Auxiliary analogue force and position signals are passed through the circuit 28' and the bus 33 to the channel input/output circuit 30' to be converted for test purposes by means of 12-bit analogue to digital converters in the channel input/output circuit 30', as in the other circuits 30.

To simulate a mechanically split but normally closely coupled pair of primary controls such as the split control column of an L1011 aircraft, two primary channels may be coupled as shown in Figure 2 by a multi-bit bus 65 connecting the channel processor circuits 32 of the two channels. The multi-bit bus 65 includes 16 data lines and a write command line from each microprocessor to a 16 bit wide, 16 word long (each word being two bytes) FIFO in the channel processor circuit 32 of the other channel. The FIFO in each of the two channel processor circuits 32connected by the bus 65 is accessible to the microprocessor of that circuit 32 for reading, and receives an address qualified read command form this microprocessor. Each FIFO is reset in every channel processor frame after being read by the microprocessor of its channel processor circuit 32.The reset signals are developed by logic driven by the respective reading microprocessor. The interrupt driven control simulating program of each channel processor circuit 32 connected by the bus 65 includes the following operations: 1) Transfer up to 16 words from the FIFO of this circuit 32 to a predetermined area of buffer RAM of this circuit 32.

2) Write a clear FIFO flag to the reset logic of the FIFO of this circuit 32.

3) Transfer up to sixteen words from another predetermined area of the buffer RAM to the FIFO of the other circuit 32 through the bus 65.

In addition to its microprocessor, each of the channel processor circuits 32 has, in a constructed example, 4K bytes of workspace RAM, and two areas of EPROM, one containing the control simulation program and the other a monitoring and debugging program which includes a power-up and reset bootstrap jump command. A timer, for example an 8253 timer, in the circuit 32 is used to cause an interrupt in every processor clock interval, so that for a real time clock frequency of 512 Hz, the interrupt occurs every 1.95 milliseconds. This interrupt is used to cause the control simulation program to run. The monitoring and debugging program is run as a continuously looping background task.When the microprocessor is an Intel iAPX86-10, 8 megahertz type 8086-2, a hardware multiplier such as the Am29516 is included in the circuit 32 for 16 x 16 bits multiplication, since the microprocessor is not itself capable of floating point computation. The data inputs and outputs of the multiplier are connected directly to the multiplexed bus of the 8086-2 to minimise delays.

Each channel processor circuit 32 may be provided with a UART for an RS232 link to a VDU terminal (not shown) for monitoring and debugging the respective channel. The baud rate can be defined by the timer in the circuit 32. The monitoring and debugging background task program is then provided with two interrupt driven monitoring routines, the first, labelled Tx, running when the UART is ready to transmit a character to the VDU terminal, and serving to cause the microprocessor to take a first character out of a software first-in, first-out output queue and write this character to the UART, and the second, labelled Rx, running when a character arrives at the UART from the VDU terminal and serving to cause the microprocessor to read this character and to write it into an input buffer area of RAM.In each loop of the debugging program, RAM locations are inspected by the microprocessor and, if their contents have changed, the new contents are placed in the software first-in, first-out output queue for transmission to the VDU terminal through the UART. New values of parameters can be entered using this program. An interrupt controller, such as an Intel 8259A, is included in the circuit 32 to handle the monitoring the debugging interrupts, and two others. The four interrupts thus handled are: Rx: the interrupt from the UART indicating that a character has been input from the RS2321inked terminal and is to be read by the channel microprocessor.

Tx: the interrupt from the UART indicating that the UART is ready to receive a character for transmission through the RS232 link.

Real Time Clock interrupt: received from the timer indicating that a new channel processing frame must start.

Real Time Clock Slave interrupt: received from the timer of another channel processor circuit 32 to which this channel processor circuit is connected by the bus 65 and indicating that a new channel processing frame must start.

The last two of these interrupts are alternatives.

The crosstalk processor circuit CPUX includes, in addition to its microprocessor, two sets of bus tranceivers for connection respectively to the bus to the data link interface 35 and the crosstalk bus XB, an interrupt controller, a counter time, a UART for connection to the serial- link 27, clock and wait state generators, an area of RAM for interrupt vectors and workspace, and an area of EPROM containing a boots- trap address, monitoring and debugging programs, and a crosstalk program which controls the transfer of data between the data link interface 35, and the channel input(output circuits 30 and 30', and address latches and an internal control and data bus that connects the circuit CPUX to a data entry panel 66.The data entry panel 66 has two ranks of thumbwheel switches, four seven-segment displays, a plurality of other switches and a light emitting diode (LED). The internal bus (not shown) from the crosstalk processor circuit CPUX is connected to the data entry panel 66 to multiplexers connected to the channel processor circuits 32 through the crosstalk bus XB and to the switching and display components of the panel 66.

The background task program of the crosstalk processor circuit CPUX is a modified version of the program used in the channel processor circuits 32. It has memory-mapped access to an address space allowing it to examine locations in all of the channels' double buffered RAMs and the 1K words RAM area of the data link interface 35.

In addition the background task program includes the polling of address, data and control latches of the data entry panel 66 and the subsequent actions of fetching and changing data in the channel processor circuits 32.

As well as the Tx and Rx interrupt routines, another interrupt routine is included to handle keyboard eavesdropping in which the crosstalk microprocessor checks each character transmitted to a channel mi croprocessor from the VDU terminal 26 and, if a 'change CPU' control character is entered at the VDU terminal 26, which the monitored channel microprocessor ignores), the crosstalk microprocessor takes the next character entered at the terminal 26 as a new channel number, cuts the present VDU/channel CPU link, connects itself to the microprocessor of the new channel, issues a 'refresh page' command, cuts the link between the channel and crosstalk microprocessors and connects the terminal 26 to the microprocessor of the channel by controlling the multiplexers in the data entry panel 66.

When the data link interface 35 issues an interrupt to the crosstalk processor circuit CPUX, the crosstalk microprocessor carries out the crosstalk program described hereinbefore.

The data entry panel 66 provides the facility for examining single memory locations throughout the control loading system and changing the values held therein. To call up a memory location, a number allocated to the channel required is entered on a 'CPU NO' thumbwheel switch of the panel 66. The address of the location then dialled up on four 'ADDRESS' switches of the panel 66. An 'ENTER ADDRESS' button on the panel 66 is pushed, which sets an interrupt. The microcomputer of the crosstalk processor circuit CPUX responds by communicating with the appropriate chnnel microprocessor via the crosstalk bus XB. The crosstalk microprocessor requests the chnnel processor circuit 32 for a readout of data held in the requested address. On receiving the information, the crosstalk microprocessor writes hex data to the seven-segment display latches.A similar routine is provided for entering data; data is first dialled up on thumbwheel switches, entered using the push button and then the crosstalk microprocessor instructs the channel microprocessor to alter the data held in the addressed location.

To implement keyboard eavesdropping the crosstalk processor configures a multiplexer so that at all times it will receive an Rx interrupt whenever a key is depressed. On occasions when the VDU terminal 26 connection is directed through to one of the channel microprocessor circuits 32 the crosstalk processor ignores all but the 'control R' character. On receipt of this the crosstalk processor circuit CPUX interprets the next character as the requested channel number, causing it to write to the multiplexers' address latches so as to redirect the link, connecting the VDU terminal 26 with the microprocessor of the newly selected channel. A character other than that for a valid channel number causes the multiplexers to be configured in such a way as to connect the VDU terminal 26 with the crosstalk processor.

Claims (8)

1. Control apparatus for an actuator, the apparatus including a processor adapted to compute a value for an output command signal for controlling the actuator in accordance with a predetermined mathematical model, the processor being coupled to means for supplying data representative of at least one operating variable of the actuator, means for supply an output command signal to the actuator, the output command signal having the said computed value, and a store having interchangeable areas in which data processed by the processor and data to be processed by the processor can be separately stored, the apparatus further including means for causing the interchangeable areas to interchange, and means for reading data processed by the processor and stored in the said store and for writing data into areas of the store for data to be processed by the processor, whereby data relating to parameters independent of the actuator can be supplied to the processor through the said store, such parameters being determined by the said mathematical model.

2. Control apparatus according to claim 1, wherein the said store is a double buffered RAM arrangement having two interchangeable areas.

3. Control apparatus according to claim 1 or claim 2, wherein the said means for reading data and for writing data includes a further processor.

4. Control apparatus according to claim 3, wherein the further processor is adapted to transfer data processed by the first said processor from the said store to an interface store, and to transfer data from the interface store to the said store having interchangeable areas, the transfers of data being carried out as alternate operations.

5. Apparatus for controlling a plurality of actuators, the apparatuses comprising a plurality of control apparatus according to claim 1 or 2, wherein the said means for reading data and for writing data includes a further processor which is adapted to transfer data processed by each of the other said processors from the respective stores to an interface store, and to transfer data from the interface store to each of the said respective stores, the transfers of data being carried out as alternate operations at each of the said respective stores.

6. Apparatus according to claim 5, wherein the interface store is adapted to be coupled to a host computer.

7. A flight controls simulator comprising apparatus according to claim 5 or 6.

8. A flight controls simulator substantially as described hereinbefore with reference to the accompanying drawings.