GB2173662A - Radar signal processor - Google Patents

Abstract

Discriminating wanted signals from noise in radar signal processors is generally achieved by a single threshold crossing detector and an associated pulse-to-pulse integrator. Strong signals, however, require less integration than weak signals to achieve a specified detection probability: this specification discloses a multi-level threshold crossing detector (13, 14, 15, 16) with associated pulse-to-pulse integrators (25) which integrate weak signals over many pulses and stronger signals over fewer pulses. <IMAGE>

Description

SPECIFICATION Radar signal processor The present invention is concerned with radar signal processing particularly for pulse radar.

Pulse-to-pulse integrators are well known for pulse radar systems. The beam width of a radar antenna is normally such that a target is exposed to a number of successive radar pulses as the beam scans by. Pulse to pulse integration techniques integrate the radar returns in successive intervals between radar pulses to improve the signal to noise detection performance of the radar.

Some well known forms of integrator are described in Introduction to Radar Systems by Skolnik, second edition, published 1981, pages 388 to 392.

Normally with such integration systems, the received radar video is first threshold detected to provide a logic "1" when the video exceeds the threshold level. The resulting stream of logic "1"'s and "0"'s is then integrated over successive pulse repetition periods. However, the quantisation of the radar return into just two levels (binary quantisation) using a single threshold detector results in a loss of about 1.5 to 2 dB in signal-to-noise ratio as compared the theoretical ideal for post detection integration (i.e. integration of the radar returns after detection from the received radio frequency signals).

This loss of signal-to-noise ratio performance can be reduced if the received radar video is quantised into more than two levels. This can be done using a plurality of threshold detectors set at different threshold levels each then feeding respective pulse to pulse integrators.

Apart from the above lost detection sensitivity when using 1 bit processing, there is a need in certain forms of radar equipment, particularly in the fields of remote sensing, to process and then display a range of amplitude levels to convey the texture of the target. For example, the higher Radar Cross Section parts on a ship may be picked out if the ship is mapped in sufficientspatial resolution, to perceive the elevated bridge from the deck.

According to the present invention, radar signal processing apparatus for pulse radar, comprises a multi-level threshold detector providing a plurality of binary output signals indicative of analogue radar video exceeding respective different threshold levels, a respective pulse-to-pulse integrator for at least a plurality of the binary output signals from the multi-level threshold detector, each said integrator integrating over a respective number of radar pulses and the number of pulses for the integrator integrating the binary output signal for a low said threshold level being greater than the number of pulses for the integrator integrating the binary output signal for a relatively higher said threshold level, and means combining the integrated binary signals from said integrators to provide an indication of detected radar targets.

It can be shown that the probality of detection of a target in a signal processor employing pulse-topulse integration depends both on the mean signalto-noise ratio of the radar return prior to integration and the number of pulses over which integration is carried out. Thus, for a constant probability of detection (of say 90%) a relatively strong radar return with a high signal-to-noise ratio requires relatively fewer pulses of integration, whereas a radar return having a signal-to-noise ratio of perhaps -1 dB may require integration over 100 successive radar pulses.

The present invention makes use of this fact by employing fewer stages of integration for the radar returns which exceed the relatively higher threshold levels, therefore having a relatively higher signal-tonoise ration. The use of such shorter integrators, integrating over fewer successive radar pulses, provides a substantial saving in the hardware cost, complexity and power dissipation of radar signal processors.

Conveniently, each said integrator integrates over a different number of radar pulses from the other integrators, said respective numbers of pulses being selected so that all the integrators provide substantially the same probability of detection.

An example of the present invention will now be described with reference to the accompanying drawing which shows a simplified block schematic diagram of a signal processor embodying the principles of the present invention.

In the figure, detected radar video from a radar receiver is supplied on a line 10 via a video amplifier 11 and a scaling potentiometer 12 to a series of threshold detectors 13 to 16. In the drawing the threshold detectors are shown as comparators which receive the radar video on one input and receive on their other inputs respective voltage levels from a potential divider network 17. The threshold detectors 13 to 16 are each arranged to produce a binary output signal on respective output lines 17 to 20 which is a logic "1" when the radar video signal exceeds the respective threshold level from the potential divider 17.

It will be appreciated that the video amplifier 11, scaling potentiometer 12 and threshold detectors 13 to 16 in association with the potential divider network 17 are illustrated in the figure in a much simplified form. These may be constituted by proprietary items or an Analogue to Digital converter.

The detailed design of these circuits is however well within the ability of the skilled worker in this field and forms no part of the present invention.

The respective binary output signals from the threshold detectors 13 to 16 are fed to four corresponding pulse-to-pulse integrators indicated generally at 21 to 24. The illustrated form of integrator comprises one or more delay units 25 connected in series. Each delay unit 25 is arranged to have a delay corresponding to the pulse repetion period of the radar apparatus so that the output signal from each delay unit is the binary signal for the pulse repetition period immediately before that of the signal fed to the input of the delay unit. In this way, the binary signal for a particular range in successive pulse repetition periods is provided simultaneously at the input and the output of a particular delay unit.

Considering the upper most integrator 21 in the figure, there is shown only a single delay unit 25 and a summing unit 26 producing a signal on a line 30 corresponding to the sum of the binary signal from the output of the delay unit and the binary signal directly from the upper most threshold detector 13 supplied to the input of the delay unit. It can be seen therefore, that the integrator 21 integrates over only two successive pulses of the radar which may be sufficient to provide the desired probability of detection for radar returns which exceed the highest threshold level from the potential divider 17.

The second integrator 22, has two delay units 25 connected in series and the output of each delay unit is summed together with the input to the first delay unit directly from the threshold detector 14 by the summing unit 27. Thus, integrator 22 integrates over three successive pulses which may be sufficient to provide the desired probability of detection for the second threshold level from the potential divider 17.

The integrators 23 and 24 similarly include additional delay units 25 providing for integration over four and five successive pulses respectively.

The integrated output signals from the integrators 21 to 24 are combined together to provide an indication of detected radar targets such as in a display unit 34.

In one arrangement, the output signals from the various integrators may be used to control the brightness of a respective colour of a multi-coloured display so that targets detected at the corresponding different threshold levels are marked on the display in different colours. Alternatively, the output signals from the different integrators may themselves be converted to produce a signal analogue single having a magnitude corresponding to the threshold level at which the radar return has been detected and integrated. Thus, radar returns indicated by signals from integrator 21 may be marked on the display at maximum brightness, whereas returns only detected at lower threshold levels may be marked with lesser brightness.

A simplified multiple thresholding and pulse-topulse integration processing system has been described to demonstrate the principles embodied in the present invention. In practical embodiments, many more threshold levels may be employed with corresponding additional numbers of integrators integrating over larger numbers of pulses. The delay units 25 may be embodied as digital delay units in the form of shift registers with each delay unit comprising a shift register with as many bits as desired range intervals in one range sweep of the radar between radar pulses and being clocked at a rate synchronised with the radar pulse repetition frequency.

Anotherform of integrator which may be employed in embodiments of the present invention comprises a binary counter for each range gate of the radar which is clocked by signals from a respective threshold detector indicating a radar return exceeding the threshold in that range gate.

Such a counter may operate as a m out of n integrator which is arranged to provide a target indication if there are radar returns exceeding the threshold in the respective range gate in a number m out of a total n successive pulse repetition periods.

The optimum value of m for a particular number of sample pulses is selected in accordance with known criteria to provide the best detection probability. The size of the counter and controlling circuitry is dependent on the number of pulses over which the integration is to be continued. Separate counters and associated circuitry are required for each range gate at each detection threshold level. By employing relatively smaller counters for integration over fewer successive pulses for the higher detection threshoids, substantial hardware savings are possible.

Claims (2)

1. Radar signal processing apparatus for pulse radar, comprising a multi-level threshold detector providing a plurality of binary output signals indicative of analogue radar video exceeding respective different threshold levels, a respective pulse to pulse integrator for at least a plurality of the binary output signals from the multi-level threshold detector, each said integrator integrating over a respective number of radar pulses and the number of pulses for the integrator integrating the binary output signal for a low said threshold level being greater than the number of pulses for the integrator integrating the binary output signal for a relatively higher said threshold level, and means combining the integrated binary signals from said integrators to provide an indication of detected radar targets.

2. Radar signal processing apparatus as claimed in claim 1 where each said integrator integrates over a different number of radar pulses from the other integrators, said respective numbers of pulses being selected so that all the integrators provide substantially the same probability of detection.