GB2172718A - Division of binary numbers - Google Patents

Abstract

A divider system for performing a series of division computations comprises a cascade of subtraction stages (30 Fig. 4) in which binary division is performed in stepwise fashion. In each stage, e.g. (a)-(f), the divisor e.g. 0101 is subtracted from the dividend which may be the same dividend as from the previous stage if the previous stage subtraction resulted in a borrow or the result from the previous subtraction stage if no borrow resulted from the previous stage subtraction. The "borrow" and "no- borrow" results from each stage are correlated with the original dividend/divisor input to the first stage and represent the required quotient for the respective dividend/divisor pair, taking the value "0" for a "no-borrow", "1" for a "borrow". At each stage, the divisor and dividend are relatively shifted by one place, in opposite senses (Figs. 1a, 1b). <IMAGE>

Description

SPECIFICATION Division of binary numbers This invention relates to the processing of numerical data in situations where a large number of divisions are required to be executed rapidly. Currently, as far as we are aware, the fastest hardware implementations of a divide circuit at integrated circuit level give a 16 by 16 bit divide in 3.6 microseconds and software implementations typically take between 1 and 10 microseconds. This is a severe limitation to the processing of numerical data and where large arrays of numbers are involved, it can lead to long delays before data can be processed if the necessary computing facilities are only available on a time-sharing basis.

The object of the present invention is to provide an improved method and circuitry for effecting division.

According to one aspect of the invention we provide a method of performing a series of division computations involving binary numbers, said method comprising: (a) providing, in digital form, electrical representations of said binary numbers; (b) storing said electrical representations in sets respectively comprising dividends and divisors; (c) sequentially extracting from said sets a series of dividend/divisor pairs and bringing the dividend and divisor of each pair into a predetermined relationship with respect to their digit positions; (d) sequentially subjecting each dividend/divisor pair to a multistage cycle of subtraction operations each involving subtractively combining the dividend or the result of a preceding subtraction stage with the divisor and generating and storing a binary digit whose value represents the polarity of the result of such subtractive combination, the number with which the divisor is subtractively combined in each stage being determined by the polarity of the result of the preceding subtraction stage and the arrangement being such that each dividend/divisor pair is subjected to the first subtraction stage prior to completion of the cycle of subtraction operations on at least one preceding dividend/divisor pair, and such that the relationship between dividend and divisor is displaced by one digit position per subtraction stage; and (c) correlating the binary digits generated during each subtraction stage with the respective original dividend/divisor pair.

In practice, the arrangement may be such that each dividend/divisor pair is subjected to one subtraction stage in response to transfer of the preceding dividend/divisor pair to the next subtraction stage whereby, in a steady state condition, each subtraction stage of the cycle is operating on a different dividend/divisor pair.

As used herein, "subtractively combining" is to be understood to refer to subtraction in a conventional arithmetical sense and also subtraction by the usual binary additive method using 2's complement arithmetic.

The sets of dividend and divisor numbers will generally each comprise a large number of values from which quotients are to be calculated; however, the invention includes within its ambit, the case where one of the sets may contain only one value.

According to a second aspect of the invention there is provided a computer programmed to operate in accordance with the method defined above.

According to a further aspect of the invention there is provided a divider system comprising: a plurality of stages each of which comprises first and second input registers respectively connected to receive binary dividend and divisor numbers from the preceding stage or, in the case of the first stage, from storage means for storing dividend and divisor numbers for which the quotients are required to be calculated, subtraction means for subtractively combining the contents of the input registers, means for generating a binary digit indicating the polarity of the subtraction, means for transferring either the contents of the dividend register or the result of the subtractor to the next stage (as the dividend for that stage) in dependence upon the polarity of said result, means for transferring the divisor to the next stage; means for extracting dividend and divisor pairs from said storage means and applying the dividend and divisor of each pair to the subtraction means of the first stage in a predetermined relationship with respect to their digit positions; means for effecting a one digit shift of the dividend and divisor relative to one another from one stage to the next; and means for recording the binary digits generated in each stage and correlating each set of binary digits with the respective dividend/divisor pairs inputted to the first stage.

Where fixed point arithmetic is employed, the initial relationship between the dividend and divisor of each pair may be such that the most significant bit (MSB) of the dividend is in alignment with the least significant bit (LSB) of the divisor. Alternatively, floating point arithmetic may be employed, ie. with the MSB of the mantissa of both dividend and divisor set in floating point arithmetic, and in this event the initial relationship may be one of alignment between the dividend and divisor, their exponents being processed separately and the difference therebetween being used subsequently to locate the correct position of the decimal point in the overall result.

In a presently preferred embodiment of the invention, said means for recording and correlating said binary digits comprise a series of shift registers each of which differs in length by one bit from the next and receives the binary digits from a respective one of said stages, the arrangement being such that the binary digits generated in each stage and associated with each divided/divisor pair are maintained and shifted in alignment in said shift registers whereby the final stages of the shift registers collectively provide, in parallel, binary outputs which constitute the result of effecting division of the respective initial dividend/divisor pairs.

To promote further understanding of the invention and illustrate further features and advantages thereof, the invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1A illustrates diagrammatically the initial relationship between dividend and divisor where fixed point arithmetic is employed; Figure 1B illustrates shifting of the dividend and divisor relative to each other: Figure 2 illustrates a sequence of operations involved in performing division of 11002 by 01012, which sequence may be employed by the method in accordance with the invention; Figure 3 is a block diagram illustrating one stage of a divider system according to the invention; Figure 4 is a block diagram illustrating pipelining of the stages shown in Figure 3; and Figure 5 is a more detailed diagram showing the interconnections between the components in Figure 3.

Referring to Figures 1A and 1B, a binary technique is used in the present invention for effecting division, which involves initially aligning the dividend and divisor so that the MSB of the dividend is level with the LSB of the divisor, as indicated in Figure 1A. The divisor is then subtracted from the dividend and the result of the subtraction determines the next step in the procedure. If a "borrow" is obtained, the MSB of the result will be O and if there is no borrow, the MSB of the result with be 1. If there is a borrow the next dividend (Figure IB) is the same as the previous one. If there is no borrow, the result of the subtraction is used as the new dividend in place of the previous one. The next stage is the same as the first except that the dividend and divisor are shifted one digit position relative to each other so that two bits overlap (see Figure 1B).The next subtraction is then executed and if this gives a borrow the next MSB of the overall result will be 0 and, if no borrow occurs, the next MSB will be a 1. The process can be repeated to any number of stages with each stage adding another bit to the overall result. In practice, the number of stages employed will be selected according to the precision required in the result.

Figure 2 illustrates division of 12 (binary 1100) by 5 (binary 0101). Thus, in Figure 2a, thefirst stage of subtraction is carried out with the MSB of the dividend in alignment with the LSB of the divisor. This produces a borrow (which corresponds to a MSB of O in the overall result) and, consequently, the dividend is carried forward unchanged into the second stage (Figure 2b) in which the dividend and divisor are shifted to a two bit overlap. Again a borrow results (giving a 0 for the next MSB of the overall result) and the dividend is transferred unchanged to the third stage (Figure 2c) in which a further one digit shift in position is imposed. This time the result of subtraction is positive which indicates that the corresponding bit of the overall result is 1.Because no borrow arises in the third stage, the result of the third stage is used as the dividend in the fourth stage and a further one digit shift in position is imposed. The procedure is repeated to the required precision and it will be seen that the six stages (a) to (f) in Figure 2 generate an overall result of 0010.01.

Referring now to Figures 3 and 4, implementation of the foregoing division technique is effecting by means of a pipelining technique involving a series of stages connected in a cascade as shown in Figure 4. Each stage is in the form shown in Figure 3 and comprises two N bit registers 10, 12 for storing dividends and divisors from a preceding stage, or in the case of the first stage from storage means containing arrays of dividends and divisors for which quotients are to be calculated.

Entry of new data into the registers 10, 12 is controlled by clock pulses on line 14. The outputs of the registers 10, 12 are connected to inputs A and B of a 2N bit subtractor 16 in such a way that the required relationship between dividend and divisor is obtained (as will be described more fully with reference to Figure 5). The output C of the subtractor is connected to one input of an N bit 2:1 multi- plexer 18, the second input of the multiplexer 18 being connected to receive the dividend from the register 10.The subtractor 16 provides a further output on line 20 which indicates whether or not the subtraction performed results in a borrow (ie. negative or positive) and this output is used to control the multiplexer 18 so that, in the event of a borrow, the dividend obtained from register 10 is made available at its output 22 for transfer to the following stage. In the absence of a borrow, the new dividend from the subtractor 16 is made available at the multiplexer output 22 for transfer to the next stage. The divisor held in register 12 is also available for transfer to the next stage via line 24.

Figure 3 is shown in somewhat simplified form for the sake of clarity. Figure 5 shows the third stage in greater detail for the case where the value of N is 8. Thus, it will be noted that the eight outputs of the dividend register 10 are connected to the eight least significant A inputs of the subtractor whereas the eight outputs of the divisor register 12 are connected to the 6th-13th least significant B inputs thereby creating the required shift between dividend and divisor for stage 3. The eight least significant outputs of the subtractor are connected to one set of eight inputs of the multiplexer, the other set of eight being connected to the dividend register 10.A reduction in the amount of hardware per stage can be effected by utilising the fact that the MSBs of the subtractor are not used except in the first stage; thus at stage 3 the subtractor need only be 2N-3 bits long, ie. 13 bits in the example described.

As shown in Figure 4, the stages are connected in cascade and are controlled by clock pulses on lines 14 so that each time a clock pulse is generated a new dividend/divisor pair is entered into stage 1 and the dividends and divisors in the subsequent stages are transferred from one stage to the next stage.

Thus, it will be seen that the pipeline comprising the cascade of stages can at any one time process a large number of divisions in stepby-step fashion. The results from each stage are represented by the borrow signals on lines 20 which may be 1 for a borrow and 0 for no borrow. These signals, after inversion by inverters 34, are entered into a bank of shift registers 30 each associated with a respective stage. Each shift register 30 is one bit shorter than the one preceding it, the longest being N-l bits long. The shift registers 30 are also clocked by the clock pulse source, via lines 32, so that their contents are shifted one place to the right each time a dividend/divisor pair enters the first stage.Because each shift register is one bit shorter than the preceding one, it will be appreciated that the nth stages (counting from the right) of the shift registers will all contain binary digits correponding to a respective initial dividend/divisor pair input to the pipeline. Thus, after a particular dividend/divisor pair has proceeded through the pipeline, the parallel outputs of the shift register 30 will collectively provide the result of the division, the N-1 bit long shift register providing the MSB and the final stage providing the LSB of the overall result.

Correlation between the input dividend/divisor pairs and the respective sets of binary digits progressing through the bank of shift registers 30 may be achieved by means of a counter 36 which may be preset with a count of -(N-l) and thereby provide a count of 1 after N clock pulses to signify arrival of the first result at the parallel outputs of the shift registers 30.

In the foregoing example, fixed point arithmetic is employed. However, the hardware can be simplified by making use of floating point arithmetic, ie. setting each dividend and divisor with the MSB of its mantissa in floating point arithmetic. In this way, subtraction of the dividend and divisor may be performed with their MSBs aligned in the first stage. The exponents of the dividend and divisor of each pair will be subtracted separately to provide a new exponent to be coupled with the mantissa of the result obtained after the initial dividend and divisor have undergone the pipelining procedure described above. Where floating point arithmetic is used, the subtractor in each stage need only be N bits long.

Typically, it is envisaged that the hardware may be implemented as a 24 by 24 bit divider stage (for use in a 32 bit floating point divider) using fast TTL running with a 10 MHz clock and providing results every 100 nsec once the pipeline has been filled.

Claims (7)

1. A method of performing a series of division computations involving binary numbers, said method comprising: (a) providing, in digital form, electrical representations of said binary numbers; (b) storing said electrical representations in sets respectively comprising dividends and divisions; (c) sequentially extracting from said sets a series of dividend/divisor pairs and bringing the dividend and divisor of each pair into a predetermined relationship with respect to their digit positions; (d) sequentially subjecting each dividend/divisor pair to a multistage cycle of subtraction operations each involving subtractively combining the dividend or the result of a preceding subtraction stage with the divisor and generating and storing a binary digit whose value represents the polarity of the result of such subtractive combination, the number with which the divisor is subtractively combined in each stage being determined by the polarity of the result of the preceding subtraction stage and the arrangement being such that each dividend/divisor pair is subjected to the first subtraction stage prior to completion of the cycle of subtraction operations on at least one preceding dividend/divisor pair, and such that the relationship between dividend and divisor is displaced by one digit position per subtraction stage; and (c) correlating the binary digits generated during each subtraction stage with the respective original dividend/divisor pair.

2. A method as claimed in Claim 1 in which the arrangement is such that each dividend/divisor pair is subjected to one subtraction stage in response to transfer of the preceding dividend/divisor pair to the next subtraction stage whereby, in a steady state condition, each subtraction stage of the cycle is operating on a different dividend/divisor pair.

3. A divider system comprising: a plurality of stages each of which comprises first and second input registers respectively connected to receive binary dividend and divisor numbers from the preceding stage or, in the case of the first stage, from storage means for storing dividend and divisor numbers for which the quotients are required to be calculated, subtraction means for subtractively combining the contents of the input registers, means for generating a binary digit indicating the polarity of the subtraction, means for transferring either the contents of the dividend register or the result of the subtractor to the next stage (as the dividend for that stage) in dependence upon the polarity of said result, means for transferring the divisor to the next stage; means for extracting dividend and divisor pairs from said storage means and applying the dividend and divisor of each pair to the subtraction means of the first stage in a predetermined relationship with respect to their digit positions; means for effecting a one digit shift of the dividend and divisor relative to one another from one stage to the next; and means for recording the binary digits generated in each stage and correlating each set of binary digits with the respective dividend/divisor pairs inputted to the first stage.

4. A divider system as claimed in Claim 3 in which said means for recording and correlating said binary digits comprise a series of shift registers each of which differs in length by one bit from the next and receives the binary digits from a respective one of said stages, the arrangement being such that the binary digits generated in each stage and associated with each dividedjdivisor pair are maintained and shifted in alignment in said shift registers whereby the final stages of the shift registers collectively provide, in parallel, binary outputs which constitute the result of effecting division of the respective initial dividend/divisor pairs.

5. A divider system as claimed in Claim 3 or 4 in which said means for extracting said dividend/divisor pairs and applying them to the subtraction means of the first stage is coordinated with said transferring means whereby a new dividend/divisor pair is applied to the first stage upon transfer of the previous dividend/divisor pair to the second stages.

6. A method of performing a series of division computations substantially as hereinbefore described with reference to the accompanying drawings.

7. A divider system substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.