GB2168879A - Differential phase shift keying detector - Google Patents

Abstract

A differential phase shift keying detector comprises a high Q bandpass filter (W) which provides an output to a phase comparator (X) which includes a VCO. Phase comparator (X) compares the VCO frequency with the data carrier and produces a signal proportional to phase difference. A phase shift causes a decrease in the VCO frequency and the signal is supplied to a low pass filter (Y) where the waveform is adjusted and a reference voltage is used to provide switching levels for a pulse squarer and pulse stretcher. Advantages over known circuits include the use of much fewer components, high noise immunity and a simple setting up procedure. <IMAGE>

Description

SPECIFICATION Differential phase shift keying detector This invention relates to differential phase-shift keying (DPSK) and the recovery of non-return to zero information from a DPSK encoded data signal.

The function of a DPSK detector is to detect a phase shift of e.g. 1800 in the data carrier and to output a logical zero for a phase duration of a predetermined number of cycles of the data carrier frequency (e.g. four cycles) each time this phase shift occurs.

At least in its preferred embodiment, the invention has advantages over circuits previously known in that it uses considerably fewer components and is consequently less expensive to manufacture, it has high noise immunity and has a simple setting up procedure.

According to the present invention, there is provided a DPSK-detector circuit comprising means for receiving a DPSK-modulated carrier input signal, means for generating oscillations, and means for comparing said oscillations with said input signal whereby a phase shift in the input signal can be detected.

A preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which Figure 1 is a circuit diagram of a DPSK detector according to the invention Figure 2 shows a series of diagrammatic waveforms A to E at points A to E marked in Figure 1.

Referring to Figure 1, the circuit is shown divided into four blocks labelled W, X, Y and Z. These are respectively: a high Q bandpass filter, a voltage controlled oscillator (VCO) and phase comparator, a low pass filter and a pulse stretcher. Standard symbols are used throughout for standard components as can readily be understood by one skilled in the art.

The integrated circuits Z28a, b and c are operational amplifiers such as CA224, Z27 is a phase comparator and voltage controlled oscillator such as CD4046B manufactured by National Semiconductor Corporation of 301 Harper Center, Horne Lane, Bedford, U.K. (or by RCA, or Motorola). Z20 is a flip-flop acting as an inverter.

The DPSK encoded signal is initially passed into the bandpass filter W which has a defined 0 and a centre frequency of 1200 Hz. The purpose of this filter is to eliminate as far as possible, the transient signals which appear during the 1800 phase shifts.

This region has to be as clean as possible to ensure the correct response from the phase locked loop. The desired waveform is shown by waveform A. The 1800 phase shift region is ideally a sinusoidal curve, but a lower frequency than the data carrier, so as to cause the phase shift. R78 is used to optimise the filter frequency response. In setting up, R78 is adjusted by feeding the data string 11111111 to the input and monitoring the signal at A.

The signal then passes to the phase comparator (X) at pin 14. The IC (Z27) includes a V.C.O. which has its output at pin 4 and is nominally set at a frequency of 1200 Hz for an input voltage of 2.5V by the selection of C92 (10nF) and R72 (100K). R72 is conveniently adjusted by entering the data string 1010101 and monitoring the waveform at C. This V.C.O. output is returned to one of the inputs for the phase comparator (pin 3). The phase comparator compares the V.C.O. frequency with the data carrier, sampling the signals two times per cycle, and produces a signal proportional to the phase difference shown by waveform B. Waveform B is not to the same time scale as the other waveforms so has been represented as having a discontinuous horizontal scale. Waveform B is a square wave of 2400 Hz but when a phase shift is encountered the duty factor (mark to space ratio) of the wave is changed.This output is applied to the V.C.O. input whereby the change in duty factor reduces the average voltage of the V.C.O. input hence decreasing its frequency and allowing it to follow the phase shift in the data carrier. The signal is now passed to the low pass filter (Y) where the waveform is adjusted such that the average peak is 0.3v above the 2.2v reference used and the phase changes are shown by the waveform being 0.5v below the 2.2 reference. The 2.2v reference is used so that the changes in signal level are sufficient to provide switching levels for the pulse squarer and pulse stretcher.

The low pass filter also removes most of the high frequency ripple. This produces the signal shown by waveform C.

After the signal has been filtered it is passed into the non-inverting input of Z28b. This op-amp (due to its very high gain) simply squares up the input signal. See waveform D.

At this stage the signal is put into a pulse circuit (Z). When a low appears on the output of Z28b the capacitor C96 discharges through the diode D9.

This therefore means that the output of Z28c goes high. Although the output form Z28b goes high after one cycle of the data carrier, the output from Z28c does not change. This effect is due to the time constant of RP3, R67 and C96. This is adjusted via R67 so that the capacitor charges up to 3.2v after 4 ms, at which point the next bit of data will arrive. The arrival bit will send the output of Z28c either high or low.

To improve the rise and fall of the output, the signal c from Z28 is inverted by Z20. The output from this flip flop is demodulated DPSK signal (i.e.

the data stream) see waveform E.

Further sample waveforms are given in Figure 3 which is a photograph taken from an oscilloscope.

The corresponding signals are given by the following key: 1. Trigger waveform (input data).

2. Output from Bandpass filter (A).

3. Output from low pass filter (C).

4. Phase comparator output (B).

5. Data stream (inverted) (E).

6. As (1).

7. Input to bandpass filter.

8. Output from pulse squarer (D).

9. As (4).

10. As (5).

The overlying grid is of no meaning. In waveform D, there is a change in duty factor at the phase change.

The above arrangement of a V.C.O. being controlled by a phase comparator (or the IC CD4046B) is an example of the use of a "phase locked loop".

The circuit described above operates at a baud rate of 300 bits/sec., but the circuit will operate at many different band rates with simple adjustments.

While the above arrangement describes the variation of the frequency of generated oscillations in order to follow the phase shift in the data carrier, it is envisaged that the phase of the generated oscillations might instead be changed to the same effect.

It will of course be understood that the present invention has been described above purely by way of example, and modifications of detail can be made within the scope and spirit of the invention.

Claims (10)

1. A DPSK-detector circuit comprising means for receiving a DPSK-modulated carrier input signal, means for generating oscillations, and means for comparing said oscillations with said input signal whereby a phase shift in the input signal can be detected.

2. A DPSK-detector circuit according to claim 1 further comprising means for altering the oscillations in accordance with the comparison made.

3. A DPSK-detector circuit according to claim 1 or 2 further comprising a band-pass filter of high Q factor to which the input signal is applied.

4. A DPSK-detector circuit according to claim 1, 2 oF 3 wherein the means for comparing the oscillations generated is a phase comparator.

5. A DPSK-detector circuit according to any one of claims 1 to 4 wherein the means for generating oscillations is a voltage-controlled oscillator.

6. A DPSK-detector circuit according to claims 4 and 5 wherein a signal from the phase comparator is used to control the voltage-controlled oscillator.

7. A DPSK detector circuit comprising means for receiving a DPSK modulated carrier input signal and means for generating oscillations of the same frequency as the carrier input, the latter means being capable of varying its frequency, in the event of a phase change in the carrier input, so as to restore a predetermined phase relationship between the carrier input and said oscillations generated, said means also producing a signal which indicates a temporary change in said phase relationship.

8. A circuit according to claim 7 wherein said predetermined phase relationship is maintained by means of a phase-locked loop.

9. A circuit according to claim 7 wherein said indicating signal produced is a signal used to control the oscillations generated.

10. A DPSK-detector circuit substantially as hereinbefore described with reference to the accompanying drawing.